JPS59188942A - Ic with high withstand voltage - Google Patents

Abstract

PURPOSE:To obtain an IC free from no erroneous operation in logic circuit by a method wherein a region between a high voltage circuit and a logic circuit as well as another region over the logic circuit are covered with another logic circuit and a signal line as well as the second conductive layer different from a conductive layer utilized for a bus bar through the intermediary of an insulating film exceeding 1mum thick providing this layer with ground potential for high frequency signal. CONSTITUTION:A P<+> type diffusion layer 20 comprising a high voltage circuit and an N<+> type source diffusion region 22 comprising a logic circuit are adjacently formed on the surface layer of a P type substrate 21 while overall surface is covered with an SiO2 film 23 wherein an opening is made and the film 23 is coated with the first Al wiring layer 16 abutting against the adjacent part and extending over the film 23. Said layer 16 is coated with a PSG film 23' exceeding 1mum thick on which the second Al wiring layer 17 is provided to be covered with an SiO2 film 23''. Later contact openings 31 and 32 are respectively made on the exosed part of said film 23' and the film 23'' to provide the wiring layer with ground potential for high frequency signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a high-voltage IC in which a high-voltage circuit and a control logic circuit are built into the same chip.

In display devices such as dot matrix type PDPs, fluorescent display tubes, etc., display is performed by supplying high voltage pulses of 100 V or more to a large number of electrode lines in a matrix forming a dot. I saved up this,
A number of driving high voltage switching circuits corresponding to the number of driving electrodes are required. In a large panel, the number of these electrodes becomes very large, so it is preferable to use a plurality of high voltage switching circuits integrated into ICs in terms of cost. recent years,
The technology of high-voltage ICs using the MO8 structure has progressed, and ICs with 16 or 32 circuits of high-voltage MOS switching transistors and control logic circuits built into a single chip have advanced.
C was developed.

In these ICs, in order to avoid malfunction of the logic circuit due to capacitive coupling between the high voltage transistor that supplies several hundred pulses and the logic circuit that handles pulse signals of about 5V,
An electrode layer is provided to shield high frequency signals. This electrode layer is made of the same metal layer as the low-resistance conductive layer that makes up the IC bus line, and it does not cover the logic circuit, but fills only the area between the high-voltage transistor and the logic circuit pull. do not have. Furthermore, the signal line connecting the high voltage transistor and the logic circuit is not covered with a shielding electrode layer. Therefore, in order to minimize electrostatic coupling between high-voltage switching transistors and logic circuits, the area of the shielding electrode layer must be set to a sufficient area (
I had to take it. In other words, in order to reduce the coupling capacitance between the drain output terminal of the high voltage switching transistor and various signal terminals of the logic circuit, the distance between these terminals is increased and the space between the high voltage transistor and the logic circuit is filled. It was necessary to make the metal layer absorb more of the electric lines of force extending from the high voltage output terminal.

The distance between these terminals depends on the pulse amplitude and pulse transition time handled by the high-voltage switching transistor. .This is an IC
In response to the need for larger and larger chips, restrictions are being placed on the number of circuits that can be included within a chip.

FIG. 1 shows a chip configuration diagram of a conventional high voltage IC. A signal line section 14 and a logic circuit 13 for sending signals from the /<RAD to the logic circuit and the /<RAD section into which external control signals are input.
area, high voltage MO8) transistor (12a112b,
12c, 12d, 12g, 12f) and signal lines (15a, 12f) connecting each high voltage transistor and the logic circuit 13.
15b, 15c, 15d, 15e, 15f) inside the chip 11k excluding the regions 15b, 15c, 15d, 15e, 15f), the above-mentioned shielding metal layer 1
6 is provided. In conventional high-voltage ICs, this shielding metal layer 16 is used for high-voltage transistors, logic circuit signal lines, and bus lines. It was manufactured in the same process as the conductive layer.

Therefore, the area shielded by such a conductive layer is 1. This is only the area between the high voltage transistor and the logic circuit. Therefore, the shielding effect on the logic circuit section is weak, and the higher the voltage of the pulse handled by the IC, the longer the distance l between the high voltage transistor and the logic circuit must be made sufficiently large, which leads to an increase in the chip area. Ta. Furthermore, if l is made small, the shielding becomes incomplete, and various signal lines of the logic circuit receive pulse induction of high voltage pulses from the output terminal of the high voltage transistor, causing the logic circuit to malfunction. This not only reduces the reliability of the IC, but also causes destruction of the high voltage transistor, which poses a practical problem.

It is an object of the present invention to eliminate the above-mentioned conventional drawbacks, and to form the region and the entire logic circuit area on an insulating film with a thickness of 1 μm or more, which is made in a separate process from the conductive layer used for bus lines and signal lines. By covering the second conductive layer with a second conductive layer and using it as a shielding electrode layer for high frequency signals, it is possible to obtain a high-density, high-voltage I'C without malfunction of the logic circuit.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a plan view showing an embodiment of the configuration of a high voltage IC according to the present invention. Note that the same numbers and symbols as in FIG. 1 represent the same components. Also, Fig. 3(a), (
i) is a cross-sectional structural diagram showing a part of the high voltage IC according to the present invention realized on a Si-based substrate. In one embodiment of the present invention, the second conductive layer 17, which is manufactured in a different process from the conductive layers used for bus lines and signal lines, has a thickness of 1 μm.
A plurality of high voltage transistors (1
28 to 12f) and the logic circuit 130 and the entire upper surface of the logic circuit section. In implementing the present invention, bipolar, MOS, ECL
, GaAs, etc., any IC structure may be used.
For the sake of convenience, the explanation will be given below assuming a configuration using the MO8 structure. Multiple horizontal high voltage MO8) transistors (1
2a to 12f) have a ring shape in which the drain is surrounded by the source region. A high voltage signal is typically taken out from its drain terminal. Such MOS transistors are usually arranged around the chip so that they can be easily bonded to lead terminals of a package. Therefore, such high voltage MO8) transistors (12a to 12f)
It is preferable in terms of area efficiency to arrange the low voltage logic circuit 13 for supplying a control signal to the gate of the transistor 8) between the regions occupied by the plurality of high voltage MO transistors. However, this does not limit the invention in any way.

In FIG. 2, the logic circuit 13 is arranged on top of the chip 11 in a row of high voltage MOS transistors (12a, 12b, 12).
An example is given in which they are arranged side by side between C) and a row of high voltage MO8 transistors (12d-12e-12f) arranged at the bottom of the chip 11. High voltage MO8) transistor (
Each gate control signal (12a=12f) is transmitted from a corresponding buffer circuit provided in the logic circuit 13 to 15a to 15a.
The signal is sent to each high-voltage MO8) transistor via the 15f signal line. Further, control signals necessary for operating the logic circuit 13 are inputted from the electrode pad section 14 and sent to the logic circuit 13 through the signal line section 14. The entire upper surface of the logic circuit of the chip configured in this way, high voltage MO
8) Cover the region between the transistors (12a-12f) and the logic circuit and the region between the band portion and the high voltage MO8) transistor with a metal layer 17. In FIG. 2, a metal layer 17 is overlapped with a portion of the high voltage transistors 12a to 12f in order to further enhance the shielding effect against high frequency signals. This metal layer 17 is shown in FIGS. 3(a) and 3(b) I
A structure like the one shown can be easily formed. now,
For convenience, the description will be made assuming that the IC is fabricated on a P-type Si semiconductor substrate. First, a high concentration region 20 of P is formed by thermal diffusion of poron in a field region in which a thermal oxide film formed on the top of the P type substrate 21 is opened.

Then, the n+ conductive layer 2 becomes the source part of a transistor constituting a logic circuit or a high voltage MO8) transistor.
2 is formed in a region where a part of the thermal oxide film on the P-type semiconductor substrate 21 is opened. This conductive layer 22 is usually made of phosphorus (P).
It is formed together with the drain region by thermally diffusing or ion-implanting impurities such as from the upper surface of the substrate 21.

Next, 5,000 to 6,000 people (7) formed polycrystalline Si, which will become the gate electrode of the transistor, through the necessary steps to form the channel region of the MOB) transistor.
After depositing the CVD 8 Ioz insulating film, the desired contact holes are drilled and the AI! A conductive layer 16 is deposited and patterned. Therefore, AI! conductive layer 16
Below is a SiO□ film 23 film type 3, which is a combination of a thermal oxide film of several thousand amps and a CVD 8i02 film of 5,000 to 6,000 amps. Next, a 1-2 μm thick phosphor glass film 2i is deposited and patterned. And AI! 16, a region 30 for making electrical contact is opened on the surface that will become the source electrode, and the second layer of AI! 7 pieces made of 1 film, patterned.

Further, a 5in2 film 23'' as a protective film is deposited by CVD, and a through hole 30 for taking out the electrode is opened.In an IC manufactured by such a process, the third
An element having the structure shown in Figure (a) is produced.

In this structure, the first metal layer AI! source electrode 16 of
Or the second metal layer AI! By setting any one of 17 to the ground potential for high frequency signals, the entire area of 17 shown in FIG. 2 is shielded from the high voltage switching pulse generation system. Also, the first layer of AI! A film 16 is formed, and a phosphorus glass film 23 of about 1 to 2 μm is formed thereon.
' of the source electrode 16, the AI! of the source electrode 16 is deposited. By opening only the back contact 631 so that the second layer AJ film does not come into contact with the surface and patterning the second layer conductive layer 16 by vapor deposition, an IC having the structure shown in FIG. 3(b) is obtained. . In this case, the second layer AI! I! Thousands of amps attached as a protective film to
About CVD5iO1! The through hole for taking out the electrode that is opened in the film 23''Ic is located between the area 31 where the phosphor glass film 23' has already been opened on the AJ screen of the source electrode 16 and the new second hole.
Holes are formed at two locations, one in the region 32 on the second layer Af film 17.

Then, electrodes are taken out to the outside through bonding wiring, and set to a ground potential for the same high-frequency signal outside the chip. Even with such a structure, the shielding effect obtained is the same as that of the structure shown in FIG. 3(a). still,
The thickness of the phosphor glass film 23' can be several μm. If the film thickness of the ring glass film 23' is increased in this way, the load capacitance seen from the various signal terminals in the logic circuit to the shielding electrode 17 will be equal to 9 times the substrate of the terminal whose signal line is the AJ electrode of the first layer. The capacitance can be reduced to less than half, and no major characteristic deterioration of the logic circuit occurs.

Also in the case of FIG. 3(a), it is possible to make the thickness of the phosphor glass film 23' several μm.

Therefore, the same effect as in the case of the structure shown in FIG. 3(b) can be obtained. It should be noted that the protective film 23'' does not need to be made of CVD SiO□, and may be made of phosphorus glass as a groove phase.

Since the shield electrode 17 formed as described above absorbs the lines of electric force of the high electric field extending from the high voltage MOS switching transistors 12a to 12f, no malfunction of the logic circuit occurs. Since it does not depend on the magnitude of the pulse amplitude handled by the high voltage switching transistor,
High voltage MO8) transistors 12a to 12f and logic circuit 1
3 can be made sufficiently small by d.

Therefore, it is very advantageous for IC implementation, and has high density and high voltage resistance.
C can be obtained. That is, even if the amplitude of the high-voltage switching pulse becomes large, l' remains constant, so there is no problem of reducing the number of circuits included in the chip as in the prior art.

Note that the shielding metal layer 17 can be provided between the high voltage MO8) transistors 12a and 12f and the pad portion 14, but since it is not possible to cover only the pad portion with the metal layer 17, this interval is l. ’ must be larger than ’.

However, since the signal line extending from the pad section to the logic circuit section 13 is covered with a shielding metal layer, the shielding effect is greater than in the conventional configuration, and the distance between the high voltage MO8) transistor and the pad section can be reduced. It is. In addition, the shielding electrode 17 is not limited to AJ, but P't
+Au-W* Any metal layer such as Mo or a silicided version thereof may be used. In short, it is sufficient to use a low-resistance metal layer. Furthermore, the oxide film 23
' is not limited to a phosphorus glass film, but may be a polyimide or other oxide film. Preferably, it is made of an insulating film with a low dielectric constant. Furthermore, the same effect can be obtained even if the shielding electrode 171C is supplied with a power supply potential instead of the ground potential.

FIG. 4 is a plan view showing the structure of another embodiment of the high voltage IC according to the present invention. In this embodiment, the same numbers and symbols as in FIGS. 1 to 3 represent the same components.

In FIG. 4, the first layer Af film is deposited on areas excluding high voltage transistors, logic circuits, pads, and signal lines,
Moreover, the ICC second AJ film 7 is attached to the logic circuit section, the signal line section, and the region between the high voltage transistor and the logic circuit 13. Even with this structure, I
It is clear that the same shielding effect as C can be obtained.

A detailed explanation will be omitted since it is clear from the above description.

As is clear from the above description, according to the present invention, it is possible to realize a highly reliable element without causing malfunction of the built-in logic circuit in a high-voltage IC that handles any high-voltage pulse. Further, even if the pulse amplitude to be handled increases, the high density of the IC will not be reduced, and the number of high voltage transistor circuits that can be integrated into the chip will not decrease. Therefore, although a high voltage of ±350 V is required for a driver such as an electrostatic printer, such a circuit can also be applied and has great effects. Furthermore, since the thickness of the insulating film under the shield electrode is set to about several μm, the capacitance between the signal line and the ground in the logic circuit is small, and the dynamic characteristics are not significantly degraded.

[Brief explanation of the drawing]

Figure 1 shows the chip configuration of a conventional high-voltage IC, Figure 2 shows the chip configuration of a conventional high voltage IC.
The figure shows an example of the chip structure of a high-voltage IC that is inventive. Figures 3 (a) and (b) are diagrams that show the structure of a high-voltage IC according to the present invention. High voltage resistance I according to the present invention
FIG. 4 is a diagram showing another example of the chip configuration of C. In each figure, 11: IC chips 12a, 12b, 12c, 12d, 12e, 12f:
High voltage transistor, 13: Logic circuit, 14: Pad, signal line, 15a, 15b, 15c, 15d, 15e, 15f:
Signal line, 16.17: Metal layer, 21: Semiconductor substrate, 20.22: Impurity layer, 23, 23, 23'': Insulating film 30, 31.32: Contact opening region. Fig. 1 Fig. 3 Fig. 0 Fig. 0 Pavilion

Claims (1)

[Claims] The area between the high voltage circuit part and the logic circuit part and the entire area above the logic circuit are made of a conductive layer that is used for signal lines and cross lines of the logic circuit through an insulating film with a thickness of 1 μm or more. A high voltage IC, characterized in that the IC is covered with a different second conductive layer, and the second conductive layer is set at a ground potential with respect to a high frequency signal.