JPH104561A - Video signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the processing unit to be compatible with the NTSC system and the PAL system, to suppress the scale of circuit configuration and to prevent frequency interference by multiplying medium value data with each of color difference signal data, selecting data and adding data based on a clock pulse whose frequency is 14.1875MHz. SOLUTION: An R system processing block 21 multiplies medium value data with red component color difference signal data RY to respectively obtain Ra-Rc and Rd being color difference signal data. The data are given to a selection output circuit 211, from which the data are selected and outputted based on the output of a hexadecimal counter 23 receiving a clock pulse whose frequency is 14.1875MHz. Thus, the output value is similarly processed by modulation with a chrominance subcarrier whose frequency is 4.43MHz. In a B system processing block 22, similarly data BY are modulated by selection output circuits 221, 222. The two kinds of modulated data are added by an adder 24 to obtain chrominance carrier signal data whose frequency is 14,1875MHz. Thus, the scale of circuit configuration is suppressed and longitudinal stripe noise due to frequency interference is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing method and a video signal processing device, and more particularly to an improvement in a device for performing balanced modulation of a color difference signal with a color subcarrier.

[0002]

2. Description of the Related Art In general, a composite video signal of a color outputted as a video is converted into a video signal R, G, B for each of color components representing three primary colors (red, green, blue) by a color difference matrix, parallel modulation, or the like. It is obtained by performing processing. These processes are called a color encoder, and are performed by a video signal processing device as shown in FIG.

[0003] A video signal source 40 such as a television camera or an RGB processor supplies a red, red,
Three types of video signals R, G, and B representing the three primary colors of green and blue are generated. The matrix circuit 41 that takes in these three types of video signals R, G, and B combines the video signals R, G, and B at a predetermined ratio (R: 30%, G: 59%, and B: 11%) to generate luminance. A signal Y is generated, and a luminance signal Y is subtracted from the video signals R and B to generate two types of color difference signals RY and BY. The balance modulation circuit 42 modulates the amplitudes of the two color subcarriers, which are 90 ° out of phase with each other, with the chrominance signals RY and BY, and combines them to generate a carrier chrominance signal. Then, the addition circuit 43 adds the luminance signal Y and the carrier chrominance signal, and further adds the composite synchronization signal and the color synchronization signal to generate a video signal. In addition, the synchronization signal generation circuit 4
4 generates horizontal scanning and vertical scanning synchronization signals based on a reference clock having a cycle determined for each television system, and supplies these synchronization signals to each unit to synchronize the mutual operations. Let it. The balanced modulation circuit 42
Are also generated from the reference clock by the synchronizing signal generation circuit 44. The standard of the frequency fSC of the chrominance subcarrier is determined by the signal transmission method, and the NTSC (National Television System) is used.
em Committee) method is about 3.58 MHz, PA
About 4.43 in L (Phase Alternation by Line) method
MHz.

In recent television camera systems and the like, there has been a shift from a conventional video signal processing apparatus using analog signal processing to a video signal processing apparatus using digital signal processing that is easy to adjust and has little deterioration of the video signal. Is underway. Correspondingly, the color difference signals RY, B-
The balanced modulation of Y is also performed by digital signal processing. Hereinafter, a method of digitizing a system for obtaining a carrier chrominance signal by balance-modulating the color difference signals RY and BY with a chrominance subcarrier will be described.

First, a frequency of 3.58 according to the NTSC system is used.
In order to process the chrominance signal RY based on the modulation of the chrominance subcarrier in the same manner as that of the chrominance subcarrier, as shown in the graph of FIG.
Using a (3.58 MHz × 4) clock as a sampling clock, (RY), 0,-(RY), 0, (R
−Y)... May be sequentially sampled. In addition, since the color difference signal BY is 90 ° out of phase with the color difference signal RY, to process the color difference signal BY similarly, 0, (BY), 0, − ( BY), 0,
.. May be sequentially sampled. Therefore, in order to generate a carrier color signal generated by adding these modulated color difference signals RY and BY, the frequency 1
Using a 4.32 MHz clock as a sampling clock, (RY), (BY),-(RY),-(BY)
It is sufficient to sequentially sample the sampling data Y). In the actual processing, a clock having a frequency of 14.32 MHz is used as a sampling clock from the beginning (RY), (BY),-(RY),-(B
-Y), the carrier color signal is generated by sequentially sampling the sampled data.

Incidentally, as described above, the color subcarrier (f
The frequency of sc) is defined by the following standards for each of the NTSC and PAL television systems. NTSC system: fSC = 3.579545 MHz PAL system: fSC = 4.43461875 MHz For this reason, when configuring a camera system, a frequency which is an integral multiple of fSC is used as a reference clock of the system. Incidentally, assuming that the frequency of the horizontal scanning is fH and the frequency of the vertical scanning is fV, it is defined as follows.

NTSC system: 4 · fSC = 910 · fH PAL system: 4 · fSC = 1135 · fH + 2 · fV However, if a system is configured to comply with these standards, NTSC and PAL greatly differ in fSC. It was difficult to standardize the system. So PA
It has been considered to use a reference clock defined by 4 · FSC = 908fH = 14.1875 MHz as the reference clock of the L system, and to make the system common with the NTSC system. However, in such a system, in order to obtain the original fSC corresponding to the PAL system, it is necessary to form a phase locked loop circuit with the FSC system clock and the fSC system clock so that their phases match each other.

[0008]

According to the conventional video signal processing method, it is necessary to construct a phase-locked loop circuit, so that the circuit size of an apparatus for implementing the method becomes large, and the clock of the FSC system is reduced. Since two types of clocks having different frequencies of the fSC system clock are used at the same time, interference between the two frequencies affects the analog system, causing a problem that vertical stripe noise easily occurs on the screen.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and has a first feature in that the present invention has an advantage in that a genuine wave having a modulation period of color information in a specific television system is provided. Means for generating intermediate value data corresponding to a value obtained by sampling a signal with a reference clock having a cycle shorter than the cycle thereof, and a color difference provided by each of the plurality of generated intermediate value data at timings according to the reference clock. Means for multiplying the signal data, and from the plurality of color difference signal data multiplied by the different intermediate value data, at a timing according to the reference clock, between a common multiple cycle of a cycle of the reference clock and a modulation cycle of the color information. Means for periodically selecting one piece of data in a predetermined order to generate carrier color signal data; Lies in comprising a means for suppressing the limit value or less of the carrier chrominance signal data when exceeding the limit value determined according to the luminance signal data corresponding to the difference signal data.

The second characteristic is that a value obtained by sampling a regular gen-wave signal having a modulation period of color information in a specific television system with a reference clock having a period shorter than that period is obtained. Means for generating the associated intermediate value data, and a predetermined order from a plurality of the generated intermediate value data at a timing according to the reference clock during a common multiple period between the period of the reference clock and the modulation period of the color information. Means for periodically selecting one piece of data, means for multiplying the selected intermediate value data by color difference signal data provided at a timing according to the reference clock to generate carrier color signal data, and means for generating the carrier color signal data. When the value to be represented exceeds the limit value determined according to the luminance signal data corresponding to the color difference signal data, the carrier color signal data is set to the limit value In that it comprises means for suppressing the lower, the.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video signal processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
First, a signal processing method used in the video signal processing device according to the embodiment of the present invention will be described. FIG.
FIG. 7 is a diagram illustrating a method of modulating a color difference signal with a color subcarrier having a frequency of 4.43 MHz corresponding to the PAL system using a reference clock of 875 MHz.

In order to generate a color subcarrier having a frequency of 4.43 MHz as digital data from a clock having a frequency of 14.875 MHz, as shown in FIG. 0, a, -b, -c, 1, -c,-
The intermediate value data may be allocated in the order of b, a, 0, -a, b, c, -1, c, b, -a, and 0 in accordance with each timing of the reference clock. The intermediate value data of a, b, and c are as follows: a = 0.923880０．９1-2 ^ -4 b = 0.707107 ≒ 1-2 ^ -2-2-2-5 c = 0.382683 ≒ 1 −2 ^ −1−2 ^ −3 (＾ represents a power). Therefore, these a,
If b, c, 0, and 1 can be generated, a chrominance subcarrier can be generated by digital / analog conversion (hereinafter, referred to as D / A conversion).

In order to process the digital data of the color difference signals RY and BY (hereinafter referred to as color difference data RY and BY) in the same manner as when modulated by a color subcarrier having a frequency of 4.43 MHz, In FIG. 3, the intermediate value data assigned to each timing of the reference clock should be output by multiplying the color difference signal data RY and BY. That is, the color difference data RY, BY are multiplied by the respective intermediate value data a, b, c, 1 to obtain Ra = RY · a, Rb = RY · b, Rc = RY · c, Rd = RY · 1 Ba = BY · a, Bb = BY · b, Bc = BY · c, Bd = BY · 1 are obtained, and these data are assigned at each timing of the reference clock in accordance with the assignment order of the intermediate value data shown in FIG. It will be good. For example, regarding the color difference signal data RY, 0, Ra, -Rb, -Rc,
Rd, -Rc, -Rb, Ra, 0, -Ra, Rb, R
.., -Rd, Rc, Rb, -Ra, 0,... Further, regarding the color difference signal data BY, considering that the phase difference with the color difference signal data RY is 90 °, −K · Bd, K · Bc,
K-Bb, -K-Ba, 0, K-Ba, -K-Bb,-
K-Bc, K-Bd, -KBc, -KBb, KB
a, 0, -K-Ba, K-Bb, K-Bc, -K-Bd
.. Are sequentially assigned. Note that K is a value for inverting positive / negative for each horizontal scanning period. FIG. 4 is a block diagram illustrating the configuration of the video signal processing device according to the embodiment of the present invention. In FIG. 4, the R-system processing block 21 modulates the color difference signal RY of the red component with the color subcarrier, and the B-system processing block 22 modulates the color difference signal BY of the blue component with the color subcarrier. doing.

The R-system processing block 21 adds (1-2 ^-) to the color difference signal data RY corresponding to the color difference signal RY.
4) Ra, Rb, and Rc, which are values obtained by multiplying (1-2 ^ -2-2 ^ -5) and (1-2 ^ -1-2 ^ -3), respectively, and the color difference signal data RY itself Rd and 0 are generated. Then, these positive and negative values are input to the first selection output circuit 211, and the frequency 1
4.1 Operate with 1875 MHz clock pulse 16
It is selectively output in a predetermined order based on the output value of the binary counter 23. The output order at this time follows the allocation order of the sampling data shown in FIG.

Therefore, the output value of the first selection output circuit 211 is 0, Ra, -Rb, -Rc, Rd, -Rc, -R
b, Ra, 0, -Ra, Rb, Rc, -Rd, Rc, R
.. b, -Ra, 0,..., which means that the chrominance signal RY has been subjected to the same processing as the modulation by the color subcarrier having the frequency of 4.43 MHz.

In the B processing block 22, Ba, Bb, Bc, B
The positive and negative values of d and 0 are input to the second selection output circuit 221, and are selectively output in a predetermined order based on the output value of the hexadecimal counter 23. The output order at this time also follows the sampling data allocation order shown in FIG. After that, the positive and negative values of the output value of the second selection output circuit 221 are input to the third selection output circuit 222, and the third selection output is performed based on the line selection pulse LP that is inverted every horizontal scanning period. Circuit 22
2 is selectively output. As a result, the output value of the third selection output circuit 222 becomes -KBd, KBc, KB
b, -K-Ba, 0, K-Ba, -K-Bb, -KB
c, K-Bd, -K-Bc, -K-Bb, K-Ba,
0, -K-Ba, K-Bb, K-Bc, -K-Bd
・ It becomes. Therefore, the color difference signal BY has a frequency of 4.43M.
This means that the same processing as that performed by modulating the chrominance subcarrier of Hz is performed.

The adder 24 adds the two types of data modulated by the chrominance subcarriers obtained by the above processing, thereby obtaining carrier chrominance signal data. This carrier chrominance signal data is output in a cycle in accordance with the frequency of 14.875 MHz, but is multiplied by the above-described intermediate value data as a coefficient. A carrier chrominance signal with a frequency of 4.43 MHz, equivalent to that modulated by the corresponding chrominance subcarrier, can be obtained.

As described above, according to the video signal processing method according to the embodiment of the present invention, about 0.92, about 0.71, about 0.38, 0 based on the reference clock of 14.1875 MHz. 3. A frequency corresponding to the PAL system is assigned by assigning a positive value or a negative value of 1 in a predetermined cycle.
Two chrominance subcarriers having a phase difference of 90 ° at 43 MHz are generated, and chrominance signal data corresponding to a chrominance signal is modulated based on the chrominance subcarriers to obtain carrier chrominance signal data.

Therefore, the frequency of the reference clock is set to 14.1
Since 875 MHz can be used for the NTSC system and the PAL system, there is no need to configure a phase locked loop circuit that simultaneously uses two types of reference clocks as in the related art.
It is possible to suppress an increase in the scale of the circuit configuration, and to suppress vertical stripe noise or the like generated on a screen due to interference between two types of frequencies.

The case where specific processing in each of the processing blocks 21 and 22 is performed will be described below. The device shown in FIG. 5 performs color difference signal data RY corresponding to the color difference signal RY.
From the reference clock CK to generate carrier chrominance signal data equivalent to that modulated by a chrominance subcarrier corresponding to the PAL system, which corresponds to the R-system processing block 21 in the block diagram of FIG. I do.

As shown in FIG. 4, the device comprises a first latch circuit 1, a first selector 2, a first adder 3, a second
Latch circuit 4, third latch circuit 5, second selector 6, second adder 7, first inverter 8, third selector 9, fourth latch circuit 10, second inverter 1
1, a third adder 12, a fourth selector 13, and a fifth latch circuit 14.

The first latch circuit 1 stores the color difference signal data R
Y is latched based on the clock CK, and the first
At the same time as the data D1 of the first selector 2 and the second latch circuit 4, the second data D2 obtained by inverting each bit of the color difference signal data RY.
Output to The first selector 2 selectively outputs one of the data obtained by multiplying the second data D2 by 1, 2 and 1/4 to the first adder 3 as the third data D3. The first adder 3 performs an addition process on data obtained by multiplying the first data D1 by 4 and the second data D2,
Is output to the third latch circuit 5 as the data D4. The second latch circuit 4 outputs the second data D2 to the clock CK.
, And the second data D2 is output as it is. The third latch circuit 5 latches the fourth data D4 based on the clock CK, and outputs the fourth data D4 to the second adder 7 as it is. The second selector 6 outputs the second data D
One of the data obtained by multiplying 2 by 1/2 and 1/8, respectively, is selectively output to the second adder 7 as fifth data D5. The second adder 7 outputs the fourth data D4 and the fifth data D4.
And outputs the result to the third selector 9 as seventh data D7. The first inverter 8 inverts each bit of the second data D2 output from the second latch circuit 4, and outputs the inverted data to the third selector 9 as sixth data D6. The third selector 9 outputs any one of the fourth data D4, the sixth data D6, and the seventh data D7 to the fourth latch circuit 10 as the eighth data D8. The fourth latch circuit 10 latches the eighth data D8 based on the clock CK and outputs the same to the second inverter 11 and the fourth selector 13. The third adder 12 is a circuit that adds 1 to the output value from the second inverter 11 and outputs the result to the fourth selector 13 as ninth data D9. The fourth selector 13 selects and outputs one of the eighth data D8 and the ninth data D9 to the fifth latch circuit 14 as the tenth data D10. The fifth latch circuit 14 generates a tenth latch based on the clock CK.
Is latched and output to the next stage.

Hereinafter, the operation of the video signal processing apparatus according to the embodiment of the present invention will be described while supplementing the operation. Here, in the device, when generating data Ra in which color difference signal data RY is multiplied by a In generating data Rb in which color difference signal data RY is multiplied by b, generating data Rc in which color difference signal data RY is multiplied by c In the case of generating data Rd in which the color difference signal data RY is multiplied by 1, the case of generating 0 will be described in five cases.

When Generating Data Ra by Multiplying the Color Difference Signal Data RY by a First, a = 0.923880 ≒ 1-2 ^ −4, and the data Ra is: Ra = RY · a ＝ RY · (1 However, in an actual circuit, the subtraction process is replaced by an addition process by inverting the subtraction data and adding 1, and the multiplication data or the dividend data is shifted by n bits to obtain 2 ^ n. The multiplication process and the division process of double (n is an integer) are realized. That is, since Ra ≒ RY−RY · 2 ^ −4, RY is shifted by 4 bits to the lower side to calculate RY · 2−4, and each bit of RY · 2 ^ −4 is inverted to obtain RY and RY. Add and then add 1 to get Ra.

The operation of the device is as follows. First, data (D1２2 + 1) obtained by multiplying the first data D1 by 4 and adding 1 from the first latch circuit 1 is input to the first adder 3. ,
1 is added to the inverted second data D2 of the color difference signal data RY.
The data D2 · 2 ^ −2 multiplied by / 4 is input from the first selector 2 to the first adder 3. Then, the data D1 · 2 ^ 2 + 1 and the data D2 · 2 ^ −
2 is added, and then multiplied by 1/4 to obtain fourth data D4. Therefore, the fourth data D4 is D4 = (D1 （2 + 1 + 1 + D2２2 ^ -2) ^ 2 ^ 2 = D1−D1２2-2-2, which is equal to RY-RY ・ 2 ^ -4. I do. Therefore, Ra
Is generated.

The fourth data D 4 is input to the third selector 9, then is selectively output as eighth data D 8, and is output via the fourth latch circuit 10 to the fourth selector 1.
3 and the fourth latch 13 to the fifth latch 1
4 to be output as tenth data D10. When generating data Rb obtained by multiplying color difference signal data RY by b First, b = 0.707107 ≒ 1-2 ^ -2-2 ^ -5, and data Rb is expressed as follows: Rb = RY · b ≒ RY · (1-2 ^ -2-2 ^ -5). Then, RY is shifted by 2 bits and 5 bits to the lower side to calculate RY · 2 ^ −2 and RY · 2 ^ −5, and these bits of RY · 2 ^ −2 and RY · 2 ^ −5 are calculated. Reverse to R
Y is added, and 2 is added to obtain Rb.

The operation of the device is as follows. First, data D1 ・ 2 + 2 + 2 obtained by multiplying the first data D1 by 4 and adding 2 from the first latch circuit 1 is input to the first adder 3, and the color difference The data D2 obtained by multiplying the second data D2 obtained by inverting the signal data RY by 1 is supplied from the first selector 2 to the first adder 3
Is input to The data D1.
Data D1 · 2 ^ 2 obtained by adding 2 ^ 2 + 2 and data D2
+ D2 + 2 is input to the third latch 5. Also, the second
D2 · 2 ^ −3 obtained by multiplying the data D2 of by 1/8 is input from the second selector 6 to the second adder 7, and the data D1 · 2 ^ 2 + D2 + 2 input from the third latch 5 After the addition, a seventh data D7 is obtained by multiplying by 1/4. Therefore, the seventh data D7 is as follows: D7 = (D1２2 + D2 + D2 ・ 2 ^ -3 + 2) ^ 2 ^ = D1-D1２2 ^ -2-D1１2２-5, and RY-RY・ It matches 2 ^ -2-RY ・ 2 ^ -5.
Therefore, Rb is generated. After the seventh data D7 is input to the third selector 9,
Selected as the data D8 of the fourth latch circuit 1
The data is input to the fourth selector 13 via 0, and is output as tenth data D10.

In the case of generating data Rc by multiplying the color difference signal data RY by c First, c = 0.328683 ^ 1-2 ^ -1-2 ^ -3, and the data Rc is as follows: Rc = RY · b ≒ RY · (1-2 ^ -1-2 ^ -3). Therefore, RY is shifted by 1 bit and 3 bits to the lower side to calculate RY ・ 2 ^ -1 and RY ・ 2 ^ -3, and these bits of RY ^ 2 ^ -1 and RY ・ 2 ^ -3 are calculated. Reverse to R
Y is added, and 2 is added to obtain Rc.

The operation of the device is as follows. First, data D1 ・ 2 + 2 + 2 obtained by multiplying the first data D1 by 4 and adding 2 from the first latch circuit 1 is input to the first adder 3, and the color difference Data D2 · 2 obtained by multiplying the second data D2 obtained by inverting the signal data RY by 2 is input from the first selector 2 to the first adder 3. The data D1 ·
Data D1 · 2 obtained by adding 2 ^ 2 + 2 and data D2 · 2
2 ^ 2 + D2 · 2 + 2 is input to the third latch 5. Data D2 · 2 obtained by multiplying the second data D2 by を
^ -1 is input from the second selector 6 to the second adder 7, and the data D1 ・ 2 ^ 2 + input from the third latch 5
Seventh data D7 is obtained by multiplying by ４ after adding D2 · 2 + 2. Therefore, the seventh data D7 is: D7 = (D1２2 + D2 ＋ 2 + D2 ・ 2 ^ -1 + 2) ２
2 ^ -2 = D1-D1 ・ 2 ^ -1-D1２2 ^ -3, which is consistent with RY-RY ・ 2 ^ -1-RY ・ 2 ^ -3.
Therefore, Rc is generated. After the seventh data D7 is input to the third selector 9,
Selected as the data D8 of the fourth latch circuit 1
The data is input to the fourth selector 13 via 0, and is output as tenth data D10.

When Generating Data Rd by Multiplying Color Difference Signal Data RY by 1 First, the second data D 2 obtained by inverting the color difference signal data RY from the first latch circuit 1 is input to the second latch circuit 4. You. Next, the second data D2 is input from the second latch circuit 4 to the first inverter 8, bit-inverted again, and output as sixth data D6 to the third selector 9. The sixth data D6 is the color difference data RY itself. Then, by the third selector 9, the sixth selector
Is selectively output as the eighth data D8,
After being input to the fourth selector 13 via the fourth latch circuit 10, it is output as tenth data D10. In this manner, data Rd obtained by multiplying the color difference signal data RY by 1 is generated.

In the case of generating 0 In this case, by selecting a state in which no data is output from the third selector 9, 0 is generated and output. By the way, Ra, Rb, Rc and R
When generating the negative data of d, the eighth adder 12 adds 1 to the eighth data D8 output from the fourth latch circuit 10 after inverting each bit by the second inverter 11. By doing, the ninth data D
9, i.e., -Ra, -Rb, -Rc and -Rd. Then, the ninth data D9 is output from the fourth selector 13 as the tenth data D10 via the 54th latch circuit 14.

By the above operations, the data Ra, -Ra, Rb,-necessary for the modulation processing by the color subcarrier of the frequency 14.1875 MHz corresponding to the PAL system.
Rb, Rc, -Rc, Rd, -Rd, and 0 are determined. Therefore, 0, Ra, -Rb, -Rc, Rd,-
Rc, -Rb, Ra, 0, -Ra, Rb, Rc, -R
d, Rc, Rb, -Ra, 0 in the order of the reference clock CK.
By assigning each data at each timing of
Using a reference clock CK having a frequency of 14.1875 MHz, processing equivalent to modulating the color difference signal data RY with a color subcarrier having a frequency of 4.43 MHz corresponding to the PAL system can be performed.

The B-system processing block 22 also
Data Ba, -Ba, Bb, -Bb, Bc, -B required for modulation processing by the same configuration as R-system processing block 21
c, Bd, -Bd, 0 are obtained. And -Bd,
Bc, Bb, -Ba, 0, Ba, -Bb, -Bc, B
d, -Bc, -Bb, Ba, 0, -Ba, Bb, Bc,
By allocating according to the reference clock CK in the order of −Bd, it is possible to perform the same processing as modulating the color difference signal data BY with the color subcarrier corresponding to the PAL system. However, the B-system processing block 22 is configured to invert the positive / negative of data every one horizontal scanning period, as shown in the selection output circuit 222 of FIG.

When only the color sub-carrier is obtained in the apparatus, the color difference signal data RY and BY provided to each of the processing blocks 21 and 22 may be replaced with fixed data other than 0. That is, the processing blocks 21 and 22
, The carrier color signal data having a constant amplitude can be obtained.
By converting the data output from the first and second data into analog values and extracting them, two types of color subcarriers whose phases are shifted by 90 ° are obtained.

Therefore, according to the video signal processing apparatus according to the embodiment of the present invention, based on the reference clock of 4.multidot.FSC = 14.1875 MHz, the PAL system is supported and the frequency is 4.43 MHz and the phases are 90.degree. Two different chrominance subcarriers are generated as digital data, a chrominance signal is balanced-modulated based on the chrominance subcarrier to generate a carrier chrominance signal, and the carrier chrominance signal is converted into an analog value by a D / A converter (not shown). It is converted and output. For this reason, it is possible to generate a color subcarrier corresponding to the PAL system having a frequency of 4.43 MHz based on the reference clock.
With a reference clock that is very close to the reference clock corresponding to the C system, both the NTSC system and the PAL system can be supported, and the common use of the system is promoted.

By the way, according to the video signal processing method according to the present embodiment, after that, the color difference signal RY corresponding to the red component and the color difference signal BY corresponding to the blue component are modulated by the above-described processing method. When a color synthesis signal Cry is generated by adding the sum (hereinafter referred to as a color modulation component signal Cr) and the luminance signal Y to generate and transmit the signal, a D / A converter converts the signal to an analog value. May cause trouble. FIG. 6 is a graph showing a relationship when a color subcarrier having a frequency of 4.43 MHz is sampled by a reference clock CK having a frequency of 14.875 MHz.

That is, as shown in FIG. 6, when the color subcarrier is sampled by the reference clock CK,
The graph shown in the middle row shows that this data is D /
When the A converter converts the analog value, the D /
Data range that can be handled by the A converter [for example, 8-bit D
/ A converter in the range of 0 to 255], and the excess may be clipped. In this case, as shown in the lowermost graph of FIG. 6, the upper half of the data may be completely clipped. At this time, a signal having an apparent waveform as shown by a dotted line in the lowermost graph of FIG. 6 may be generated, and a signal having a frequency different from the original frequency of 4.43 MHz may be generated. was there.

Therefore, in order to prevent this, the maximum value Crmax of the color modulation component signal Cr is set to Crmax so that the data corresponding to the color composite signal Cry does not clip beyond the data range that can be handled by the D / A converter. = Dmax-YD [YD> Dmax / 2] A gain is applied to the color modulation component signal Cr so that Crmax = YD [YD <Dmax / 2]. In the above equation, Dmax is the maximum value of data that can be handled by the D / A converter, and YD is luminance signal data.

For example, in the case of an 8-bit D / A converter, 255 is Dmax and Dmax / 2 is 128. If the luminance signal data YD is 200, it exceeds 128 which is Dmax / 2. Crmax becomes Crmax = Dmax-YD [YD> Dmax / 2] = 200-128 = 72, and it is sufficient to apply a gain to the color modulation component signal Cr so as not to exceed this.

In this embodiment, the device shown in FIG. 4 is an example of the modulating means 31 and has a frequency of 14.1875 MHz.
Is an example of n · FSC, where n = 4
It has become.

[0041]

According to the present invention, the frequency 14.1875
Based on a reference clock of 2 MHz, the frequency is 4.43 MHz corresponding to the PAL system and the phases are different from each other by 90 °.
The type of color subcarrier is generated, the color difference data corresponding to each color difference signal is modulated based on the color subcarrier, and the output is D / A converted. It is possible to cope with both the NTSC system and the PAL system which are different by using a very close main clock. At this time, on the input side of the D / A converter, the carrier chrominance signal data superimposed on the luminance signal data is:
Since the signal is suppressed so as not to exceed the input range of the D / A converter, it is possible to prevent the signal waveform after the D / A conversion from being distorted.

Accordingly, unlike the related art, there is no need to provide a phase locked loop circuit that uses two types of main clocks at the same time, and it is possible to suppress an increase in the circuit configuration.
It is possible to suppress vertical stripe noise generated on the screen due to interference between two types of frequencies.

[Brief description of the drawings]

FIG. 1 is a first principle diagram of a video signal processing device according to the present invention.

FIG. 2 is a second principle diagram of the video signal processing device according to the present invention.

FIG. 3 is a first diagram illustrating a video signal processing method according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating an outline of a video signal processing device according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a video signal processing device according to an embodiment of the present invention.

FIG. 6 is a second diagram illustrating the video signal processing method according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a color encoder according to a conventional example.

FIG. 8 is a diagram illustrating a video signal processing method according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st latch circuit 2 1st selector 3 1st adder 4 2nd latch circuit 5 3rd latch circuit 6 2nd selector 7 2nd adder 8 1st inverter 9 3rd selector Reference Signs List 10 fourth latch circuit 11 second inverter 12 third adder 13 fourth selector 14 fifth latch circuit 15 fourth adder 31 intermediate value generation means 32 selection means 33 digital / analog conversion means 34 arithmetic Means D1 to D10 First to tenth data RY, BY Color difference signal RY, BY Color difference signal data YD Luminance signal data

Claims (2)

[Claims] 1. A method for generating intermediate value data corresponding to a value obtained by sampling a square wave signal having a modulation period of color information in a specific television system with a reference clock having a period shorter than the period. Means for multiplying the generated plurality of intermediate value data by color difference signal data provided at timings according to the reference clock, respectively; and obtaining the reference clock from the plurality of color difference signal data multiplied by different intermediate value data. Means for generating carrier color signal data by periodically selecting one data in a predetermined order during a common multiple cycle of the cycle of the reference clock and the modulation cycle of the color information at a timing according to
Means for suppressing the carrier color signal data to a limit value or less when a value represented by the carrier color signal data exceeds a limit value determined according to the luminance signal data corresponding to the color difference signal data. A video signal processing device. 2. Generating intermediate value data corresponding to a value obtained by sampling a square wave signal having a modulation period of color information in a specific television system with a reference clock having a period shorter than that period. Means for periodically selecting one data in a predetermined order from a plurality of generated intermediate value data at a timing according to the reference clock during a common multiple cycle of a cycle of the reference clock and a modulation cycle of the color information; Means for generating carrier color signal data by multiplying the selected intermediate value data by color difference signal data provided at a timing according to the reference clock, and a value represented by the carrier color signal data corresponding to the color difference signal data. Means for suppressing the carrier chrominance signal data below the limit value when the limit value defined according to the luminance signal data to be performed is exceeded. A video signal processing device.