JPH07115657A - Video signal processing method and video signal processor - Google Patents

Abstract

PURPOSE:To generate chrominance subcarrier used for a balanced modulation processing in a color encoder. CONSTITUTION:Prescribed intermediate value data are cyclically allocated to the respective timings of reference clocks provided with a cycle shorter than the chrominance subcarrier. By converting the intermediate value data outputted corresponding to the reference clocks to analog values, the chrominance subcarrier corresponding to a specified television system is obtained. By providing an intermediate value generation means 31, a selection means 32 and a digital/analog conversion means 33, cyclically taking out the positive and negative values of five intermediate values, 0, 0.38, 0.71, 0.91 and 1 generated by the intermediate value generation means 31 for instance during 16 clock cycles in a prescribed order by the selection means 32 and converting them to the analog values by the digital/analog conversion means 33, the chrominance subcarrier of approximately 4.43MHz corresponding to a PAL system is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing method and a video signal processing apparatus, and more particularly to an improvement in a method and apparatus for balanced modulation of color difference signals with color subcarriers.

[0002]

2. Description of the Related Art Generally, a color-combined video signal output as a video signal is a color difference matrix and parallel modulation for video signals (R, G, B) of respective color components representing three primary colors (red, green, blue). It is obtained by performing processing such as. These processes are called a color encoder and are performed by a video signal processing device as shown in FIG.

A video signal source 40, such as a television camera or an RGB processor, produces a red,
Three types of video signals (R, G,
B) is generated. These three types of video signals (R, G, B)
The matrix circuit 41 that takes in the video signals (R, G,
B) in a predetermined ratio [R: 30%, G: 59%, B: 11
%] To generate a luminance signal (Y), and further subtract the luminance signal (Y) from the video signal (R, B) to generate two types of color difference signals (RY, BY). . The balanced modulation circuit 42 amplitude-modulates the two color subcarriers that are 90 ° out of phase with each other by the color difference signals (RY, BY),
The two are combined to generate a carrier color signal. Then, the adding circuit 43 adds the luminance signal (Y) and the carrier color signal,
Further, the composite sync signal and the color sync signal are added to generate a video signal. Further, the synchronization signal generation circuit 44 generates each synchronization signal for horizontal scanning and vertical scanning based on a reference clock having a cycle determined for each television system,
By supplying these synchronization signals to the respective parts, mutual operations are synchronized. The color subcarrier supplied to the balanced modulation circuit 42 is also generated from the reference clock by the synchronization signal generation circuit 44. The frequency f _{SC of} this color subcarrier
Is standardized according to the signal transmission method, and NTSC (National Television System Committee)
e) method is about 3.58MHz, PAL (Phase A
Alternate by Line), it is about 4.43 MHz.

By the way, in recent television camera systems and the like, there has been a shift from a conventional video signal processing device using analog signal processing to a video signal processing device employing digital signal processing that is easy to adjust and has little deterioration of the video signal. It is being advanced. Corresponding to this, the color difference signals (RY, B
The balanced modulation of -Y) is also performed by digital signal processing. Hereinafter, a method for digitizing a system for balance-modulating the color difference signals (RY, BY) with color subcarriers to obtain a carrier color signal will be described.

First, the frequency 3.58 according to the NTSC system
In order to process the color difference signal (RY) on the basis of the color subcarrier of MHz, in order to process the color difference signal (RY), as shown in the graph of FIG.
z (3.58 MHz x 4) clock is used as a sampling clock, and (RY), 0,-(RY), 0,
(RY) ... Data may be sequentially sampled. In addition, the color difference signal (BY) is the color difference signal (RY).
Since the phase is shifted by 90 ° with respect to the color difference signal (B-
Y) is processed similarly, 0, (BY), 0,-
The data of (BY), 0, ... May be sequentially sampled. Therefore, these modulated color difference signals (R
In order to generate a carrier color signal generated by adding -Y, BY), a clock having a frequency of 14.32 MHz is used as a sampling clock, and (RY), (BY),-
Sampling data of (RY) and-(BY) may be sequentially sampled. In the actual processing, a clock having a frequency of 14.32 MHz is used as a sampling clock from the beginning (RY), (BY),
The carrier color signal is generated by sequentially sampling the sampling data of − (RY) and − (BY).

By the way, as described above, the color subcarrier (f
The frequency of sc) is defined by the standard as follows for each television system of NTSC and PAL. NTSC system: f _SC = 3.579545 MHz PAL system: f _SC = 4.43461875 MHz Therefore, when configuring a camera system, a frequency that is an integral multiple of f _SC is used as the reference clock of the system. Incidentally, when the horizontal scanning frequency is f _H and the vertical scanning frequency is f _V , the following definitions are made.

NTSC system: 4f _SC = 910f _H PAL system: 4f _SC = 1135f _H + 2f _V However, if the system is configured so as to comply with these standards, NTSC and PAL f _{Since the SCs} differ greatly, it was difficult to standardize the system. So PA
As a reference clock of the L system, it is considered to use a reference clock defined by 4 · F _SC = 908 f _H = 14.1875 MHz to make the system common to the NTSC system. However, in such a system, in order to obtain the original f _SC corresponding to the PAL system, it is necessary to configure a phase locked loop circuit with the F _SC system clock and the f _SC system clock so that their phases coincide with each other. It was

[0008]

However, according to the video signal processing method according to the conventional example, since it is necessary to configure the phase locked loop circuit, the circuit scale of the apparatus for implementing the method becomes large, and the F _SC system is also used. Since two types of clocks with different frequencies are used at the same time as the f _SC clock and the f _SC clock, the interference of these two frequencies affects the analog system and causes vertical stripe noise on the screen. Was there.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art. For each timing of a reference clock having a constant cycle, the cycle of the reference clock and the color in a particular television system are set. Predetermined intermediate values are cyclically assigned for each common multiple of the information modulation cycle, and two types of color subcarriers corresponding to the television system differ in phase by 90 ° from each other based on the allocated intermediate values. Or a color signal signal data which is sequentially given at the timing according to the reference clock by the assigned intermediate value to perform amplitude modulation to generate carrier color signal data corresponding to the television system. A video signal processing method is provided.

Then, intermediate value data associated with a value obtained by sampling a positive ground wave signal having a modulation cycle of color information in a specific television system with a reference clock having a cycle shorter than the cycle is generated. Means and a plurality of generated intermediate value data, one data is cyclically selected in a predetermined order during a common multiple cycle of the cycle of the reference clock and the modulation cycle of the color information at a timing according to the reference clock. And a means for sequentially converting the selected data into an analog value to generate a color subcarrier corresponding to the above-mentioned television system.

Further, intermediate value data associated with a value obtained by sampling a positive ground wave signal having a modulation cycle of color information in a specific television system with a reference clock having a cycle shorter than the cycle is generated. Means for multiplying the generated color difference signal data by a plurality of intermediate value data generated at timings according to the reference clock, and a plurality of the color difference signal data multiplied by different intermediate value data, Means for generating one carrier color signal data by periodically selecting one data in a predetermined order during a common multiple of the reference clock cycle and the color information modulation cycle at a timing according to a clock. A video signal processing device or a positive ground wave signal having a modulation cycle of color information in a specific television system Means for generating intermediate value data associated with a value obtained by sampling with a reference clock having a certain cycle, and a cycle of the reference clock and the color at a timing according to the reference clock from a plurality of generated intermediate value data. Means for periodically selecting one data in a predetermined order during a common multiple cycle of the information modulation cycle, and the carrier color by multiplying the selected intermediate value data by the color difference signal data given at the timing according to the reference clock. A video signal processing device including means for generating signal data.

[0012]

[Operation] According to the video signal processing method of the present invention, color subcarriers corresponding to a specific television system are obtained from reference clocks of different frequencies. For example, 4F
_With respect to the reference clock of _SC (about 14.1875 MHz), 0, 0.38, 0., etc. are obtained every 16 clock cycles which is a common multiple cycle with the cycle of the color subcarrier corresponding to the PAL system.
By periodically assigning positive / negative values of five intermediate values of 71, 0.92, and 1 in a predetermined order, a color subcarrier having a frequency of about 4.43 MHz corresponding to the PAL system is generated. Therefore, the carrier color signals corresponding to the NTSC system and the PAL system can be obtained by using the reference clock having a frequency close to the reference clock corresponding to the NTSC system. Further, the color difference signal data given at the timing according to the reference clock is multiplied by the intermediate value assigned to the reference clock to perform amplitude modulation to obtain the carrier color signal data. Therefore, the NTSC system uses a reference clock with a frequency close to that of the NTSC system.
It is possible to respectively perform balanced modulation of color difference signals corresponding to the PAL system and the PAL system.

According to the video signal processing apparatus of the present invention, as shown in FIG. 1, the intermediate value generating means (31), the selecting means (32) and the digital / analog converting means (33).
Have. For example, the selection means (32) selects positive / negative values of five intermediate values of 0, 0.38, 0.71, 0.92, 1 generated by the intermediate value generation means (31) for 16 clock cycles. To the digital /
By converting to an analog value by the analog converting means (33), a frequency of about 4.43M corresponding to the PAL system is obtained.
The Hz color subcarrier is output.

Further, according to the video signal processing apparatus of the present invention, as shown in FIG. 2, it has an intermediate value generating means (31), a selecting means (32) and a calculating means (34). For example, 0, 0.38 generated by the intermediate value generation means (31),
The calculating means (34) multiplies the color difference signal data by the positive / negative values of the five intermediate values of 0.71, 0.92, and 1, and gives them to the selecting means (32), whereby the selecting means (32).
Outputs carrier color signal data obtained by modulating a color difference signal with a color subcarrier.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A video signal processing method and a video signal processing apparatus according to embodiments of the present invention will be described below with reference to the drawings. First, a video signal processing method according to an embodiment of the present invention will be described. FIG. 3 shows a frequency corresponding to the PAL system using a reference clock of 14.1875 MHz.
It is a figure explaining the method of modulating a color difference signal with a 43-MHz color subcarrier.

In order to generate a color subcarrier having a frequency of 4.43 MHz as digital data from a clock having a frequency of 14.1875 MHz, as shown in FIG. 3, 16 clock cycles (color subcarrier) of the reference clock, which is a common multiple cycle of each other. 5 cycles), 0, a, -b, -c, 1, -c,-
Intermediate value data may be assigned in the order of b, a, 0, -a, b, c, -1, c, b, -a, and 0 in accordance with each timing of the reference clock. In addition, each intermediate value data of a, b, and c is a = 0.923880≈1-2 ⁻⁴ b = 0.707107≈1-2 ⁻² −2 ⁻⁵ c = 0.382683≈1-2 ^{− 1} -2 ^-3. Therefore, if these a, b, c, 0, and 1 can be generated, the color subcarrier can be generated by digital / analog conversion [hereinafter referred to as D / A conversion].

Digital data of color difference signals (RY, BY) [hereinafter referred to as color difference data (RY, BY)]
In order to be processed as if it was modulated by a color subcarrier having a frequency of 4.43 MHz, in FIG. 3, the color difference signal data (RY, BY) is multiplied by the intermediate value data assigned to each timing of the reference clock. It should be output. That is, color difference data (RY, B
Y) is multiplied by each intermediate value data a, b, c, 1 to obtain Ra = RY · a, Rb = RY · b, Rc = RY · c, R
d = RY · 1 Ba = BY · a, Bb = BY · b, Bc = BY · c, B
Data d = BY.multidot.1 is obtained, and these data may be allocated at each timing of the reference clock according to the allocation order of the intermediate value data shown in FIG. For example, regarding color difference signal data (RY), 0, Ra, -Rb, -Rc, Rd, -Rc, -Rb, R
a, 0, -Ra, Rb, Rc, -Rd, Rc, Rb,-
Data of Ra, 0, ... May be sequentially assigned. Also,
Regarding the color difference signal data (BY), considering that the phase difference with the color difference signal data (RY) is 90 °, −K · Bd, K · Bc, K · Bb, −K · Ba, 0, K
-Ba, -K-Bb, -K-Bc, K-Bd, -K-B
c, -K / Bb, K / Ba, 0, -K / Ba, K / B
Data of b, K / Bc, -K / Bd ... Are sequentially allocated. Note that K is a value that inverts positive / negative for each horizontal scanning period. Hereinafter, an apparatus that implements the video signal processing method according to the present embodiment will be described.

FIG. 4 is a block diagram for explaining the configuration of the video signal processing apparatus according to the embodiment of the present invention. In Figure 4,
The R component processing block (21) modulates the red component color difference signal (RY) with the color subcarrier, and the B component processing block (22) modulates the blue component color difference signal (BY) with the color subcarrier. I'm processing it. In the R processing block (21), the color difference signal data (RY) corresponding to the color difference signal (RY) is (1-2 ⁻⁴ ), (1-2 ⁻² −).
2 ^-5), (1-2 ^-1 -2 ^-3) which is a value obtained by multiplying each Ra, Rb, Rc, addition, Rd and 0 is a color difference signal data (RY) values of itself is generated. Then, these positive and negative values are input to the first selection output circuit (211), and the frequency 14.1875 MH is calculated from these nine values.
Hexadecimal counter (2
It is selectively output in a predetermined order based on the output value of 3).
The output order at this time follows the allocation order of the sampling data shown in FIG.

Therefore, the output value of the first selection output circuit (211) is 0, Ra, -Rb, -Rc, Rd, -Rc, -Rb, R.
a, 0, -Ra, Rb, Rc, -Rd, Rc, Rb,-
.., which means that the color-difference signal (RY) is processed by the color subcarrier having a frequency of 4.43 MHz, which is equivalent to the processing of modulation.

In the B system processing block (22), Ba, Bb, and
Positive and negative values of Bc and Bd and 0 are input to the second selection output circuit (221) and selected and output in a predetermined order based on the output value of the hexadecimal counter (23). The output order at this time also follows the allocation order of the sampling data shown in FIG. 3, similarly to the R system processing block 21. afterwards,
The positive and negative values of the output value of the second selection output circuit (221) are input to the third selection output circuit (222) and are output based on the line select pulse (LP) which is inverted every horizontal scanning period. The selection output circuit (222) of No. 3 outputs. Accordingly, the output values of the third selection output circuit (222) are -K-Bd, K-Bc, K-Bb, -K-Ba, 0, K.
-Ba, -K-Bb, -K-Bc, K-Bd, -K-B
c, -K / Bb, K / Ba, 0, -K / Ba, K / B
b, K · Bc, −K · Bd ... Therefore, the color difference signal (BY) has a frequency of 4.43.
The same processing as that performed by the color subcarrier of MHz is performed.

Carrier color signal data is obtained by adding the two types of data modulated by the color subcarriers obtained by the above processing by the adder (24). This carrier color signal data is output in a cycle according to a frequency of 14.1875 MHz, but since it is multiplied by the above-mentioned intermediate value data as a coefficient, if it changes to an analog value by D / A conversion, it will be in the PAL system. Frequency equivalent to that modulated by the corresponding color subcarrier, 4.43 MHz
The carrier color signal can be obtained.

As described above, according to the video signal processing method of the embodiment of the present invention, about 0.92, about 0.71, about 0.38, 0 based on the reference clock of 14.1875 MHz. 3. A frequency corresponding to the PAL system is assigned by assigning a positive value or a negative value of 1 in a predetermined cycle.
Two color subcarriers whose phases are different from each other by 90 ° at 43 MHz are generated, and the color difference signal data corresponding to the color difference signal is modulated based on these color subcarriers to obtain carrier color signal data.

Therefore, the frequency of the reference clock is set to 14.1
Since it is possible to correspond to the NTSC system and the PAL system at 875 MHz, it is not necessary to configure a phase locked loop circuit that simultaneously uses two types of reference clocks, unlike the conventional case.
It is possible to prevent the circuit configuration from increasing in size, and it is possible to suppress vertical stripe noise and the like generated on the screen due to interference of two types of frequencies.

A case where a specific process is performed in each of the processing blocks 21 and 22 will be described below. The apparatus shown in FIG. 5 uses the reference clock (CK) from the color difference signal data (RY) corresponding to the color difference signal (RY) to generate the PAL signal.
The carrier color signal data equivalent to that modulated by the color subcarrier corresponding to the method is generated, and corresponds to the R system processing block (21) in the block diagram of FIG.

As shown in FIG. 4, the apparatus has a first latch circuit (1), a first selector (2), a first adder (3), a second latch circuit (4), and a second latch circuit (4). 3 latch circuit (5), second selector (6), second adder (7),
First inverter (8), third selector (9), fourth
Latch circuit (10), second inverter (11), third adder (12), fourth selector (13) and fifth
Latch circuit (14).

The first latch circuit (1) latches the color difference signal data (RY) based on the clock (CK),
The color difference signal data (RY) is simultaneously output to the first adder (3) as the first data (D1) as it is.
The second data (D2) obtained by inverting each bit of is output to the first selector (2) and the second latch circuit (4). The first selector (2) uses, as the third data (D3), any one of the data obtained by multiplying the second data (D2) by 1, 2 and 1/4, respectively. Selectively output to (3). The first adder (3) multiplies the first data (D1) by 4 and the second data (D1).
2) and the addition processing, and the third data is obtained as the fourth data (D4).
To the latch circuit (5). The second latch circuit (4) latches the second data (D2) based on the clock (CK) and outputs the second data (D2) as it is. The third latch circuit (5) latches the fourth data (D4) based on the clock (CK) and outputs it as it is to the second adder (7). The second selector (6) outputs 1/2 and 1 to the second data (D2), respectively.
Any one of the data multiplied by / 8 is selectively output to the second adder (7) as the fifth data (D5). The second adder (7) adds the fourth data (D4) and the fifth data (D5) and outputs it as the seventh data (D7) to the third selector (9). The first inverter (8) outputs a second inverter output from the second latch circuit (4).
Each bit of the data (D2) is inverted and output as the sixth data (D6) to the third selector (9). Third
The selector (9) of the fourth latch circuit (9) uses any one of the fourth data (D4), the sixth data (D6) and the seventh data (D7) as the eighth data (D8). 10)
Output to. The fourth latch circuit (10) latches the eighth data (D8) based on the clock (CK),
The signal is output to the second inverter (11) and the fourth selector (13). The third adder (12) is a circuit that adds 1 to the output value from the second inverter (11) and outputs it as the ninth data (D9) to the fourth selector (13). The fourth selector (13) outputs the eighth data (D
Either the data 8) or the ninth data (D9) is selectively output to the fifth latch circuit (14) as the tenth data (D10). The fifth latch circuit (14) has a clock (C
Latch the tenth data (D10) based on K),
Output to the next stage.

The operation of the video signal processing apparatus according to the embodiment of the present invention will be described below supplementarily. Here, in the device, data (Ra) obtained by multiplying color difference signal data (RY) by a
When the color difference signal data (RY) is multiplied by b (Rb)
When the color difference signal data (RY) is multiplied by c (Rc)
When color is generated Color difference signal data (RY) is multiplied by 1 (Rd)
Will be described separately for the five cases of generating 0 and generating 0.

When data (Ra) is generated by multiplying color difference signal data (RY) by a First, a = 0.923880≈1-2 ⁻⁴ , and the data (Ra) is Ra = RY · a ≈RY · (1-2 ⁻⁴ ), but in an actual circuit, subtraction data is inverted and 1 is added to replace subtraction processing with addition processing, and multiplicand data or dividend data is shifted by n bits. Thus, multiplication processing and division processing of 2 ⁿ times (n is an integer) are realized. That is, since Ra≈RY−RY · 2 ⁻⁴ ,
Calculates RY · 2 ^-4 and 4-bit shift RY lower side, adds the RY and the bit inversion of the RY · 2 ^-4,
Further, 1 is added to obtain Ra.

The operation of the device is as follows. First, the data (D1 · 2 ² +1) obtained by multiplying the first data (D1) by 4 and adding 1 from the first latch circuit (1) is the first adder. (3)
Input to the second and the color difference signal data (RY) is inverted
Data (D2) multiplied by 1/4
2 ^-2 ) is from the first selector (2) to the first adder (3)
Entered in. Then, by the first adder (3),
The data (D1 · 2 ² +1) and the data (D2 · 2 ⁻² ) are added and then multiplied by ¼ to obtain the fourth data (D1).
4) is required. Therefore, the fourth data (D4) is D4 = (D1 · 2 ² + 1 + D2 · 2 ⁻² ) · 2 ⁻² = D1−D1 · 2 ⁻² , which corresponds to RY−RY · 2 ⁻⁴ . Therefore, Ra is generated.

The fourth data (D4) is input to the third selector (9) and then selectively output as the eighth data (D8), and the fourth data (D4) is output via the fourth latch circuit (10). It is input to the fourth selector (13) and is output from the fourth selector (13) as the tenth data (D10) via the fifth latch (14). Data (Rb) obtained by multiplying color difference signal data (RY) by b
First, b = 0.07107107≈1-2 ⁻² −2 ⁻⁵ , and the data (Rb) is Rb = RY · b≈RY · (1-2 ⁻² −2 ⁻⁵ ). Becomes Therefore, to calculate the RY · 2 ^-2 and RY · 2 ^-5 to 2 bits and 5 bits shifted RY to the lower side, by inverting each bit of RY · 2 ^-2 and RY · 2 ^-5 RY Is added, and 2 is further added to obtain Rb.

The operation of the device is as follows. First, the data (D1 · 2 ² +2) obtained by multiplying the first data (D1) by 4 and adding 2 from the first latch circuit (1) is the first adder. (3)
Input to the second and the color difference signal data (RY) is inverted
The data (D2) obtained by multiplying the data (D2) of 1 by 1 is input from the first selector (2) to the first adder (3).
Data (D1 · 2 ² +) is output from the first adder (3).
2) and the data (D2) are added (D1.2)
² + D2 + 2) is input to the third latch (5). Also, data (D2) obtained by multiplying the second data (D2) by 1/8
2 · 2 ⁻³ ) is input from the second selector (6) to the second adder (7) and added with the data (D1 · 2 ² + D2 + 2) input from the third latch (5). Later 1 /
The fourth data is multiplied to obtain the seventh data (D7). Therefore, the seventh data (D7) is D7 = (D1 · 2 ² + D2 + D2 · 2 ⁻³ +2) · 2 ⁻² = D1−D1 · 2 ⁻² −D1 · 2 ⁻⁵ , and RY−RY · matching 2 ^-2 -RY · 2 ^-5. Therefore, Rb is generated. The seventh data (D7) is input to the third selector (9), and then selectively output as the eighth data (D8), and the fourth data is output via the fourth latch circuit (10). It is input to the selector (13) and output as the tenth data (D10).

To generate data (Rc) by multiplying color difference signal data (RY) by c First, c = 0.382683≈1-2 ^-1 -2 ^-3 , and the data (Rc) is Rc = RY · b≈RY · (1-2 ⁻¹ −2 ⁻³ ). Therefore, to calculate the RY · 2 ^-1 and RY · 2 ^-3 to 1 bit and 3-bit shift RY to the lower side, by inverting each bit of RY · 2 ^-1 and RY · 2 ^-3 RY Is added, and 2 is further added to obtain Rc.

In the operation of the device, first, the data (D1 · 2 ² +2) obtained by multiplying the first data (D1) by 4 and adding 2 from the first latch circuit (1) is the first adder. (3)
Input to the second and the color difference signal data (RY) is inverted
The data (D2 · 2) obtained by multiplying the data (D2) of 2 by 2 is input from the first selector (2) to the first adder (3). This first adder (3) outputs data (D1 · 2 ²
+2) and the data (D2.2) are added (D
1 · 2 ² + D2 · 2 + 2) is input to the third latch (5). Further, the data (D2 · 2 ⁻¹ ) obtained by multiplying the second data (D2) by ½ is the second data from the second selector (6).
Is added to the data (D1 · 2 ² + D2 · 2 + 2) input from the third latch (5) and then multiplied by ¼ to obtain the seventh data (D7). Desired. Therefore, the seventh data (D7) is D7 = (D1 · 2 ² + D2 · 2 + D2 · 2 ⁻¹ +2) · 2
A ^{-2 = D1-D1 · 2 -1} -D1 · 2 -3, matching ^{RY-RY · 2 -1 -RY ·} 2 -3. Therefore, Rc is generated. The seventh data (D7) is input to the third selector (9), and then selectively output as the eighth data (D8), and the fourth data is output via the fourth latch circuit (10). It is input to the selector (13) and output as the tenth data (D10).

When Color Difference Signal Data (RY) is Multiplied by 1 to Generate Data (Rd) First, the color difference signal data (R) is output from the first latch circuit (1).
The second data (D2) obtained by inverting Y) is input to the second latch circuit (4). Next, the second data (D2) is input from the second latch circuit (4) to the first inverter (8) and bit-inverted again to generate the sixth data (D6) as the third selector (D6). It is output to 9). The sixth data (D6) is the color difference data (RY) itself. Then, the sixth selector (9) selectively outputs the sixth data (D6) as the eighth data (D8), and the sixth data (D6) is output to the fourth selector (13) via the fourth latch circuit (10). After being input, it is output as the tenth data (D10). In this way, data (Rd) obtained by multiplying the color difference signal data (RY) by 1 is generated.

In the case of generating 0 In this case, by selecting the state in which no data is output from the third selector (9), 0 is generated and output. By the way, when negative data of Ra, Rb, Rc and Rd is generated, each bit of the eighth data (D8) output from the fourth latch circuit (10) is inverted by the second inverter (11). After that, by adding 1 by the third adder (12), the ninth data (D9), that is, -Ra, -Rb,-
Rc and -Rd are generated. Then, the ninth data (D9) is output from the fourth selector (13) as the tenth data (D10) via the 54th latch circuit (14).

By the above operations, the data (Ra, -Ra, Rb, etc.) necessary for the modulation processing by the color subcarrier of frequency 14.1875 MHz corresponding to the PAL system is obtained.
-Rb, Rc, -Rc, Rd, -Rd, 0) are respectively calculated. Therefore, 0, Ra, -Rb, -Rc, R
d, -Rc, -Rb, Ra, 0, -Ra, Rb, Rc,
By allocating respective data at each timing of the reference clock (CK) in the order of −Rd, Rc, Rb, −Ra, 0, the PAL system is used by using the reference clock (CK) having the frequency of 14.875 MHz. Corresponding frequency 4.4
The same processing as that of modulating the color difference signal data (RY) with the color subcarrier of 3 MHz can be performed.

As for the B system processing block (22), the data (Ba, -Ba, Bb, -Bb, Bc, and
-Bc, Bd, -Bd, 0) is obtained. And-
Bd, Bc, Bb, -Ba, 0, Ba, -Bb, -B
c, Bd, -Bc, -Bb, Ba, 0, -Ba, Bb,
By assigning Bc and -Bd in this order so as to follow the reference clock (CK), it is possible to perform the same processing as that of modulating the color difference signal data (BY) with the color subcarrier corresponding to the PAL system. However, B system processing block (22)
Then, as shown in the selective output circuit (222) of FIG.
It is configured to invert the positive / negative of data for each horizontal scanning period.

By the way, in the case of obtaining only the color subcarrier in the apparatus, each processing block (21), (2)
The color difference signal data (RY, BY) given in 2) may be replaced with fixed data other than 0. That is, by giving fixed data to the processing blocks (21) and (22), carrier color signal data having a constant amplitude can be obtained, and the data output from the processing blocks (21) and (22) can be obtained. By converting each of them into an analog value and extracting them, it is possible to obtain two types of color subcarriers whose phases are shifted by 90 °.

Therefore, according to the video signal processing apparatus in the embodiment of the present invention, the PAL system is supported on the basis of the reference clock of 4 · F _SC = 14.1875 MHz, and the phases are 90 degrees with each other at the frequency of 4.43 MHz. Two different color subcarriers are generated as digital data, the color difference signals are balanced-modulated based on the color subcarriers to generate a carrier color signal, and the carrier color signal is converted into an analog value by a D / A converter (not shown). Is converted to and output. Therefore, the color subcarrier corresponding to the PAL system with the frequency of 4.43 MHz can be generated based on the reference clock.
A reference clock very close to the reference clock corresponding to the C system can support both the NTSC system and the PAL system, and promotes system commonality.

By the way, according to the video signal processing method according to the present embodiment, the color difference signal (RY) corresponding to the red color component and the color difference signal (B) corresponding to the blue color component, which are modulated by the above processing method, are then used. -Y) and the sum [hereinafter referred to as the color modulation component signal (Cr)] and the luminance signal (Y) are added to generate and transmit a color composite signal (Cry), which is then transmitted by the D / A converter. When converting to an analog value, some trouble may occur. FIG. 5 shows a frequency of 4.43.
It is a graph which shows the relationship when the color subcarrier of MHz is sampled by the reference clock (CK) of frequency 14.875 MHz.

That is, as shown in FIG. 5, when the color subcarrier is sampled by the reference clock (CK),
As shown in the graph in the middle of FIG. 5, when this data is converted into an analog value by the D / A converter, the data range that the D / A converter can handle [eg, 8-bit D / A In the case of a converter, the range from 0 to 255] may be exceeded, and the excess may be clipped. In this case, as shown in the graph at the bottom of FIG. 5, the upper half of the data may be completely clipped. At this time, a signal having an apparent waveform as shown by the dotted line in the graph at the bottom of FIG. 5 is generated, and a signal having a frequency different from the original frequency of 4.43 MHz may be generated. was there.

Therefore, in order to prevent this, the maximum value of the color modulation component signal (Cr) is prevented so that the data corresponding to the color composite signal (Cry) does not clip beyond the data range that can be handled by the D / A converter. A gain is applied to the color modulation component signal (Cr) so that (Cr _max ) becomes Cr _max = D _max -YD [YD> D _max / 2] Cr _max = Y [YD <D _max / 2] To In the above equation, D _max is the maximum value of data that can be handled by the D / A converter, and YD is luminance signal data.

For example, in the case of an 8-bit D / A converter, 255 is D _max and D _max / 2 is 128. If the luminance signal data (YD) is 200, D _max / 2.
C _max is Cr _max = D _max -YD [YD> D _max / 2] = 200-128 = 72, and the color modulation component signal (Cr) should not exceed this value.
You just need to add gain to.

In the present embodiment, the device shown in FIG. 4 is an example of the modulation means (31), which is 14.875M.
The frequency of Hz is an example of n · F _SC , and in this case n
= 4.

[0045]

According to the present invention, the frequency of 14.1875.
Based on the reference clock of MHz, the frequency corresponding to the PAL system is 4.43 MHz and the phases of the signals are different by 90 °.
Color sub-carriers of different types are generated, color-difference data corresponding to each color-difference signal is modulated based on the color sub-carriers, and the output is D / A converted. Therefore, the main clock corresponding to the NTSC system is used. It is possible to support different NTSC and PAL systems by using a very close main clock.

Therefore, there is no need for a phase-locked loop circuit that uses two types of main clocks at the same time as in the conventional case, and it is possible to prevent the circuit structure from increasing in scale, and
It becomes possible to suppress the vertical stripe noise generated on the screen due to the interference of two kinds of frequencies.

[Brief description of drawings]

FIG. 1 is a first principle diagram of a video signal processing device according to the present invention.

FIG. 2 is a second principle diagram of a video signal processing device according to the present invention.

FIG. 3 is a first diagram illustrating a video signal processing method according to an embodiment of the present invention.

FIG. 4 is a block diagram showing an outline of a video signal processing device according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a video signal processing device according to an embodiment of the present invention.

FIG. 6 is a second diagram illustrating a video signal processing method according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a color encoder according to a conventional example.

FIG. 8 is a diagram illustrating a video signal processing method according to a conventional example.

[Explanation of symbols]

 (1) First latch circuit (2) First selector (3) First adder (4) Second latch circuit (5) Third latch circuit (6) Second selector (7) Second 2 adder (8) 1st inverter (9) 3rd selector (10) 4th latch circuit (11) 2nd inverter (12) 3rd adder (13) 4th selector (14) ) Fifth latch circuit (15) Fourth adder (31) Intermediate value generation means (32) Selection means (33) Digital / analog conversion means (34) Operation means (D1 to D10) First to tenth Data (RY, BY) Color difference signal (RY, BY) Color difference data

Claims (5)

[Claims] 1. At each timing of a reference clock having a constant cycle, a predetermined intermediate value is cyclically set for each common multiple cycle of the cycle of the reference clock and the modulation cycle of color information in a specific television system. A video signal processing method, characterized in that two types of color subcarriers corresponding to the television system and having different phases by 90 ° are generated based on the assigned and assigned intermediate values. 2. At each timing of a reference clock having a fixed cycle, a predetermined intermediate value is cyclically set for each common multiple cycle of the cycle of the reference clock and the modulation cycle of color information in a specific television system. Video signal processing characterized in that the assigned intermediate value is multiplied by the color difference signal data sequentially given at the timing according to the reference clock to perform amplitude modulation to generate carrier color signal data corresponding to the television system. Method. 3. Intermediate value data associated with a value obtained by sampling a positive ground wave signal having a modulation cycle of color information in a specific television system with a reference clock having a cycle shorter than that cycle is generated. Means and a plurality of generated intermediate value data, one data is cyclically selected in a predetermined order during a common multiple cycle of the cycle of the reference clock and the modulation cycle of the color information at a timing according to the reference clock. And a means for sequentially converting the selected data into an analog value to generate a color subcarrier corresponding to the television system. 4. Intermediate value data associated with a value obtained by sampling a positive ground wave signal having a modulation cycle of color information in a specific television system with a reference clock having a cycle shorter than that cycle is generated. Means for multiplying the generated color difference signal data by a plurality of generated intermediate value data at timings according to the reference clock, and the plurality of color difference signal data multiplied by the different intermediate value data from the reference clock Means for generating carrier color signal data by periodically selecting one data in a predetermined order during a common multiple cycle of the cycle of the reference clock and the modulation cycle of the color information at a timing according to
A video signal processing device comprising: 5. Intermediate value data associated with a value obtained by sampling a positive ground wave signal having a modulation cycle of color information in a specific television system with a reference clock having a cycle shorter than that cycle is generated. Means and a plurality of generated intermediate value data, one data is cyclically selected in a predetermined order during a common multiple cycle of the cycle of the reference clock and the modulation cycle of the color information at a timing according to the reference clock. And a means for multiplying the selected intermediate value data by the color difference signal data given at the timing according to the reference clock to generate the carrier color signal data, the video signal processing apparatus.