JPH104247A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH104247A
JPH104247A JP15682496A JP15682496A JPH104247A JP H104247 A JPH104247 A JP H104247A JP 15682496 A JP15682496 A JP 15682496A JP 15682496 A JP15682496 A JP 15682496A JP H104247 A JPH104247 A JP H104247A
Authority
JP
Japan
Prior art keywords
circuit board
sub
spare
connection
main circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15682496A
Other languages
Japanese (ja)
Inventor
Tsuneo Matsumura
常夫 松村
Naoaki Yamanaka
直明 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP15682496A priority Critical patent/JPH104247A/en
Publication of JPH104247A publication Critical patent/JPH104247A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Abstract

PROBLEM TO BE SOLVED: To shorten the period of system development, and to cut down cost by a method wherein connection parts are arranged on the circumferential part of a main circuit board, a subordinate circuit board and an auxiliary circuit board and all the auxiliary connection parts are connected directly to the circum ferential part of the auxiliary circuit board. SOLUTION: Discrete parts 12 to/from which data are transferred from/to a semiconductor part 11 are dispersively arranged on a substrate. The connection part 4, which is disposed on the backside of an auxiliary circuit board 10 where the semiconductor part 11 is mounted, is connected to the connection part 4 of the main circuit board 2, and the auxiliary circuit board 10 is mounted on the main circuit board 2. The connection part 4 disposed on the backside of the auxiliary subordinate circuit board 3 is mounted on the main circuit board 2. As a result, a system, which can be correspond to the change of function, can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、所望の機能を実現
するためにシステムが搭載する回路基板に関するもの
で、特に、機能の変更に柔軟に対応可能な開発初期段階
のシステムを実現するために、論理回路構成をフィール
ドで変更可能なプログラマブル半導体部品が搭載された
予備副回路基板及び複数の予備副回路基板が接続可能な
主回路基板を有すると共に、該主回路基板が商用段階の
システムで用いる高性能な半導体部品も搭載可能なこと
を特徴とする回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board mounted on a system for realizing a desired function, and more particularly to a system at an early stage of development which can flexibly respond to a change in function. A spare sub-circuit board on which a programmable semiconductor component whose logic circuit configuration can be changed in the field is mounted, and a main circuit board to which a plurality of spare sub-circuit boards can be connected, and the main circuit board is used in a system at a commercial stage The present invention relates to a circuit board on which high-performance semiconductor components can be mounted.

【0002】[0002]

【従来の技術】機能の変更に柔軟に対応可能な開発初期
段階のシステムを構築するために、主回路基板と予備副
回路基板を有する従来の回路基板を用いたシステム構成
例を、図6に示す。図中、1はシステム、2は半導体部
品(例えばゲートアレイLSI;図示せず)が搭載され
る主回路基板、3は予備副回路基板、4は主回路基板2
と予備副回路基板3を接続するための接続部品、4′は
接続部品4とは異なった種類(半導体部品形状に適合し
た種類)で、主回路基板2上に半導体部品を搭載するた
めの接続部品、5は主回路基板2に搭載される半導体部
品とは異なった電気的性質を有する他の半導体部品(例
えばFPGA等のプログラマブルLSI)、6は予備副
回路基板3上の複数の他の半導体部品5同士を互いに接
続し、かつ該接続状態を変更可能な接続切替部品、7は
接続部品4からの信号を接続部品4′に伝搬させるため
に該接続部品4′と同種の形状を備えた接続変換部品、
8は接続部品4と接続変換部品7をつなぐための接続ケ
ーブル、9は主回路基板2からの高速信号を低速にして
予備副回路基板3上の他の半導体部品5及び接続切替部
品6に伝搬させるための速度変換部品である。
2. Description of the Related Art FIG. 6 shows an example of a system configuration using a conventional circuit board having a main circuit board and a spare sub-circuit board in order to construct a system at an early stage of development capable of flexibly responding to a change in function. Show. In the figure, 1 is a system, 2 is a main circuit board on which semiconductor components (for example, a gate array LSI; not shown) are mounted, 3 is a spare sub-circuit board, 4 is a main circuit board 2
And 4 'are different types (types suitable for the shape of the semiconductor component) of the connection component 4 and the connection for mounting the semiconductor component on the main circuit board 2. The component 5 is another semiconductor component (for example, a programmable LSI such as an FPGA) having an electric property different from that of the semiconductor component mounted on the main circuit board 2, and 6 is a plurality of other semiconductors on the auxiliary sub circuit board 3. The connection switching component 7 that connects the components 5 to each other and can change the connection state. The connection switching component 7 has the same shape as the connection component 4 ′ in order to propagate a signal from the connection component 4 to the connection component 4 ′. Connection conversion parts,
Reference numeral 8 denotes a connection cable for connecting the connection component 4 and the connection conversion component 7, and 9 denotes a low-speed signal transmitted from the main circuit board 2 and transmitted to the other semiconductor components 5 and the connection switching component 6 on the auxiliary sub-circuit board 3. It is a speed conversion part for making it work.

【0003】従来の回路基板の構成では、半導体部品は
副回路基板(図示せず)に搭載されず、接続部品4′を
介して主回路基板2に接続される。ここで、半導体部品
を接続する主回路基板2上の接続部品4′と予備副回路
基板3上の接続部品4には図示のように互換性がないた
め、接続変換部品7及び接続ケーブル8を用いて互いの
基板間を接続する構成が採られていた。従って、主回路
基板2と予備副回路基板3間の信号伝搬遅延が大きなた
め、高速動作が可能な半導体部品を採用した高速システ
ムを対象とした場合、予備副回路基板3は、主回路基板
2上の半導体部品の機能変更に関わる検証(機能検証)
にのみ使用されていた。つまり、従来の回路基板の構成
では、予備副回路基板3は、機能変更を実施した場合の
高速半導体部品の性能検証及び高速システムの性能検証
には不適であった。また、これらら性能検証を従来の回
路基板の構成で実施する場合、本来の半導体部品では不
要な速度変換部品9を予備副回路基板3上に設け、該予
備副回路基板3内で入力信号群を低速かつビット幅の大
きな信号群に展開させ、主回路基板2上と予備副回路基
板3上での信号のトータルスループットを整合させる制
御が必要であった。この場合、速度変換に係る倍数だけ
他の半導体部品5及び接続切替部品6がさらに必要(例
えば1/2の速度変換に対して2倍の部品数)となるた
め、予備副回路基板3の大型化さらには基板自体の高速
動作を阻害することは避けられなかった。そのため、上
記性能検証のためにハードウェア量が大幅に増加すると
共に予備副回路基板3で半導体部品を模擬するための制
御が複雑になるという欠点を有していた。
In a conventional circuit board configuration, semiconductor components are not mounted on a sub-circuit board (not shown), but are connected to the main circuit board 2 via connecting components 4 '. Here, since the connection component 4 'on the main circuit board 2 for connecting the semiconductor component and the connection component 4 on the auxiliary sub circuit board 3 are not compatible as shown in the figure, the connection conversion component 7 and the connection cable 8 are connected. A configuration has been adopted in which the substrates are connected to each other by using the same. Therefore, the signal propagation delay between the main circuit board 2 and the auxiliary sub-circuit board 3 is large. Therefore, when a high-speed system employing semiconductor components capable of high-speed operation is targeted, the auxiliary sub-circuit board 3 Verification related to function change of above semiconductor components (Function verification)
Only used to. That is, in the configuration of the conventional circuit board, the spare sub-circuit board 3 is not suitable for the performance verification of the high-speed semiconductor component and the performance verification of the high-speed system when the function is changed. Further, when performing these performance verifications with a conventional circuit board configuration, a speed conversion component 9 that is unnecessary for the original semiconductor components is provided on the spare sub-circuit board 3, and the input signal group is stored in the spare sub-circuit board 3. Has to be developed into a low-speed and large-bit-width signal group, and control for matching the total throughput of signals on the main circuit board 2 and the auxiliary sub-circuit board 3 is required. In this case, another semiconductor component 5 and a connection switching component 6 are further required (for example, the number of components is twice as large as 1/2 of the speed conversion) by a multiple related to the speed conversion. Inevitably, it hinders high-speed operation of the substrate itself. Therefore, there is a disadvantage that the amount of hardware for the performance verification is greatly increased and the control for simulating the semiconductor component on the spare sub-circuit board 3 is complicated.

【0004】[0004]

【発明が解決しようとする課題】本発明は上記の事情に
鑑みてなされたもので、高速システムの性能検証に係る
上記問題点を解決して、機能の変更に柔軟に対応可能な
開発初期段階の該システムを実現する回路基板を提供す
ることを目的とする。さらに、本発明は、該回路基板
が、高性能な半導体部品を搭載する商用段階のシステム
でも使用でき、システム開発の期間短縮及びコスト低減
に寄与する回路基板を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and solves the above-mentioned problems relating to the performance verification of a high-speed system, and is an early development stage capable of flexibly responding to a change in function. It is an object of the present invention to provide a circuit board for realizing the above system. Still another object of the present invention is to provide a circuit board which can be used in a system at a commercial stage in which a high-performance semiconductor component is mounted on the circuit board, thereby contributing to a reduction in system development period and cost.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に本発明の回路基板は、(1)主回路基板,副回路基板
及び予備副回路基板から構成され、(2)機能の実現に
必要な半導体部品が副回路基板上に搭載され、(3)主
回路基板と副回路基板または予備副回路基板を直結して
接続できるように、同一種類の接続部品が主回路基板,
副回路基板及び予備副回路基板上に設けられ、(4)所
定の予備副回路基板を介して主回路基板と他の予備副回
路基板間を信号伝搬させるための予備接続部品が予備副
回路基板上に設けられ、(5)接続部品が主回路基板,
副回路基板及び予備副回路基板上の周辺部に、また予備
接続部品が予備副回路基板上の周辺部にすべて直結して
接続できるように配置されることを主要な特徴とする。
従来の技術とは主回路基板と複数の予備副回路基板が接
続部品及び予備接続部品を介し直結して接続できる点が
異なる。
In order to achieve the above object, a circuit board according to the present invention comprises (1) a main circuit board, a sub-circuit board, and a spare sub-circuit board, and (2) is required for realizing functions. (3) The same type of connecting parts are mounted on the main circuit board so that the main circuit board can be directly connected to the sub-circuit board or the spare sub-circuit board.
(4) A spare sub-circuit board is provided on the sub-circuit board and the spare sub-circuit board, and (4) a spare connection component for transmitting a signal between the main circuit board and another spare sub-circuit board via a predetermined spare sub-circuit board. (5) connecting parts are provided on the main circuit board,
The main feature is that the peripheral parts on the sub-circuit board and the spare sub-circuit board and the spare connection parts are arranged so as to be directly connected to the peripheral parts on the spare sub-circuit board.
The difference from the prior art is that a main circuit board and a plurality of spare sub-circuit boards can be directly connected and connected via connecting parts and spare connecting parts.

【0006】[0006]

【発明の実施の形態】以下図面を参照して本発明の実施
の形態例を詳細に説明する。図1は本発明の第1の実施
形態例を説明する図である。図中、図6と同一符号は図
6の同一部分に対応する。10は副回路基板、11は副
回路基板10に搭載される半導体部品で、例えばゲート
アレイLSIに相当する。12は半導体部品11とのデ
ータ授受が行われる個別部品で、メモリ等が対象とな
る。従来の回路基板においても、この個別部品12は基
板上に分散して配置されている。破線部Aは副回路基板
10または予備副回路基板3が搭載されるエリアであ
る。図1では、半導体部品11を搭載した副回路基板1
0の裏面に配設された接続部品4が主回路基板2の接続
部品4に接続されて、副回路基板10が主回路基板2に
搭載される。また、FPGA等に相当する他の半導体部
品5を搭載した予備副回路基板3の裏面に配設された接
続部品4が主回路基板2の接続部品4に接続されて、予
備副回路基板3が主回路基板2に搭載される。従って、
従来例における接続ケーブル8等が不要となるため、主
回路基板2と予備副回路基板3間及び主回路基板2と副
回路基板10間の高速な信号伝搬が可能となる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram illustrating a first embodiment of the present invention. 6, the same reference numerals as those in FIG. 6 correspond to the same parts in FIG. Reference numeral 10 denotes a sub-circuit board, and 11 denotes a semiconductor component mounted on the sub-circuit board 10, which corresponds to, for example, a gate array LSI. Reference numeral 12 denotes an individual component for exchanging data with the semiconductor component 11, which is a memory or the like. Also in a conventional circuit board, the individual components 12 are dispersedly arranged on the board. A broken line portion A is an area where the sub-circuit board 10 or the spare sub-circuit board 3 is mounted. In FIG. 1, a sub-circuit board 1 on which a semiconductor component 11 is mounted is shown.
The connection component 4 disposed on the back surface of the main circuit board 2 is connected to the connection component 4 of the main circuit board 2, and the sub-circuit board 10 is mounted on the main circuit board 2. Further, the connection component 4 provided on the back surface of the spare sub-circuit board 3 on which another semiconductor component 5 corresponding to an FPGA or the like is mounted is connected to the connection component 4 of the main circuit board 2, and the spare sub-circuit board 3 is Mounted on the main circuit board 2. Therefore,
Since the connection cable 8 and the like in the conventional example become unnecessary, high-speed signal propagation between the main circuit board 2 and the spare sub-circuit board 3 and between the main circuit board 2 and the sub-circuit board 10 can be performed.

【0007】図2(a),(b)は本発明の第2の実施
形態例を示すもので、特に予備副回路基板3の2種類の
構成例を説明する基板裏面から見た図である。図中、図
1及び図6と同一符号は図1及び図6の同一部分に対応
する。図2(a),(b)では、半導体部品11の機能
を実現するために複数の他の半導体部品5を予備副回路
基板3の表裏両面に搭載する点、さらに複数の他の半導
体部品5同士の接続状態が変更できる接続切替回路6も
併せて搭載する点に特徴がある。その結果、ゲート規模
が中規模な半導体部品11の機能を予備副回路基板3で
実現できる。
FIGS. 2 (a) and 2 (b) show a second embodiment of the present invention, and are views seen from the back surface of the substrate, illustrating two types of configuration examples of the auxiliary sub-circuit substrate 3. FIG. . In the figure, the same reference numerals as those in FIGS. 1 and 6 correspond to the same parts in FIGS. 2A and 2B, a plurality of other semiconductor components 5 are mounted on the front and back surfaces of the spare sub-circuit board 3 in order to realize the function of the semiconductor component 11. It is characterized in that a connection switching circuit 6 that can change the connection state between them is also mounted. As a result, the function of the semiconductor component 11 having a medium gate size can be realized by the spare sub-circuit board 3.

【0008】図3は本発明の第3の実施形態例を示すも
ので、さらにゲート規模が大きな半導体部品11の機能
を予備副回路基板3で実現するための構成例を基板上方
から見た図である。図中、図1及び図6と同一符号は図
1及び図6の同一部分に対応する。図3では、主回路基
板2の表裏両面に接続部品4が搭載され、かつ該接続部
品4の全部もしくは一部分が互いに該主回路基板2を通
して電気的に接続される構成が特徴である。この場合、
図中、斜線部分の接続部品4は主回路基板2に設けら
れ、斜線ない部分の接続部品4は予備副回路基板3に設
けられる。その結果、該接続部品4を介して主回路基板
2の表裏両面に接続された予備副回路基板3間でデータ
の授受が可能となり、該予備副回路基板3を2枚用いて
半導体部品11の機能を実現することが可能となる。な
お、本実施形態例には図示されていないが、該予備副回
路基板3は本発明の第2の実施形態例の構成(図2)を
採ることも本発明の範疇に属する。
FIG. 3 shows a third embodiment of the present invention. FIG. 3 is a diagram showing a configuration example for realizing the function of the semiconductor component 11 having a larger gate size on the spare sub-circuit board 3 as viewed from above the board. It is. In the figure, the same reference numerals as those in FIGS. 1 and 6 correspond to the same parts in FIGS. FIG. 3 is characterized in that connection parts 4 are mounted on both front and back surfaces of the main circuit board 2, and all or a part of the connection parts 4 are electrically connected to each other through the main circuit board 2. in this case,
In the figure, the connection parts 4 in the shaded area are provided on the main circuit board 2, and the connection parts 4 in the area without the shaded area are provided on the auxiliary sub-circuit board 3. As a result, data can be exchanged between the auxiliary sub-circuit boards 3 connected to the front and back surfaces of the main circuit board 2 via the connection parts 4, and the two auxiliary sub-circuit boards 3 are used. The function can be realized. Although not shown in the present embodiment, the spare sub-circuit board 3 adopts the configuration (FIG. 2) of the second embodiment of the present invention, which also belongs to the category of the present invention.

【0009】図4は本発明の第4の実施形態例を示すも
ので、複数の半導体部品11により実現される1つ以上
の機能を1枚の予備副回路基板3で実現するための構成
例を説明する図である。図中、図1及び図6と同一符号
は図1及び図6の同一部分に対応する。即ち、主回路基
板2の表面には副回路基板10が搭載されるエリアAを
挟むようにして多数の接続部品4が配設される。一方、
予備副回路基板3の表面には多数の他の半導体部品5が
配設され、予備副回路基板3の裏面には多数の接続部品
4が配設される。又、個別部品12は予備副回路基板3
の表裏面に分散配置される。図4では、今まで説明して
きた本発明の実施形態例と同様に、主回路基板2と予備
副回路基板3は接続部品4により接続される。なお、本
実施形態例には図示されていないが、該予備副回路基板
3は本発明の第2の実施形態例の構成(図2)を採るこ
とも本発明の範疇に属する。
FIG. 4 shows a fourth embodiment of the present invention, in which one or more functions realized by a plurality of semiconductor components 11 are realized by one spare sub-circuit board 3. FIG. In the figure, the same reference numerals as those in FIGS. 1 and 6 correspond to the same parts in FIGS. That is, a large number of connection components 4 are arranged on the surface of the main circuit board 2 so as to sandwich the area A on which the sub-circuit board 10 is mounted. on the other hand,
A large number of other semiconductor components 5 are arranged on the front surface of the auxiliary sub-circuit board 3, and a large number of connection components 4 are arranged on the back surface of the auxiliary sub-circuit board 3. Also, the individual component 12 is a spare sub-circuit board 3
Are dispersedly arranged on the front and back surfaces. In FIG. 4, the main circuit board 2 and the auxiliary sub-circuit board 3 are connected by the connection component 4, similarly to the embodiment of the present invention described so far. Although not shown in the present embodiment, the spare sub-circuit board 3 adopts the configuration (FIG. 2) of the second embodiment of the present invention, which also belongs to the category of the present invention.

【0010】図5(a),(b),(c)は本発明の第
5の実施形態例を示すもので、主回路基板2上にゲート
規模が非常に大きな半導体部品11が複数搭載される場
合に対応した回路基板構成例を説明する図であり、図5
(a)はシステムを示す一部切欠斜視図、図5(b)は
主回路基板と予備副回路基板を上方から見た図、図5
(c)は予備副回路基板の斜視図である。本実施形態例
の回路基板構成では、主回路基板2と複数の予備副回路
基板3は同一のシステム内に近接して配置される。図
中、図1及び図6と同一符号は図1及び図6の同一部分
に対応する。13は予備副回路基板3に搭載される予備
接続部品である。該予備副回路基板3の表裏に配置され
た該予備接続部品13同士は該予備副回路基板3を通し
て電気的接続される。予備接続部品13が搭載された予
備副回路基板3の裏面には接続部品4が配設される。
又、個別部品12は予備副回路基板3の表裏面に分散配
置される。図5(a),(b),(c)では、システム
1に搭載された最も右側にある予備副回路基板3は、右
側から2番目の予備副回路基板3上に設けられた予備接
続部品13及び接続部品4のみを介して主回路基板2と
電気的に接続される。従って、本実施形態例によれば、
FPGA等のプログラマブルLSIが多数搭載された複
数の予備副回路基板3を最も信号伝搬遅延量の小さな形
式で主回路基板2と接続できるため、高速・大容量ゲー
トアレイLSIが搭載された複数の副回路基板10を有
する該主回路基板2と同等の高速性能を得ることがで
き、かつ実現する機能の変更も容易に行うこともでき
る。なお、本実施形態例には図示されていないが、該予
備副回路基板3は本発明の第2の実施形態例の構成(図
2)を採ることも本発明の範疇に属する。
FIGS. 5 (a), 5 (b) and 5 (c) show a fifth embodiment of the present invention, in which a plurality of semiconductor components 11 having a very large gate size are mounted on a main circuit board 2. FIG. FIG. 5 is a diagram for explaining a circuit board configuration example corresponding to the case where
5A is a partially cutaway perspective view showing the system, FIG. 5B is a view of the main circuit board and the auxiliary sub circuit board viewed from above, and FIG.
(C) is a perspective view of the auxiliary sub-circuit board. In the circuit board configuration of the present embodiment, the main circuit board 2 and the plurality of auxiliary sub-circuit boards 3 are arranged close to each other in the same system. In the figure, the same reference numerals as those in FIGS. 1 and 6 correspond to the same parts in FIGS. Reference numeral 13 denotes a spare connection component mounted on the spare sub-circuit board 3. The spare connection parts 13 arranged on the front and back of the spare sub circuit board 3 are electrically connected to each other through the spare sub circuit board 3. The connection component 4 is disposed on the back surface of the auxiliary sub-circuit board 3 on which the auxiliary connection component 13 is mounted.
Further, the individual components 12 are dispersedly arranged on the front and back surfaces of the spare sub-circuit board 3. 5A, 5B, and 5C, the rightmost spare sub-circuit board 3 mounted on the system 1 is a spare connection component provided on the second spare sub-circuit board 3 from the right. It is electrically connected to main circuit board 2 only through 13 and connecting parts 4. Therefore, according to the present embodiment,
A plurality of auxiliary sub-circuit boards 3 on which a large number of programmable LSIs such as FPGAs are mounted can be connected to the main circuit board 2 in a form having the smallest signal propagation delay. High-speed performance equivalent to that of the main circuit board 2 having the circuit board 10 can be obtained, and the function to be realized can be easily changed. Although not shown in the present embodiment, the spare sub-circuit board 3 adopts the configuration (FIG. 2) of the second embodiment of the present invention, which also belongs to the category of the present invention.

【0011】以上のように本発明の実施形態例には、次
のような特徴を有する回路基板が含まれる。 (1) システムに搭載されて1つ以上の機能を実現す
る回路基板において、該機能の実現に必要なL個(Lは
1以上の整数)の半導体部品が分配して搭載されるM枚
(M≦L,Mは1以上の整数)の副回路基板と、M枚の
該副回路基板が接続部品を介し直結して接続される主回
路基板と、該半導体部品とは異なった電気的性質により
該機能を実現するN個(Nは1以上の整数)の他の半導
体部品を搭載するK枚(N≧L/K,Kは1以上の整
数)の予備副回路基板と、該副回路基板と該予備副回路
基板に搭載される同一種類の接続部品とを有し、M枚の
該副回路基板が未搭載である該主回路基板が、同一種類
の該接続部品を介してK枚の該予備副回路基板と直結し
て接続されることを特徴とする回路基板。
As described above, the embodiment of the present invention includes a circuit board having the following features. (1) On a circuit board mounted on a system and realizing one or more functions, L (L is an integer of 1 or more) semiconductor parts necessary for realizing the functions are distributed and mounted on M substrates ( (M ≦ L, M is an integer of 1 or more) a sub-circuit board, a main circuit board to which M sub-circuit boards are directly connected via connection components, and electrical characteristics different from those of the semiconductor component K (N ≧ L / K, K is an integer of 1 or more) spare sub-circuit boards on which N (N is an integer of 1 or more) other semiconductor components for realizing the function are provided. A main circuit board which has a board and the same type of connecting parts mounted on the spare sub-circuit board, and on which the M sub-circuit boards are not mounted; A circuit board directly connected to said spare sub-circuit board.

【0012】(2) Nが2以上の他の半導体部品を搭
載する予備副回路基板において、他の該半導体部品同士
を相互接続し、かつ該接続状態を変更可能な接続切替部
品を搭載することを特徴とする(1)記載の回路基板。
(2) On a spare sub-circuit board on which N is mounted two or more other semiconductor parts, a connection switching part for interconnecting the other semiconductor parts and changing the connection state is mounted. (1) The circuit board according to (1).

【0013】(3) 主回路基板において、該主回路基
板の表裏両面に接続部品が搭載され、かつ該接続部品の
一部分が互いに該主回路基板を通して電気的に接続され
ることを特徴とする(1)又は(2)記載の回路基板。
(3) In the main circuit board, connecting parts are mounted on both front and back surfaces of the main circuit board, and a part of the connecting parts is electrically connected to each other through the main circuit board. The circuit board according to 1) or 2).

【0014】(4) 予備副回路基板において、主回路
基板から所定の予備副回路基板を介して他の該予備副回
路基板に信号伝達のため、該予備副回路基板と他の該予
備副回路基板を接続する予備接続部品を搭載することを
特徴とする(1)、(2)又は(3)記載の回路基板。
(4) In the spare sub-circuit board, a signal is transmitted from the main circuit board to another spare sub-circuit board via a predetermined spare sub-circuit board, so that the spare sub-circuit board and the other spare sub-circuit are transmitted. The circuit board according to (1), (2) or (3), further comprising a spare connection component for connecting the board.

【0015】(5) 接続部品及び予備接続部品を用い
て、主回路基板とK枚の予備副回路基板がすべて互いに
直結して接続されることを特徴とする(1)、(2)、
(3)又は(4)記載の回路基板。
(5) The main circuit board and the K auxiliary sub-circuit boards are all directly connected to each other and connected by using the connecting parts and the spare connecting parts. (1), (2),
The circuit board according to (3) or (4).

【0016】(6) 接続部品及び予備接続部品が主回
路基板,副回路基板及び予備副回路基板上の周辺部に配
置されることを特徴とする(1)、(2)、(3)、
(4)又は(5)記載の回路基板。
(6) The connection parts and the auxiliary connection parts are arranged on the main circuit board, the sub-circuit board, and the peripheral part on the auxiliary sub-circuit board. (1), (2), (3),
The circuit board according to (4) or (5).

【0017】(7) 予備副回路基板に搭載する他の半
導体部品が、実現する論理回路構成をフィールドで変更
可能なプログラマブル半導体部品であることを特徴とす
る(1)、(2)、(3)、(4)、(5)又は(6)
記載の回路基板。
(7) Another semiconductor component mounted on the spare sub-circuit board is a programmable semiconductor component whose realizable logic circuit configuration can be changed in the field. (1), (2), (3) ), (4), (5) or (6)
The described circuit board.

【0018】[0018]

【発明の効果】以上説明したように、本発明の回路基板
によれば、最も小さな基板間の信号伝搬遅延量を有し、
かつ例えば多数のプログラマブルLSIを搭載したシス
テムを構築できるため、機能の変更に柔軟に対応可能な
システムが実現できるという利点がある。
As described above, according to the circuit board of the present invention, the signal propagation delay between the boards is the smallest.
In addition, for example, since a system equipped with a large number of programmable LSIs can be constructed, there is an advantage that a system capable of flexibly responding to a change in function can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態例を示す斜視図であ
る。
FIG. 1 is a perspective view showing a first embodiment of the present invention.

【図2】(a),(b)は本発明の第2の実施形態例を
示す斜視図である。
FIGS. 2A and 2B are perspective views showing a second embodiment of the present invention.

【図3】本発明の第3の実施形態例を示す上面図であ
る。
FIG. 3 is a top view showing a third embodiment of the present invention.

【図4】本発明の第4の実施形態例を示す斜視図であ
る。
FIG. 4 is a perspective view showing a fourth embodiment of the present invention.

【図5】本発明の第5の実施形態例を示し、(a)はシ
ステムの斜視図、(b)は主回路基板及び予備副回路基
板の上面図、(c)は予備副回路基板の斜視図である。
5A and 5B show a fifth embodiment of the present invention, wherein FIG. 5A is a perspective view of a system, FIG. 5B is a top view of a main circuit board and a spare sub-circuit board, and FIG. It is a perspective view.

【図6】従来の回路基板を用いたシステム構成を示す斜
視図である。
FIG. 6 is a perspective view showing a system configuration using a conventional circuit board.

【符号の説明】[Explanation of symbols]

1…システム、2…主回路基板、3…予備副回路基板、
4…接続部品、4′…接続部品4とは異なった種類(半
導体部品形状に適合した種類)で、主回路基板2上に半
導体部品を搭載するための接続部品、5…主回路基板2
に搭載される半導体部品とは異なった電気的性質を有す
る他の半導体部品(例えばFPGA等のプログラマブル
LSI)、6…接続切替部品、7…接続変換部品、8…
接続ケーブル、9…速度変換部品、10…副回路基板、
11…半導体部品、12…個別部品、13…予備接続部
品。
DESCRIPTION OF SYMBOLS 1 ... System, 2 ... Main circuit board, 3 ... Spare auxiliary circuit board,
Reference numeral 4 denotes a connection component, 4 ': a connection component for mounting a semiconductor component on the main circuit board 2 of a type different from the connection component 4 (a type adapted to the shape of the semiconductor component), and 5: a main circuit board 2
Other semiconductor components (for example, programmable LSI such as FPGA) having electrical properties different from the semiconductor components mounted on the semiconductor device; 6, a connection switching component; 7, a connection conversion component;
Connection cable, 9: speed conversion component, 10: sub-circuit board,
11: semiconductor parts, 12: individual parts, 13: spare connection parts.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 システムに搭載されて1つ以上の機能を
実現する回路基板において、 該機能の実現に必要なL個(Lは1以上の整数)の半導
体部品が分配して搭載されるM枚(M≦L,Mは1以上
の整数)の副回路基板と、 M枚の該副回路基板が接続部品を介し直結して接続され
る主回路基板と、 該半導体部品とは異なった電気的性質により該機能を実
現するN個(Nは1以上の整数)の他の半導体部品を搭
載するK枚(N≧L/K,Kは1以上の整数)の予備副
回路基板と、 該副回路基板と該予備副回路基板に搭載される同一種類
の接続部品とを有し、 M枚の該副回路基板が未搭載である該主回路基板が、同
一種類の該接続部品を介してK枚の該予備副回路基板と
直結して接続されることを特徴とする回路基板。
1. A circuit board which is mounted on a system and realizes one or more functions, wherein L (L is an integer of 1 or more) semiconductor components necessary for realizing the functions are distributed and mounted. A number of sub-circuit boards (M ≦ L, M is an integer of 1 or more), a main circuit board to which M sub-circuit boards are directly connected via connection components, and an electric power different from the semiconductor components K (N ≧ L / K, K is an integer of 1 or more) spare sub-circuit boards on which N (N is an integer of 1 or more) other semiconductor components for realizing the function according to the characteristic are provided; A main circuit board having the sub-circuit board and the same type of connecting parts mounted on the spare sub-circuit board, and the M sub-circuit boards not being mounted, through the same type of connecting parts; A circuit board directly connected to and connected to the K spare sub-circuit boards.
【請求項2】 Nが2以上の他の半導体部品を搭載する
予備副回路基板において、他の該半導体部品同士を相互
接続し、かつ該接続状態を変更可能な接続切替部品を搭
載することを特徴とする請求項1記載の回路基板。
2. A spare sub-circuit board on which another semiconductor component in which N is 2 or more is mounted with a connection switching component that interconnects the other semiconductor components and that can change the connection state. The circuit board according to claim 1, wherein:
【請求項3】 主回路基板において、該主回路基板の表
裏両面に接続部品が搭載され、かつ該接続部品の一部分
が互いに該主回路基板を通して電気的に接続されること
を特徴とする請求項1又は2記載の回路基板。
3. The main circuit board, wherein connection parts are mounted on both front and back surfaces of the main circuit board, and a part of the connection parts is electrically connected to each other through the main circuit board. 3. The circuit board according to 1 or 2.
【請求項4】 予備副回路基板において、主回路基板か
ら所定の予備副回路基板を介して他の該予備副回路基板
に信号伝達のため、該予備副回路基板と他の該予備副回
路基板を接続する予備接続部品を搭載することを特徴と
する請求項1,2又は3記載の回路基板。
4. The spare sub-circuit board and another spare sub-circuit board for transmitting a signal from the main circuit board to another spare sub-circuit board via a predetermined spare sub-circuit board. 4. The circuit board according to claim 1, further comprising a spare connection component for connecting the circuit board.
【請求項5】 接続部品及び予備接続部品を用いて、主
回路基板とK枚の予備副回路基板がすべて互いに直結し
て接続されることを特徴とする請求項1,2,3又は4
記載の回路基板。
5. The main circuit board and the K auxiliary sub-circuit boards are all directly connected to each other and connected, using the connecting parts and the spare connecting parts.
The described circuit board.
【請求項6】 接続部品及び予備接続部品が主回路基
板,副回路基板及び予備副回路基板上の周辺部に配置さ
れることを特徴とする請求項1,2,3,4又は5記載
の回路基板。
6. The method according to claim 1, wherein the connecting parts and the auxiliary connecting parts are arranged on the peripheral parts on the main circuit board, the sub-circuit board and the auxiliary sub-circuit board. Circuit board.
【請求項7】 予備副回路基板に搭載する他の半導体部
品が、実現する論理回路構成をフィールドで変更可能な
プログラマブル半導体部品であることを特徴とする請求
項1,2,3,4,5又は6記載の回路基板。
7. The semiconductor device according to claim 1, wherein the other semiconductor component mounted on the spare sub-circuit board is a programmable semiconductor component whose realizable logic circuit configuration can be changed in a field. Or the circuit board according to 6.
JP15682496A 1996-06-18 1996-06-18 Circuit board Pending JPH104247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15682496A JPH104247A (en) 1996-06-18 1996-06-18 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15682496A JPH104247A (en) 1996-06-18 1996-06-18 Circuit board

Publications (1)

Publication Number Publication Date
JPH104247A true JPH104247A (en) 1998-01-06

Family

ID=15636156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15682496A Pending JPH104247A (en) 1996-06-18 1996-06-18 Circuit board

Country Status (1)

Country Link
JP (1) JPH104247A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016159453A (en) * 2015-02-27 2016-09-05 理想科学工業株式会社 Substrate connection system and ink-jet recording device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016159453A (en) * 2015-02-27 2016-09-05 理想科学工業株式会社 Substrate connection system and ink-jet recording device

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