JPH1041477A - Ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory having an excellent element characteristic and easy to manufacture. SOLUTION: An N-channel ZnO layer 2 is formed on the (111) plane of a Si substrate 1. On the surface of the N-channel ZnO layer 2,<+> p layers 3, 4 are formed at a prescribed interval, and a ferroelectric layer 5 made of an LiTaO3 is formed on a region of the N-channel ZnO layer 2 between the<+> p layers 3, 4. A source electrode and 6 drain electrode 7 are formed respectively on the<+> p layers 3, 4 and a gate electrode 8 is formed on the ferroelectric layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory for performing a nonvolatile memory operation.

[0002]

2. Description of the Related Art Hitherto, a ferroelectric memory performing a nonvolatile memory operation has been proposed. FIG. 6 is a schematic sectional view showing an example of a conventional ferroelectric memory.

In FIG. 6, n ⁺ layers 42 and 43 are formed at a predetermined interval on the surface of a p-type Si (silicon) substrate 41, and are formed on a region of the p-type Si substrate 41 between the n ⁺ layers 42 and 43. A ferroelectric layer 44 made of a metal oxide is formed. A source electrode 45 and a drain electrode 46 are formed on the n ⁺ layers 42 and 43, respectively, and a gate electrode 47 is formed on the ferroelectric layer 44. Thus, this ferroelectric memory has an FET (field effect transistor) structure.

Here, the principle of operation of the ferroelectric memory shown in FIG. 6 will be described. When a predetermined positive voltage is applied to the gate electrode 47, the ferroelectric layer 44 is polarized, the interface of the ferroelectric layer 44 with the gate electrode 47 is negatively charged, and the p-type Si substrate 4
1 is positively charged. Thereby, the n ⁺ layer 42,
A channel is formed in a region of the p-type Si substrate 41 between the 43. Therefore, when a source-drain voltage is applied, a current flows between the source and the drain. Ferroelectric layer 4
If 4 is sufficiently polarized, a current flows between the source and the drain even after the voltage applied to the gate electrode 47 is set to 0. That is, operation as a nonvolatile memory is enabled.

[0005]

However, in the above-mentioned conventional ferroelectric memory, the interface between the Si substrate 41 and the ferroelectric layer 44 has a thickness of several hundreds of degrees.
Mutual diffusion of atoms and constituent atoms of the ferroelectric layer 44 occurs.
Thereby, the interface of the ferroelectric layer 44 does not exhibit ferroelectricity. When the ferroelectric layer 44 repeats polarization,
Oxygen in the ferroelectric layer 44 is taken into the Si substrate 41, and oxygen defects occur near the interface of the ferroelectric layer 44. Thus, there is a problem that the ferroelectric layer 44 having a good interface does not exist on the Si substrate 41. Therefore, various methods have been proposed to improve the interface between the substrate and the ferroelectric layer.

The first method is to use La instead of Si substrate.
A (lanthanum) -doped STO (SrTiO ₃ ) substrate is used, and a ferroelectric layer is formed on the STO substrate. According to this method, since the STO substrate itself is an oxide, it is difficult to take in oxygen from the ferroelectric layer.
Therefore, the interface between the STO layer and the ferroelectric layer is improved. However, STO substrates are expensive, and ST
It is difficult to form a peripheral circuit on an O substrate.

The second method is to form a La-doped STO layer on a Si substrate and form a ferroelectric layer on the STO layer. According to this method, similarly to the first method, the interface between the STO layer and the ferroelectric layer is improved. However, the structure becomes complicated, and a technique for forming an STO layer on a Si substrate has not been established.

The third method is to form a stable buffer layer on a Si substrate to prevent mutual diffusion and to form a ferroelectric layer on the buffer layer. FIG. 7 is a schematic sectional view of a conventional ferroelectric memory using a buffer layer.

In FIG. 7, CeO is placed on a Si substrate 51._Two
A buffer layer 52 is formed and CeO _TwoOn the buffer layer 52
PbTiO_ThreeA ferroelectric layer 53 is formed. this
PbTiO_ThreeGate electrode 54 is formed on ferroelectric layer 53
Have been. CeO_TwoThe thickness of the buffer layer 52 is 1 μm or less.
Is necessary.

[0010] In the ferroelectric memory of FIG. 7, a stable C is placed between the Si substrate 51 and the PbTiO ₃ ferroelectric layer 53.
Since the eO ₂ buffer layer 52 is provided, PbTi
The interface of the O ₃ ferroelectric layer 53 becomes good. However, since the thick CeO ₂ buffer layer 52 needs to be formed on the Si substrate 51, the manufacturing process is complicated and the manufacturing time is long. Also, the Si substrate 51 and Pb
Since the thick CeO ₂ buffer layer 52 exists between the TiO ₃ ferroelectric layer 53 and the TiO ₃ ferroelectric layer 53, the device characteristics as an FET become poor.

An object of the present invention is to have good device characteristics,
An object of the present invention is to provide a ferroelectric memory that can be easily manufactured.

[0012]

According to the ferroelectric memory of the present invention, first and second electrodes are formed on a semiconductor layer at predetermined intervals, and the first and second electrodes are formed.
A ferroelectric layer made of an oxide is formed on a region of the semiconductor layer between the electrodes, and a third electrode is formed on the ferroelectric layer. The semiconductor layer has a higher reduction than the ferroelectric layer. It has the property. The semiconductor layer may be a semiconductor layer formed on a substrate, or may be a semiconductor layer formed on a semiconductor substrate. The semiconductor layer is preferably made of zinc oxide.

In this ferroelectric memory, when a voltage is applied to the third electrode, the ferroelectric layer is polarized, and a channel is formed in a region of the semiconductor layer between the first electrode and the second electrode. You. Thus, when a voltage is applied between the first electrode and the second electrode, a current flows between the first electrode and the second electrode via the channel.

Since the polarization of the ferroelectric layer continues even after the application of the voltage to the third electrode is stopped, when a voltage is applied between the first electrode and the second electrode, the polarization through the channel occurs. First
Current flows between the first electrode and the second electrode. Thus, a non-volatile memory operation is realized.

In the ferroelectric memory according to the present invention,
Since the semiconductor layer has a higher reducing property than the ferroelectric layer, oxygen in the ferroelectric layer is less likely to be taken into the semiconductor layer, and oxygen defects are generated near the interface of the ferroelectric layer even after repeated polarization. This is prevented from occurring. Therefore, a ferroelectric layer having a good interface is formed on the semiconductor layer, and good device characteristics can be obtained.

In particular, an oxide semiconductor layer is formed on a substrate, first and second electrodes are formed on the oxide semiconductor layer at a predetermined interval, and a gap between the first electrode and the second electrode is formed. An oxide ferroelectric layer is formed on the region of the oxide semiconductor layer, and a third electrode is formed on the oxide ferroelectric layer, and the oxide semiconductor layer is higher than the oxide ferroelectric layer. It may have a reducing property. Note that the oxide semiconductor layer may be formed directly over the substrate, or may be formed over a layer over the substrate.

In this case, when a voltage is applied to the third electrode, a channel is formed in a region of the oxide semiconductor layer between the first electrode and the second electrode. That is, the oxide semiconductor layer functions as a channeling layer.

[0018] An oxide semiconductor layer can be easily formed over the substrate. Further, since the oxide semiconductor layer has a high reducing property with respect to the oxide ferroelectric layer, generation of oxygen vacancies near the interface of the oxide ferroelectric layer is prevented. Further, since the oxide semiconductor layer exists between the substrate and the oxide ferroelectric layer, interdiffusion of atoms between the substrate and the oxide ferroelectric layer does not occur. Therefore, the interface between the oxide semiconductor layer and the oxide ferroelectric layer is good, and a favorable nonvolatile memory operation is realized.

In particular, the substrate is preferably a semiconductor substrate, and is preferably made of a silicon substrate. Further, the oxide semiconductor layer is preferably formed using zinc oxide. In this case, zinc oxide can be easily formed on the silicon substrate.

Further, first and second electrodes are formed on the semiconductor substrate at predetermined intervals, and an oxide semiconductor layer and an oxide are formed on a region of the semiconductor substrate between the first electrode and the second electrode. The material ferroelectric layer and the third electrode may be sequentially formed, and the oxide semiconductor layer may have a higher reducing property than the oxide ferroelectric layer. Note that the first electrode, the second electrode, and the oxide semiconductor layer may be formed directly over the semiconductor substrate or may be formed over the semiconductor layer over the semiconductor substrate.

In this case, when a voltage is applied to the third electrode, a channel is formed in a region of the semiconductor substrate between the first electrode and the second electrode. That is, the semiconductor substrate functions as a channeling layer.

An oxide semiconductor layer can be easily formed over a semiconductor substrate. Further, since the oxide semiconductor layer has a high reducing property with respect to the oxide ferroelectric layer, oxygen in the oxide ferroelectric layer is not taken into the oxide semiconductor layer, and Occurrence of oxygen vacancies near the interface of the layers is prevented. Furthermore, since the oxide semiconductor layer exists between the semiconductor substrate and the oxide ferroelectric layer, mutual diffusion of atoms between the semiconductor substrate and the oxide ferroelectric layer does not occur. Therefore, the interface between the oxide semiconductor layer and the oxide ferroelectric layer is good, and a favorable nonvolatile memory operation is realized.

In particular, the semiconductor substrate is preferably made of a silicon substrate. Further, the oxide semiconductor layer is preferably formed using zinc oxide. In this case, zinc oxide can be easily formed on the silicon substrate.

In particular, the substrate is a silicon substrate having a (111) plane, and the oxide semiconductor layer is a silicon substrate having a (1) plane.
11) It is preferably made of zinc oxide formed on the surface. The zinc oxide may be formed directly on the (111) plane of the silicon substrate, or may be formed on the (1) surface of the silicon substrate.
11) It may be formed on a silicon layer on the surface.

On the (111) plane of the silicon substrate, zinc oxide having a plane orientation (001) is easily epitaxially grown.
On the (001) plane of zinc oxide, a trigonal or hexagonal oxide ferroelectric is easily epitaxially grown. Further, by terminating dangling bonds on the surface of the silicon substrate with zinc, a favorable interface can be formed between the silicon substrate and the oxide semiconductor layer. Also,
Since zinc oxide has a high reducing property with respect to the oxide ferroelectric layer, generation of oxygen vacancies near the interface of the oxide ferroelectric layer can be prevented. Therefore, a ferroelectric memory having better nonvolatile memory characteristics can be easily manufactured.

Preferably, the semiconductor layer is made of a trigonal or hexagonal oxide semiconductor, and the ferroelectric layer is made of a trigonal or hexagonal ferroelectric. In this case, since the oxide semiconductor has a high reducing property with respect to the ferroelectric, oxygen is not taken into the semiconductor layer from the ferroelectric layer,
Oxygen deficiency near the interface of the ferroelectric layer is prevented. Further, a trigonal or hexagonal ferroelectric is easily epitaxially grown on a trigonal or hexagonal oxide semiconductor. Therefore, a good interface between the semiconductor layer and the ferroelectric layer can be easily formed.

[0027]

FIG. 1 is a schematic sectional view of a ferroelectric memory according to an embodiment of the present invention. In FIG.
An n-type ZnO layer 2 is formed on a (111) plane of a Si substrate 1. on the surface of the n-type ZnO layer 2 p ⁺ layer (high impurity concentration layer) at a predetermined distance 3,4 it is formed, LiTaO over the area of the n-type ZnO layer 2 between the p ⁺ layer 3, 4
_A ferroelectric layer 5 made of ₃ (lithium tantalate) is formed. Source electrodes 6 are formed on p ⁺ layers 3 and 4 respectively.
And a drain electrode 7, and a gate electrode 8 is formed on the ferroelectric layer 5.

Next, a method of manufacturing the ferroelectric memory shown in FIG. 1 will be described. FIG. 2 is a schematic diagram of an ECR (Electron Cyclotron Resonance) ion beam sputtering apparatus used for manufacturing the ferroelectric memory of FIG.

In FIG. 2, an ECR ion source 12 and a Kauffman ion source 13 are installed in a reaction chamber 11. In the reaction chamber 11, a substrate holder 14 and a target holder 15 are installed.
i substrate 1 is mounted, and Zn
(Zinc) target 15A, LiTaO ₃ target 1
5B and an Al (aluminum) target 15C are mounted. Further, a main valve 16 is provided in the reaction chamber 11, and a turbo pump 17, a cryopump 18 and a rotary pump 19 are provided as an exhaust system.

First, a 300 μm-thick Si substrate 1 is subjected to thermal annealing at 800 ° C. for 1 hour or more.
The natural oxide film on the surface is removed. Thereafter, an n-type ZnO layer 2 having a thickness of 100 nm is formed on the (111) plane of the Si substrate 1 by an ion beam sputtering method. In this case, the dangling bond on the surface of the Si substrate 1 is first deposited by depositing Zn at a growth rate of 30 ° / min for 5 to 10 seconds.
After terminating with n, ZnO is grown. Thereby, S
A good interface is obtained between the i-substrate 1 and the n-type ZnO layer 2. When forming the n-type ZnO layer 2, the Zn target 15
A is used, and Al is used as the n-type dopant. ZnO
Table 1 shows the conditions for forming the layer 2.

[0031]

[Table 1]

Next, p ⁺ layers 3 and 4 are formed on the surface of the n-type ZnO layer 2 at predetermined intervals by ion implantation. p
As a type dopant, Li (lithium), Na (sodium), or the like is used.

Next, n-type Zn between the p ⁺ layers 3 and 4
On the region of the O layer 2, a 300 nm-thick L was formed by ion beam sputtering using a LiTaO ₃ target 15B.
A ferroelectric layer 5 made of iTaO ₃ is formed. Table 2 shows the conditions for forming the ferroelectric layer 5.

[0034]

[Table 2]

After that, on the p ⁺ layers 3 and 4, a thickness of 3 was formed by ion beam sputtering using an Al target 15 C.
A source electrode 6 and a drain electrode 7 made of Al having a thickness of 00 nm are formed, and a gate electrode 8 made of Al having a thickness of 300 nm is formed on the ferroelectric layer 5 by an ion beam sputtering method. The distance between the source electrode 6 and the drain electrode 7 is 200 μm. Table 3 shows the conditions for forming the source electrode 6, the drain electrode 7, and the gate electrode 8.

[0036]

[Table 3]

The source electrode 6, the drain electrode 7, and the gate electrode 8 may be made of Pt, Au, or the like. Next, the operation of the ferroelectric memory manufactured as described above will be described. When a negative gate voltage is applied to the gate electrode 8, the interface of the ferroelectric layer 5 with the gate electrode 8 is positively charged, and the interface with the n-type ZnO layer 2 is negatively charged. Thereby, a channel is formed in the region of the n-type ZnO layer 2 between the p ⁺ layers 3 and 4. Therefore, when a source-drain voltage is applied, a current flows between the source and the drain. Since the polarization of the ferroelectric layer 5 is maintained even after the voltage applied to the gate electrode 8 is set to 0, when a voltage between the source and the drain is applied, a current flows between the source and the drain via the channel. Thus, a non-volatile memory operation is realized.

In the ferroelectric memory of the present embodiment,
On the (111) plane of the substrate 1, ZnO having a plane orientation (001)
Easily grows epitaxially. Further, since ZnO is a hexagonal crystal, a ferroelectric layer 5 having three-fold or six-fold symmetry is easily epitaxially grown on the (001) plane of the ZnO layer 2. Therefore, the manufacturing process becomes easy.

Further, by terminating the tongue bond on the surface of the Si substrate 1 with Zn, the Si substrate 1 and the ZnO layer 2 are terminated.
And a good interface can be formed between them. In addition, since ZnO has a higher reducibility than the ferroelectric layer 5, even if the polarization is repeated, oxygen in the ferroelectric layer 5 is changed to ZO.
Oxygen vacancies are prevented from being generated near the interface of the ferroelectric layer 5 without being taken into the nO layer 2. Thereby, Z
A good interface can be formed between the nO layer 2 and the ferroelectric layer 5.

FIG. 3 is a diagram showing a simulation result of element characteristics of the ferroelectric memory of FIG. The horizontal axis in FIG. 3 is the gate voltage applied to the gate electrode 8 first, and the vertical axis is the current value flowing between the source and the drain when the voltage applied to the gate electrode 8 is 0. The source-drain voltage is 10V.

According to the simulation results shown in FIG. 3, when a voltage of 40 V or more is applied to the gate electrode 8 to sufficiently polarize the ferroelectric layer 5, the voltage applied to the gate electrode 8 becomes zero.
It can be seen that a constant current between the source and the drain flows even after the setting. Therefore, the ferroelectric memory of FIG. 1 can perform a good nonvolatile memory operation. FIG. 4 is a schematic cross-sectional view showing an example in which the ferroelectric memory of FIG. 1 is formed on a Si substrate together with peripheral circuits.

As shown in FIG. 4, a ferroelectric memory 10 and a MOSFET (metal oxide semiconductor field effect transistor) 20 of this embodiment are formed on a Si substrate 1. MOSFET 20 is formed on source region 21 and drain region 22 formed at predetermined intervals on the surface of Si substrate 1, and on a region of Si substrate 1 between source region 21 and drain region 22 via an oxide film. The gate electrode 23 is formed.

As described above, the ferroelectric memory of this embodiment can be integrated on the Si substrate 1 together with other elements or circuits. FIG. 5 is a schematic sectional view of a ferroelectric memory according to another embodiment of the present invention.

In FIG. 5, (11) of the n-type Si substrate 31
1) The p ⁺ layers 32 and 33 are formed on the surface at predetermined intervals. n-type Si substrate 31 between p ⁺ layers 32 and 33
A ZnO buffer layer 34 is formed on the (111) plane of
On the ZnO buffer layer 34, a ferroelectric layer 35 made of LiTaO ₃ is formed. A source electrode 36 and a drain electrode 37 are formed on the p ⁺ layers 32 and 33, respectively, and a gate electrode 38 is formed on the ferroelectric layer 35.

Here, the operation of the ferroelectric memory of FIG. 5 will be described. When a negative gate voltage is applied to the gate electrode 38, the interface of the ferroelectric layer 35 with the gate electrode 38 is positively charged, and the interface with the ZnO buffer layer 34 is negatively charged.
Thereby, the Si substrate 31 between the p ⁺ layers 32 and 33
A channel is formed in the region of. Therefore, the source
When a voltage between drains is applied, a current flows between the source and the drain via the channel. Even after the voltage applied to the gate electrode 38 is set to 0, the polarization of the ferroelectric layer 35 continues. Therefore, when a voltage between the source and the drain is applied, a current flows between the source and the drain via the channel. That is, a nonvolatile memory operation is realized.

In the ferroelectric memory of the present embodiment, S
On the (111) plane of the i-substrate 31, Zn with the plane orientation (001)
O easily grows epitaxially, and the ZnO buffer layer 3
Since the ferroelectric layer 35 having three-fold or six-fold symmetry is easily epitaxially grown on the (001) plane of No. 4, the manufacturing process is facilitated.

Further, by terminating dangling bonds on the surface of the Si substrate 31 with Zn, the Si substrate 31 and the ZnO
A good interface can be formed with the buffer layer 34. Further, since ZnO has a high reducing property, generation of oxygen defects near the interface of the ferroelectric layer 35 is prevented, and a good interface between the ZnO buffer layer 34 and the ferroelectric layer 35 is formed. Becomes possible. Therefore, a favorable nonvolatile memory operation is realized.

In the above embodiment, the ferroelectric layers 5, 3
Although LiTaO ₃ is used as the material of No. 5,
LiNbO ₃ (lithium niobate), P instead of O ₃
Even if another ferroelectric such as ZT or BaTiO ₃ (barium titanate) is used, high characteristics can be obtained as a nonvolatile memory as in the above embodiment. Here, the PZT system is (PbTiO ₃ ) _x (PbZrO ₃ ) _{1 -X} ,
0 ≦ X ≦ 1.

In the above embodiment, the ion beam sputtering method is used to form each layer and electrode. However, the present invention is not limited to this. For each layer, the MBE method (molecular beam epitaxial growth method), the CVD method ( Other growth methods such as chemical vapor deposition may be used, and other formation methods such as vapor deposition may be used for each electrode.

Further, in the above embodiment, the ferroelectric memory having the p-type channel has been described. However, the ferroelectric memory having the n-type channel can be realized by reversing the conductivity type of each layer.

In the above embodiment, the ZnO layer 2 or the ZnO buffer layer 34 is formed directly on the Si substrate 1 or 31, but the ZnO layer 2 or the ZnO buffer layer 34 is formed on the Si substrate 1 or 31. May be formed on the formed Si layer.

Further, in the embodiment of FIG. 1, the FET structure is formed on the ZnO layer 2 on the Si substrate 1, but the FET structure may be formed on the ZnO substrate.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a ferroelectric memory according to one embodiment of the present invention.

FIG. 2 is a schematic view of an ECR ion beam sputtering apparatus used for manufacturing the ferroelectric memory of FIG.

FIG. 3 is a diagram showing a simulation result of element characteristics of the ferroelectric memory of FIG. 1;

FIG. 4 shows the ferroelectric memory of FIG.
FIG. 3 is a schematic cross-sectional view showing an example formed on a substrate.

FIG. 5 is a schematic sectional view of a ferroelectric memory according to another embodiment of the present invention.

FIG. 6 is a schematic sectional view showing an example of a conventional ferroelectric memory.

FIG. 7 is a schematic sectional view showing another example of a conventional ferroelectric memory.

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 n-type ZnO layer 3, 4, 32, 33 p ⁺ layer 5, 35 ferroelectric layer 6, 36 source electrode 7, 37 drain electrode 8, 38 gate electrode 31 n-type Si substrate 34 ZnO buffer layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/788 29/792

Claims (7)

[Claims] A first electrode formed on the semiconductor layer at a predetermined interval from an oxide on a region of the semiconductor layer between the first electrode and the second electrode; A ferroelectric memory, wherein a third electrode is formed on the ferroelectric layer, and the semiconductor layer has a higher reducing property than the ferroelectric layer. . 2. An oxide semiconductor layer is formed on a substrate, and first and second oxide semiconductor layers are formed on the oxide semiconductor layer at predetermined intervals.
Are formed, an oxide ferroelectric layer is formed on a region of the oxide semiconductor layer between the first electrode and the second electrode, and a second ferroelectric layer is formed on the oxide ferroelectric layer. 3. A ferroelectric memory, wherein three electrodes are formed, and the oxide semiconductor layer has a higher reducing property than the oxide ferroelectric layer. 3. A first electrode and a second electrode are formed on a semiconductor substrate at a predetermined interval, and the first electrode and the second electrode are formed.
An oxide semiconductor layer, an oxide ferroelectric layer, and a third electrode are sequentially formed on a region of the semiconductor substrate between the first electrode and the second electrode, and the oxide semiconductor layer is compared with the oxide ferroelectric layer. A ferroelectric memory having high reducibility. 4. The ferroelectric memory according to claim 2, wherein said substrate comprises a silicon substrate. 5. The method according to claim 1, wherein the substrate is a silicon substrate having a (111) plane, and the oxide semiconductor layer is made of zinc oxide formed on the (111) plane of the silicon substrate. Item 5. The ferroelectric memory according to item 2, 3 or 4. 6. The ferroelectric memory according to claim 1, wherein said semiconductor layer is made of zinc oxide. 7. The semiconductor device according to claim 1, wherein the semiconductor layer is made of a trigonal or hexagonal oxide semiconductor, and the ferroelectric layer is made of a trigonal or hexagonal ferroelectric.
7. The ferroelectric memory according to any one of items 1 to 6.