CN107240606A - A kind of ferro-electric field effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a ferroelectric field effect transistor, comprising: a substrate; a channel layer formed on the substrate; a source region and a drain region formed on the channel layer, the source region and the drain region are symmetrically formed at both ends of the channel layer; a buffer layer is formed on the channel layer and between the source region and the drain region; a ferroelectric gate dielectric layer formed on the ferroelectric gate dielectric layer; a gate electrode formed on the ferroelectric gate dielectric layer; a source electrode formed on the source region; and a drain electrode formed on the drain region. The present invention adopts β _{- Ga2O3} as the channel material, and the transistor has better anti-radiation performance. At the same time, the invention also provides a preparation method of the ferroelectric field effect transistor.

Description

A kind of ferroelectric field effect transistor and its preparation method

technical field

The invention relates to a transistor and a preparation method thereof, in particular to a ferroelectric field effect transistor and a preparation method thereof.

Background technique

In recent years, my country has developed rapidly in the field of aerospace, such as the successful launch and return of the "Shenzhou" series of spacecraft, the construction of the "Beidou" satellite navigation system, the implementation of the "Chang'e" lunar exploration project and the "Tiangong" space laboratory, etc. , put forward higher requirements on the long-term reliability of memory chips. However, because the anti-radiation hardening technology is a highly sensitive technology in aerospace technology, research institutions and large microelectronics companies in almost all aerospace countries in the world have invested a lot of manpower and material resources in this field to develop semiconductor materials, devices, Research on the radiation effect mechanism and reinforcement technology of integrated circuits and memories, in order to seize the strategic commanding heights, compete for the dominance of the sky, and obtain the greatest commercial benefits. The 33 Western countries headed by the United States, Japan and Europe have formulated the "Missile Technology Control Regime (MTCR)", which clearly stipulates that anti-radiation hardening and simulation test technologies are strictly controlled or embargoed on my country.

Ferroelectric memory is one of the important frontiers and research hotspots of today's high-tech information. Compared with the traditional semiconductor memory, ferroelectric memory not only has the characteristics of high-density information storage and fast erasing and writing, but also has significant advantages such as low voltage, low cost, low loss, small size, and radiation resistance. It has great industrial potential. Since the storage unit of the ferroelectric memory controls its "on" and "off" states according to the polarization of the ferroelectric material, it is impossible to cause its polarization due to radiation sources such as alpha particles, cosmic rays, heavy ions, gamma rays, and X-rays. It can be changed to change the given storage state of a unit, so it has extremely strong radiation resistance, and is especially suitable for space and aerospace technology applications. Existing research shows that the anti-ionizing radiation ability of ferroelectric memory reaches more than 105Gy, the anti-gamma instantaneous dose rate ability is greater than 109Gy/s, the anti-neutron radiation ability reaches 1015 cm-2, and there is no single event disturbance, while the traditional MOS field effect transistor γ Radiation damage tolerance is only about 102Gy.

Therefore, compared with traditional non-volatile memories such as Flash, ferroelectric memories using ferroelectric thin film materials as storage media have better radiation resistance. However, the ferroelectric memory contains an array of Si field effect transistors, and its overall radiation resistance is limited by the radiation resistance of the Si field effect transistors. In order to prolong the service life of ferroelectric memory in space radiation environment, it is necessary to strengthen the Si field effect transistor in ferroelectric memory against radiation. Compared with the first-generation semiconductor material Si, the second-generation and third-generation semiconductor materials are generally It has larger atomic displacement threshold energy and forbidden band width, so it has better radiation resistance and temperature stability. Therefore, in recent years, the integration of ferroelectric thin film materials with second-generation and third-generation semiconductor materials such as GaAs, SiC, GaN and diamond has attracted great attention from researchers in the ferroelectric field.

Contents of the invention

Based on this, the object of the present invention is to provide a ferroelectric field effect transistor with low power consumption and good anti-radiation performance to overcome the disadvantages of the above-mentioned prior art.

In order to achieve the above object, the technical solution adopted by the present invention is: a ferroelectric field effect transistor, comprising:

Substrate;

a channel layer formed on the substrate;

a source region and a drain region formed on the channel layer, the source region and the drain region being symmetrically formed at both ends of the channel layer;

a buffer layer formed on the channel layer and between the source region and the drain region;

A ferroelectric gate dielectric layer formed on the buffer layer;

a gate electrode formed on the ferroelectric grid dielectric layer;

a source electrode formed on the source region;

as well as

A drain electrode is formed on the drain region.

Preferably, the channel layer is composed of β-Ga ₂ O ₃ material.

The use of β _{- Ga2O3} as the channel material provides a guarantee for the improvement of the radiation resistance and temperature stability of FeFET. β-Ga2O3, as a wide bandgap semiconductor material with good thermal and chemical stability, is expected to have very good radiation resistance, larger bandgap width and higher Baliga quality factor than SiC and GaN ( BFOM) value and cheaper price, using β-Ga2O3 as channel material can improve the overall radiation resistance and temperature stability of ferroelectric thin film FeFET.

Preferably, the channel layer is further doped with tin, and the tin doping concentration is 10 ¹⁵ -10 ¹⁶ cm ^-3 .

Preferably, the thickness of the channel layer is 200nm-300nm.

Preferably, the source electrode includes a Ti source electrode and an Au source electrode, and the Au source electrode is formed on the Ti source electrode; the drain electrode includes a Ti drain electrode and an Au drain electrode, and the Au drain electrode forms on the Ti drain electrode.

Preferably, the substrate is made of silicon material or germanium material.

Preferably, the buffer layer is an insulating layer, or the buffer layer is a double-layer structure composed of an insulating layer and a metal layer.

Preferably, the material of the ferroelectric gate dielectric layer is at least one of Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , BiFeO ₃ , or La, Nd, Ce, Sr, A substance formed by doping at least one of Zr, Mn, W, and Na with at least one of Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , and BiFeO ₃ , or Zr doped At least one of HfO ₂ , Si-doped HfO ₂ , Al-doped HfO ₂ , and Y-doped HfO ₂ .

Preferably, when the buffer layer is a double-layer structure composed of an insulating layer and a metal, the thickness of the insulating layer is 2nm-10nm, and the thickness of the metal layer is 50nm-80nm.

Preferably, the thickness of the ferroelectric gate dielectric layer is 5nm-600nm.

Simultaneously, the present invention also provides a kind of preparation method of above-mentioned ferroelectric field effect transistor, comprises the following steps:

(1) forming a channel layer on the substrate;

(2) forming a source layer and a drain layer on the channel layer formed in step (1);

(3) Using an ion implantation process, ion implantation is performed on the source layer and the drain layer in step (2) to form a source region and a drain region;

(4) Activating the source region and the drain region obtained in step (3) to obtain the source and drain;

(5) Depositing a buffer layer on the channel layer processed in step (4);

(6) depositing a ferroelectric gate dielectric layer on the buffer layer in step (5);

(7) deposit gate metal on the ferroelectric gate dielectric layer in step (6), obtain gate electrode;

(8) removing the buffer layer, ferroelectric gate dielectric layer and gate electrode on the source region and the drain region after step (7);

(9) Forming a source electrode and a drain electrode on the source electrode and the drain electrode processed in step (8) to obtain the ferroelectric field effect transistor.

Preferably, in the step (1), a channel layer is epitaxially grown on the substrate by using a low-temperature solid-source molecular beam epitaxy process, the epitaxy temperature is 500° C. to 700° C., and the deposition rate is 0.6 μm/h.

Preferably, a 365nm I-line photolithography process is used in the steps (2) and (8). Those skilled in the art can select a suitable etching formula according to needs.

Preferably, in the step (2), the conditions of the ion implantation process are: the implantation energy is 20-25KeV in the N ⁺ type source region and the N ⁺ type drain region, and the dose is 10 ¹⁸ -10 ¹⁹ cm ^-3 Si ⁺ ions.

Preferably, the process of the activation treatment in the step (4) is: performing thermal annealing treatment on the source region and the drain region in the step (3) at 800°C to 950°C.

The process adopted in the step (6) is a suitable film deposition process recognized in the art, including magnetron sputtering, pulsed laser deposition, atomic layer deposition and other film deposition processes, but not limited thereto.

Preferably, the gate metal in the step (7) is at least one of TiN, TaN and Pt.

Preferably, the magnetron sputtering process is adopted in the step (10), the temperature of the magnetron sputtering process is 200°C to 300°C, and the thickness of Ti metal sputtered on the source and drain electrodes is 20nm to 30nm. The thickness of the sputtered Au metal on the source and drain electrodes is 100nm-150nm.

Compared with the prior art, the beneficial effects of the present invention are:

The present invention uses β-Ga ₂ O ₃ as the channel material, a wide bandgap semiconductor material with good thermal stability and chemical stability, and is expected to have very good radiation resistance performance, which can strengthen the radiation resistance of the channel part ability.

Description of drawings

Fig. 1 is a kind of sectional structural diagram of ferroelectric field effect transistor of the present invention;

Fig. 2 is a kind of flowchart of ferroelectric field effect transistor manufacturing method of the present invention;

Among them, 1. substrate; 2. channel layer; 3. source region; 4. buffer layer; 5. ferroelectric gate dielectric layer; 6. gate electrode; 7. drain region; 8. Ti drain electrode; 9 , Au drain electrode; 10, Ti source electrode; 11, Au source electrode.

detailed description

In order to better illustrate the purpose, technical solutions and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Example 1

An embodiment of the ferroelectric field effect transistor of the present invention, a cross-sectional structure diagram of the ferroelectric field effect transistor described in this embodiment is shown in Figure 1, including:

a substrate 1, the substrate 1 is composed of a silicon material;

A channel layer 2 formed on the substrate 1, the channel layer 2 is composed of β-Ga ₂ O ₃ material, the channel layer 2 is also doped with tin, and the doping concentration of the tin is 10 ¹⁵ cm ^-3 ;

The source region 3 and the drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 are symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

A ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

A gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

The source electrode formed on the source region 3, the source electrode includes a Ti source electrode 10 and an Au source electrode 11, and the Au source electrode 11 is formed on the Ti source electrode 10;

as well as

The drain electrode formed on the drain region 7 , the drain electrode includes a Ti drain electrode 8 and an Au drain electrode 9 , and the Au drain electrode 9 is formed on the Ti drain electrode 8 .

Wherein, the thickness of the channel layer is 200nm; the buffer layer is composed of an insulating layer, specifically a hafnium-based dielectric material, the hafnium-based dielectric material is HfO ₂ , and the thickness of the buffer layer is 8nm; the ferroelectric The material of the gate dielectric layer is Zr-doped HfO ₂ , and the thickness of the ferroelectric gate dielectric layer is 5 nm.

An embodiment of the method for preparing a ferroelectric field effect transistor described in this embodiment includes the following steps:

Step 1. Epitaxial growth of β-Ga ₂ O ₃ layer:

A β-Ga ₂ O ₃ layer was epitaxially grown on the substrate by low-temperature solid-source molecular beam epitaxy, with a thickness of 200 nm, an epitaxy temperature of 500 °C, and a deposition rate of 0.6 μm/h. Figure 2(a) is the substrate Schematic diagram of the bottom structure, Figure 2(b) is a schematic diagram of the structure after the epitaxial growth of β-Ga ₂ O ₃ channel;

Step 2, photolithography to form the active layer:

A source layer, a channel and a drain layer are formed on the β-Ga ₂ O ₃ layer by photolithography, wherein the channel is located in the center of the β-Ga ₂ O ₃ layer, and the source layer and the drain layer are respectively located in the channel. both sides of the road;

Step 3, doping to form source region and drain region:

Ion implantation is carried out on the source layer and the drain layer by using ion implantation process. The implantation conditions are: Si ⁺ ions are implanted in the N ⁺ type source region and the N ⁺ type drain region with an energy of 25KeV and a dose of 10 ¹⁹ cm ^-3 , forming a source region and a drain region;

Step 4. Activate:

Thermal annealing of the source region and the drain region at 950°C for 30 minutes was activated to obtain the source region and the drain region. Figure 2(c) is a schematic diagram of the result of the activation treatment to obtain the source region and the drain region;

Step 5, deposit buffer layer:

Using the atomic layer deposition process, at a temperature of 280°C and a pressure of 15hPa, an _HfO2 layer with a thickness of 8nm is deposited on the active layer formed in step 4 to form an insulating dielectric film, as shown in Figure 2(d). Schematic diagram of the result after depositing _HfO2 insulating dielectric film;

Step 6, depositing a ferroelectric gate dielectric layer:

Using the atomic layer deposition process, at the temperature of 300°C and the pressure of 20hPa, a ferroelectric Zr-doped _HfO2 film with a thickness of 5nm is deposited on the insulating dielectric film in step 5. Figure 2(e) shows the deposition Schematic diagram of the results after accumulating ferroelectric Zr-doped _HfO2 thin films;

Step 7, depositing the gate electrode:

Using the magnetron sputtering process, under the conditions of temperature 300 ℃, pressure 0.32Pa, and sputtering power 115W, 120nm TiN was grown on the ferroelectric Zr-doped HfO ₂ film. Figure 2(f) shows the deposition Schematic diagram of the result after the gate metal TiN;

Step 8, photolithography and etching:

The source and drain electrode windows are formed by photolithography, and the buffer layer/ferroelectric HfO ₂ /TiN on the source and drain are etched. Figure 2(g) shows the etching of the buffer layer HfO ₂ /ferroelectric on the source and drain Schematic diagram of the result after completion of HfO ₂ /TiN;

Step 9, depositing source and drain electrodes:

Using the magnetron sputtering process, under the conditions of temperature 260°C, pressure 0.12Pa, and sputtering power 200W, in the source-drain electrode window formed in step 8, deposit and form Au/Ti source-drain electrodes with thicknesses of The thickness is 20nm/100nm, and then the fabrication of the transistor is completed by peeling off. Fig. 2(h) is a schematic diagram of the result of the fabrication of the transistor.

Example 2

An embodiment of the ferroelectric field effect transistor of the present invention, a cross-sectional structure diagram of the ferroelectric field effect transistor described in this embodiment is shown in Figure 1, including:

A substrate 1, the substrate 1 is composed of a germanium material;

A channel layer 2 formed on the substrate 1, the channel layer 2 is composed of β-Ga ₂ O ₃ material, the channel layer 2 is also doped with tin, and the doping concentration of the tin is 10 ¹⁶ cm ^-3 ;

The source region 3 and the drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 are symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

A ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

A gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

The source electrode formed on the source region 3, the source electrode includes a Ti source electrode 10 and an Au source electrode 11, and the Au source electrode 11 is formed on the Ti source electrode 10;

as well as

The drain electrode formed on the drain region 7 , the drain electrode includes a Ti drain electrode 8 and an Au drain electrode 9 , and the Au drain electrode 9 is formed on the Ti drain electrode 8 .

Wherein, the thickness of the channel layer is 300nm; the buffer layer is composed of a double-layer structure composed of an insulating layer and a metal layer, the insulating layer is composed of a hafnium-based dielectric material, the metal layer is TiN, and the hafnium-based The dielectric material is Al ₂ O ₃ , the thickness of the insulating layer is 2nm, and the thickness of the metal TiN is 50nm; the material of the ferroelectric gate dielectric layer is SrBi ₂ Ta ₂ O ₉ , the thickness of the ferroelectric gate dielectric layer is 100nm.

An embodiment of the method for preparing a ferroelectric field effect transistor described in this embodiment includes the following steps:

Step 1. Epitaxial growth of β-Ga ₂ O ₃ layer:

Using low-temperature solid-source molecular beam epitaxy, a layer of β-Ga ₂ O ₃ was epitaxially grown on the substrate with a thickness of 300nm. The epitaxial temperature was 700°C and the deposition rate was 0.6μm/h. Figure 2(b) shows the epitaxial Schematic diagram of the result after growing a β-Ga ₂ O ₃ channel;

Step 2, photolithography to form the active layer:

A source layer, a channel and a drain layer are formed on the β-Ga ₂ O ₃ layer by photolithography, wherein the channel is located in the center of the β-Ga ₂ O ₃ layer, and the source layer and the drain layer are respectively located in the channel. both sides of the road;

Step 3, doping to form source region and drain region:

Ion implantation is carried out on the source layer and the drain layer by using ion implantation technology. The implantation conditions are: Si ⁺ ions are implanted in the N ⁺ type source region and the N ⁺ type drain region with an energy of 20KeV and a dose of 10 ¹⁸ cm ^-3 , forming a source region and a drain region;

Step 4. Activate:

Thermal annealing of the source region and the drain region at 800°C for 30 minutes was performed to activate the source region and the drain region. Figure 2(c) is a schematic diagram of the result of the activation treatment to obtain the source region and the drain region;

Step 5, deposit buffer layer:

Using the atomic layer deposition process, at a temperature of 260°C and a pressure of 12hPa, deposit an Al ₂ O ₃ layer with a thickness of 2nm on the active layer formed in step 4 to form an insulating layer film, and use magnetron sputtering Sputtering process, at a temperature of 300°C, a pressure of 0.32Pa, and a sputtering power of 115W, 50nm TiN was grown on the insulating layer film Al ₂ O ₃ , and Figure 2(d) shows the result after depositing a buffer layer schematic diagram;

Step 6, depositing a ferroelectric gate dielectric layer:

Using the atomic layer deposition process, at the temperature of 280°C and the pressure of 15hPa, a ferroelectric SrBi ₂ Ta ₂ O ₉ film with a thickness of 100nm is deposited on the insulating dielectric film in step 5, as shown in Figure 2(e). Schematic diagram of the result after deposition of ferroelectric SrBi ₂ Ta ₂ O ₉ film;

Step 7, depositing the gate electrode:

Using the magnetron sputtering process, under the conditions of temperature 300℃, pressure 0.32Pa, and sputtering power 115W, 120nm TiN was grown on the ferroelectric SrBi ₂ Ta ₂ O ₉ film. Figure 2(f) shows the deposition Schematic diagram of the result after accumulating gate metal TiN;

Step 8, photolithography and etching:

The source and drain electrode windows are formed by photolithography, and the buffer layer/SrBi ₂ Ta ₂ O ₉ /TiN on the source and drain is etched. Figure 2(g) shows the etching of the buffer layer on the source and drain Al ₂ O ₃ /SrBi ₂ Ta ₂ O ₉ /TiN finished result schematic diagram;

Step 9, depositing source and drain electrodes:

Using the magnetron sputtering process, under the conditions of temperature 200°C, pressure 0.12Pa, and sputtering power 200W, in the source-drain electrode window formed in step 8, Au/Ti source-drain electrodes are deposited to form Au/Ti source-drain electrodes with thicknesses respectively It is 25nm/125nm, and then the fabrication of the transistor is completed by stripping, and Fig. 2(h) is a schematic diagram of the result of the fabrication of the transistor.

Example 3

An embodiment of the ferroelectric field effect transistor of the present invention, a cross-sectional structure diagram of the ferroelectric field effect transistor described in this embodiment is shown in Figure 1, including:

a substrate 1, the substrate 1 is composed of a silicon material;

A channel layer 2 formed on the substrate 1, the channel layer 2 is composed of β-Ga ₂ O ₃ material, the channel layer 2 is also doped with tin, and the doping concentration of the tin is 10 ¹⁵ cm ^-3 ;

The source region 3 and the drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 are symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

A ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

A gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

The source electrode formed on the source region 3, the source electrode includes a Ti source electrode 10 and an Au source electrode 11, and the Au source electrode 11 is formed on the Ti source electrode 10;

as well as

The drain electrode formed on the drain region 7 , the drain electrode includes a Ti drain electrode 8 and an Au drain electrode 9 , and the Au drain electrode 9 is formed on the Ti drain electrode 8 .

Wherein, the thickness of the channel layer is 250nm; the buffer layer is composed of a double-layer structure composed of an insulating layer and a metal layer, the insulating layer is composed of a hafnium-based dielectric material, the metal layer is TiN, and the hafnium-based The dielectric material is HfAlO, the thickness of the insulating layer is 10nm, and the thickness of the metal TiN is 80nm; the material of the ferroelectric grid dielectric layer is Zr doped with PbTiO3 _The material formed, the thickness of the ferroelectric grid dielectric layer is 280nm.

An embodiment of the method for preparing a ferroelectric field effect transistor described in this embodiment includes the following steps:

Step 1. Epitaxial growth of β-Ga ₂ O ₃ layer:

Using low-temperature solid-source molecular beam epitaxy, a layer of β-Ga ₂ O ₃ was epitaxially grown on the substrate, with a thickness of 250 nm, an epitaxial temperature of 600 °C, and a deposition rate of 0.6 μm/h. Figure 2(b) shows the epitaxy Schematic diagram of the result after growing a β-Ga ₂ O ₃ channel;

Step 2, photolithography to form the active layer:

Form a source layer, a channel and a drain layer on the β-Ga2O3 layer by using a photolithography process, wherein the channel is located in the center of the β-Ga2O3 layer, and the source layer and drain layer are located on both sides of the channel;

Step 3, doping to form source region and drain region:

Ion implantation is carried out on the source layer and the drain layer by using ion implantation process. The implantation conditions are: Si ⁺ ions are implanted in the N ⁺ type source region and the N ⁺ type drain region with an energy of 25KeV and a dose of 10 ¹⁹ cm ^-3 , forming a source region and a drain region;

Step 4. Activate:

Thermal annealing of the source and drain regions at 880°C for 30 minutes was performed to activate the source and drain regions. Figure 2(c) is a schematic diagram of the results of the activation treatment to obtain the source and drain regions;

Step 5, deposit buffer layer:

Using the atomic layer deposition process, at a temperature of 260 ° C and a pressure of 12 hPa, a HfAlO layer with a thickness of 6 nm is deposited on the active layer formed in step 4 to form an insulating dielectric film. Figure 2(d) shows the deposited Schematic diagram of the result after accumulating HfAlO insulating dielectric film;

Step 6, depositing a ferroelectric gate dielectric layer:

Using the pulsed laser deposition process, the single pulse energy is 300mJ, the energy density of the laser pulse is 2J/cm ² , the laser repetition frequency is 10Hz, the deposition oxygen pressure is 100mTorr, and the deposition temperature is 700°C. In step 5, an insulating dielectric film is deposited on HfAlO A Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric film with a thickness of 280nm, Figure 2(e) is a schematic diagram of the result after depositing a Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric film;

Step 7, depositing the gate electrode:

80nm TaN was grown on the Pb(Zr _0.53 Ti _0.47 )O ₃ ferroelectric film by ultra-high vacuum electron beam technology, and Fig. 2(f) is a schematic diagram of the result after deposition of gate metal TaN;

Step 8, photolithography and etching:

The source and drain electrode windows are formed by photolithography, and the buffer layer HfAlO/ Pb(Zr _0.53 Ti _0.47 )O ₃ /TaN on the source and drain is etched. Figure 2(g) shows the etching of the buffer layer on the source and drain Schematic diagram of the result after the layer HfAlO/ Pb(Zr _0.53 Ti _0.47 )O ₃ /TaN is completed;

Step 9, depositing source and drain electrodes:

Using the magnetron sputtering process, under the conditions of temperature 300°C, pressure 0.12Pa, and sputtering power 200W, in the source-drain electrode window formed in step 8, deposit and form Au/Ti source-drain electrodes with thicknesses respectively The thickness is 30nm/150nm, and then the fabrication of the transistor is completed by peeling off. Fig. 2(h) is a schematic diagram of the result of the fabrication of the transistor.

Example 4

An embodiment of the ferroelectric field effect transistor of the present invention, a cross-sectional structure diagram of the ferroelectric field effect transistor described in this embodiment is shown in Figure 1, including:

A substrate 1, the substrate 1 is composed of a germanium material;

A channel layer 2 formed on the substrate 1, the channel layer 2 is composed of β-Ga ₂ O ₃ material, the channel layer 2 is also doped with tin, and the doping concentration of the tin is 10 ¹⁶ cm ^-3 ;

The source region 3 and the drain region 7 formed on the channel layer 2, the source region 3 and the drain region 7 are symmetrically formed at both ends of the channel layer 2;

a buffer layer 4 formed on the channel layer 2 and between the source region 3 and the drain region 7;

A ferroelectric gate dielectric layer 5 formed on the buffer layer 4;

A gate electrode 6 formed on the ferroelectric gate dielectric layer 5;

The source electrode formed on the source region 3, the source electrode includes a Ti source electrode 10 and an Au source electrode 11, and the Au source electrode 11 is formed on the Ti source electrode 10;

as well as

The drain electrode formed on the drain region 7 , the drain electrode includes a Ti drain electrode 8 and an Au drain electrode 9 , and the Au drain electrode 9 is formed on the Ti drain electrode 8 .

Wherein, the thickness of the channel layer is 250nm; the buffer layer is composed of hafnium-based dielectric material, the hafnium-based dielectric material is HfN, and the thickness of the buffer layer is 10nm; the material of the ferroelectric gate dielectric layer is Nd The substance formed by doping with Bi ₄ Ti ₃ O ₁₂ , the thickness of the ferroelectric grid dielectric layer is 600nm.

An embodiment of the method for preparing a ferroelectric field effect transistor described in this embodiment includes the following steps:

Step 1. Epitaxial growth of β-Ga ₂ O ₃ layer:

Using low-temperature solid-source molecular beam epitaxy, a layer of β-Ga ₂ O ₃ was epitaxially grown on the substrate with a thickness of 250 nm. The epitaxial temperature was 500°C and the deposition rate was 0.6 μm/h. Figure 2(b) shows the epitaxy Schematic diagram of the result after growing a β-Ga ₂ O ₃ channel;

Step 2, photolithography to form the active layer:

A source layer, a channel and a drain layer are formed on the β-Ga ₂ O ₃ layer by photolithography, wherein the channel is located in the center of the β-Ga ₂ O ₃ layer, and the source layer and the drain layer are respectively located in the channel. both sides of the road;

Step 3, doping to form source region and drain region:

Ion implantation is carried out on the source layer and the drain layer by using ion implantation process. The implantation conditions are: Si ⁺ ions are implanted in the N ⁺ type source region and the N ⁺ type drain region with an energy of 25KeV and a dose of 10 ¹⁹ cm ^-3 , forming a source region and a drain region;

Step 4. Activate:

Thermal annealing of the source region and the drain region at 950°C for 30 minutes was activated to obtain the source region and the drain region. Figure 2(c) is a schematic diagram of the result of the activation treatment to obtain the source region and the drain region;

Step 5, deposit buffer layer:

Using the atomic layer deposition process, at a temperature of 280°C and a pressure of 12hPa, a _HfO2 layer with a thickness of 10nm is deposited on the active layer formed in step 4 to form an insulating dielectric film, as shown in Figure 2(d). Schematic diagram of the result after depositing HfO buffer layer film _;

Step 6, depositing a ferroelectric gate dielectric layer:

Using the pulsed laser deposition process, the single pulse energy is 320mJ, the energy density of the laser pulse is 2.5J/cm ² , the laser repetition frequency is 12Hz, the deposition oxygen pressure is 200mTorr, and the deposition temperature is 750°C, and the insulating dielectric film HfO ₂ is formed in step 5 Deposit a Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ ferroelectric film with a thickness of 320nm, and Fig. 2(e) is a schematic diagram of the result after depositing a Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ ferroelectric film;

Step 7, depositing the gate electrode:

Using the ultra-high vacuum electron beam process, 80nm Pt is grown on the Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ ferroelectric film. Figure 2(f) is a schematic diagram of the result after depositing the gate metal Pt;

Step 8, photolithography and etching:

The source and drain electrode windows are formed by photolithography, and the buffer layer HfO ₂ /Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ /Pt on the source and drain is etched. Figure 2(g) shows the etching of the buffer layer on the source and drain Schematic diagram of the result after the layer HfO ₂ /Bi _3.15 Nd _0.85 Ti ₃ O ₁₂ /Pt is completed;

Step 9, depositing source and drain electrodes:

Using the magnetron sputtering process, under the conditions of temperature 260°C, pressure 0.12Pa, and sputtering power 200W, in the source-drain electrode window formed in step 8, Au/Ti source-drain electrodes are deposited and formed, and the thicknesses are respectively The thickness is 20nm/100nm, and then the fabrication of the transistor is completed by peeling off. Fig. 2(h) is a schematic diagram of the result of the fabrication of the transistor.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that, The technical solution of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solution of the present invention.

Claims (10)

1. A ferroelectric field effect transistor, characterized in that, comprising: Substrate; a channel layer formed on the substrate; a source region and a drain region formed on the channel layer, the source region and the drain region being symmetrically formed at both ends of the channel layer; a buffer layer formed on the channel layer and between the source region and the drain region; A ferroelectric gate dielectric layer formed on the buffer layer; a gate electrode formed on the ferroelectric grid dielectric layer; a source electrode formed on the source region; as well as A drain electrode is formed on the drain region. 2. The ferroelectric field effect transistor according to claim 1, wherein the channel layer is composed of β _{- Ga2O3} material. 3 . The ferroelectric field effect transistor according to claim 2 , wherein the channel layer is further doped with tin or silicon, and the doping concentration of the tin or silicon is 10 ¹⁵ -10 ¹⁶ cm ^-3 . 4. The ferroelectric field effect transistor according to claim 1, 2 or 3, characterized in that the thickness of the channel layer is 200nm-300nm. 5. The ferroelectric field effect transistor as claimed in claim 1, wherein the source electrode comprises a Ti source electrode and an Au source electrode, and the Au source electrode is formed on the Ti source electrode; the drain electrode comprises A Ti drain electrode and an Au drain electrode, the Au drain electrode being formed on the Ti drain electrode. 6. The ferroelectric field effect transistor according to claim 1, wherein the substrate is made of silicon or germanium. 7. The ferroelectric field effect transistor according to claim 1, wherein the buffer layer is an insulating layer, or the buffer layer is a double-layer structure composed of an insulating layer and a metal layer. 8. The ferroelectric field effect transistor according to claim 1, wherein the material of the ferroelectric gate dielectric layer is Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , BiFeO ₃ At least one of La, Nd, Ce, Sr, Zr, Mn, W, Na and at least one of Bi ₄ Ti ₃ O ₁₂ , SrBi ₂ Ta ₂ O ₉ , PbTiO ₃ , BaTiO ₃ , BiFeO ₃ At least one of the substances formed by doping, or at least one of Zr-doped HfO ₂ , Si-doped HfO ₂ , Al-doped HfO ₂ , and Y-doped HfO ₂ . 9. The ferroelectric field effect transistor according to claim 7, wherein when the buffer layer is a double-layer structure composed of an insulating layer and a metal layer, the thickness of the insulating layer is 2 nm to 10 nm, and the metal layer The thickness of the layer is 50 nm to 80 nm. 10. A method for preparing a ferroelectric field effect transistor as claimed in any one of claims 1 to 9, characterized in that it comprises the steps of: (1) forming a channel layer on the substrate; (2) forming a source layer and a drain layer on the channel layer formed in step (1); (3) Using an ion implantation process, ion implantation is performed on the source layer and the drain layer in step (2) to form a source region and a drain region; (4) Activating the source region and the drain region obtained in step (3) to obtain the source and drain; (5) Depositing a buffer layer on the channel layer processed in step (4); (6) depositing a ferroelectric gate dielectric layer on the buffer layer in step (5); (7) deposit gate metal on the ferroelectric gate dielectric layer in step (6), obtain gate electrode; (8) removing the buffer layer, ferroelectric gate dielectric layer and gate electrode on the source region and the drain region after step (7); (9) Forming a source electrode and a drain electrode on the source electrode and the drain electrode processed in step (8) to obtain the ferroelectric field effect transistor.