JPH1040216A - Method and device for controlling timing and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade a data collision in a data bus without giving effect on original access time by previously changing the timing of a control signal. SOLUTION: A control part 4 is connected to accessed parts (ROM2, RAM3 and a peripheral IO part 8) via a bus line 17. A timing control part 5 controls an access timing to the accessed parts by the control part 4 which is connected by the bus line. The timing control part 5 inputs the control signal (XIORD0 and XMRD0) for performing access to the peripheral device and generates the new control signals (XIORD1 and XMRD1) for completing the access to the accessed parts at the timing being earlier than the read access which is executed by the control signals based on the signals. Then, the new control signals are supplied to the accessed parts to substitute for read access.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a timing control method for controlling access timing between a central processing unit (CPU) and a peripheral device (memory, integrated circuit, I / O device, etc.) connected by a data bus. And an apparatus. Also,
The present invention relates to a central processing unit, a peripheral device, and an information processing device including the timing control device.

[0002]

2. Description of the Related Art In a conventional data processing terminal device, a central processing unit (CPU) executes access to peripheral devices in continuous bus cycles. In such a device, for example, there is a case where a CPU reads data from a peripheral device in one bus cycle and writes data to the peripheral device in a subsequent bus cycle. In such a case, the write data from the CPU is output onto the data bus after the data is output from the peripheral device onto the data bus by the data read access.

When such an access occurs, in a data processing terminal device using a low-speed or medium-speed CPU, read data and write data collide on the data bus in successive bus cycles. Unlikely. Therefore, it was possible to directly connect the control signal between the CPU and the peripheral device (memory or peripheral IO).

However, in a high-speed CPU, in a continuous bus cycle, there is a high possibility that the CPU outputs write data on the data bus while data is output from the peripheral device onto the data bus. Data collision on the bus is likely to occur. For this reason, the following avoidance measures are taken in a data processing terminal device equipped with a high-speed CPU.

[0005] (1) A buffer is inserted into a memory or a bus line connecting a peripheral IO with a long data hold time in a read cycle, and the data line is cut off so as not to affect the next bus cycle. (2) Limit the current by inserting a damping resistor in the data bus line. (3) The timing of outputting a control signal such as a read or write signal to be output in the next bus cycle is delayed.

[0006]

However, in the circumvention means (1) of the prior art, the cost is increased and the mounting efficiency is reduced by inserting a buffer. When the buffer is incorporated in an integrated circuit such as an ASIC, input and output terminals of the data bus line are required, and the number of pins is twice as large as the bus width, which is inefficient.

When a damping resistor is inserted as in the avoidance means (2), a delay occurs due to the capacitive load of the memory or the peripheral IO and the damping resistor. Further, the mounting efficiency also decreases. Further, when the output timing of a control signal such as a read or write signal in the next bus cycle is delayed as in the avoidance means (3), the access time is increased as a result, which adversely affects the high speed of the system. Exert.

The present invention has been made in view of the above problems, and avoids data collision on a data bus without affecting the original access time by changing the timing of a control signal ahead of schedule. And an information processing apparatus using the same.

[0009]

A timing control apparatus according to the present invention for achieving the above object has the following arrangement. That is, a timing control device for controlling access timing between an access unit and a accessed unit connected by a data bus, wherein the input unit inputs a control signal for accessing the accessed unit from the access unit; Generating means for generating a new control signal for terminating access to the accessed portion at a timing earlier than access by the control signal, based on the signal, and transmitting the new control signal generated by the generating means to the received signal. Supply means for supplying the data to the access unit; holding the data output from the accessed unit based on the new control signal; and holding the data held until the end of the access is detected by the control signal on the data bus. Output means for outputting to the

[0010] Preferably, the access timing to the accessed portion by the new control signal is a timing for terminating data output to the data bus by the accessed portion before completion of the access cycle. . For example, when a memory or the like is read-accessed,
It is possible to eliminate the influence on the next access cycle due to the data hold time and the like.

Preferably, the output means starts outputting the held data at the end of or before the access by the new control signal.

Preferably, for each of a plurality of accessed parts connected to the access unit via the data bus, a control signal of the access unit is used or the new control signal is used. A registration unit for registering control information indicating, based on the access destination address issued by the access unit, detects an accessed portion to be accessed based on the control information registered by the registration unit, Determining means for determining a control signal used for the access.

According to another aspect of the present invention, there is provided an information processing apparatus including the above-described timing control device, a CPU as an access unit, and a memory or a peripheral input / output device as an accessed unit.

A timing control method according to the present invention for achieving the above object is a method for controlling access timing between an access unit and a accessed unit connected by a data bus, wherein the access unit accesses the accessed unit. An input step of inputting a control signal for performing the processing, and a generation step of generating a new control signal for terminating access to the accessed part at a timing earlier than the access by the control signal, based on the control signal, A supply step of supplying a new control signal generated in the generation step to the accessed section, holding data output from the accessed section based on the new control signal, and performing the access by the control signal. And outputting the held data to the data bus until the end of the data bus is detected.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic configuration of a data processing terminal device according to the present embodiment. In the figure,
Reference numeral 1 denotes a display unit that displays the status of the device, time information, and the like under the control of the control unit 4. 2 is RO
M (read only memory), which stores programs for controlling the controller 4 and data for operator messages and the like.

Reference numeral 3 denotes a RAM (random access memory) which stores data and the like which can be set by an operator. A control unit 4 controls the entire apparatus.
Various control operations are executed in accordance with the control program stored in the ROM 2. 5 is a timing control unit,
It performs timing control with a memory or an integrated circuit of a peripheral IO that cannot directly use the access control signal from the control unit 4. Here, the memory or the peripheral IO in which the access control signal cannot be used directly has a response timing to the access of the CPU 1 as shown in FIG. 3, for example. FIG. 3 will be described later.

Reference numeral 6 denotes an operation unit for operating the data processing terminal device and inputting various information, and is composed of a plurality of key input switches, an operation circuit for the key input switches, and the like. Reference numeral 7 denotes the entire data processing terminal device.

FIG. 2 is a diagram for explaining a connection state of the control unit 4, the timing control unit 5, the memories (ROM2, RAM3) and the peripheral IO unit 8 (display unit 1 and the like) in the present embodiment. In FIG. 2, reference numeral 8 denotes a peripheral IO unit,
Is controlled by Examples of the peripheral IO unit 8 include the display unit 1 shown in FIG. 1 and a printer (not shown).

Reference numeral 9 denotes a read signal XMRD0, which is output from the control unit 4 when executing a read operation of the memory (ROM2, RAM3). 10 is a read signal XIORD0
This is output from the control unit 4 when a read operation to the peripheral IO 8 is performed. 11 is a chip select signal XCS
4, which is issued by the control unit 4 to specify a memory or a peripheral IO for executing a read operation or a write operation.

12 is a memory read signal XMRD,
When the read operation from the control unit 4 to the memory is executed,
In order to satisfy the read timing of the memory, it is issued by the timing control unit 5 based on the XMRD0 signal 9. 13 is an IO read signal XIORD,
When the read operation from the control unit 4 to the peripheral IO unit 8 is executed, the timing control unit 5 issues the read operation based on the XIORD0 signal 10 in order to satisfy the read timing to the peripheral IO unit 8.

Numeral 14 denotes a chip select signal XCS0, which indicates that the read operation from the control unit 4 to the ROM 2 has been executed and the address and XCS output from the control unit 4.
11, the timing control unit 5
Issued to the ROM 2. Reference numeral 15 denotes a chip select signal XCS1, which indicates that a read operation or a write operation has been performed on the RAM 3 from the control unit 4.
The timing control unit 5 issues the address to the RAM 3 when it is detected by the address output from the XCS 11 or the XCS 11. In the case of accessing the DRAM,
The RAS / CAS signal will be generated and issued.
Reference numeral 16 denotes a chip select signal XCS2, which is issued from the timing control unit 5 to the peripheral IO unit 8 when an access to the peripheral IO unit 8 is detected by the address output from the control unit 4 or the XCS11.

Reference numeral 17 denotes a bus line, which interfaces data and addresses between the control unit 4 and the timing control unit 5, the ROM 2, and the peripheral IO unit 8 of the RAM 3.

FIG. 3 is a timing chart showing an access in which the read data fetch timing by the CPU of the control unit 4 is defined by the rising edge of the CPU clock in the next cycle. The timing chart of FIG.
3 shows an operation timing example of a peripheral IO unit that cannot directly use the access control signal of FIG.

In FIG. 3, when the control unit 4 executes a read operation, an XCS (chip select) is issued at the rising edge of a first clock (T1 cycle clock), and XIORD0 (read signal) at the falling edge of the first clock. ) Is issued. Then, at the rising edge of the first clock in the next cycle, the control unit 4 takes in the read data output from the peripheral IO unit 8 and ends the read operation.

In this case, the chip select signal XC
S, the end timing of the read signal XIORD0 is defined by the rising clock from which the data is taken.
As described above, since the read signal XIORD0 is defined at the rise of the first clock in the next cycle, the read data is shifted to the next cycle by the delay of the read signal XIORD0 and the hold time of the subsequent read data. become. In this state, when the write operation is performed in the next cycle, the first read operation is performed.
XIOWR0 (write signal) is issued at the falling edge of the clock, and subsequently, write data is output on the bus line 17. In such a case, if the hold time of the read data is long, a state occurs in which the read data and the write data are simultaneously output onto the data bus as shown in FIG. That is, data collision occurs at the start of output of write data.

FIG. 4 is a diagram for explaining a state in which a control signal is supplied via the timing control unit 5 to the control unit and the peripheral IO operating at the timing shown in FIG. According to the timing chart of FIG. 4, data collision in a write data cycle following read data is avoided by a control signal issued from the timing control unit.

In response to a chip select signal (XCS), a read signal (XIORD0), an address signal, and the like output from the control unit 4, the peripheral IO is controlled by the timing control circuit 5.
A read signal (XIORD) to be output to the section 8 is created and issued to the peripheral IO section 8. Here, the timing control unit 5 sends the issued read signal (XIORD) to the control unit 4.
To be completed earlier than the read cycle. This read signal X
At the end of the IORD, the timing control unit 5 captures and holds the read data output from the peripheral IO unit 8, and outputs the captured data to the bus line 17.

The control unit 4 takes in the read data output from the timing control unit 5. The end of the read data output from the timing control unit 5 is determined by the read signal XIO output from the control unit 4.
This is performed simultaneously with the termination of RD0. As described above, collision between read data and data (write data) in the next cycle can be avoided.

FIG. 5 shows a timing control unit 5 according to this embodiment.
It is a block diagram showing the structure of. In FIG.
Denotes a data holding unit, which holds read data on the bus line 17 at the timing of termination of the read signal XIORD1 or XMRD1, and outputs the held data to the bus line 17. Also, the data holding unit 501
By the termination of XIORD0 or XMRD0,
The output of the held data is terminated. Reference numeral 502 denotes a chip selector, which controls each device (ROM) based on an address signal output from the control unit 4 and a chip select signal XCS.
2, a RAM 3, a peripheral IO unit 8, etc.).
CS0, XCS1, XCS2).

The chip selector 502 instructs the selectors 503 and 504 whether to use the control signal from the control unit 4 or a signal obtained by processing the control signal. Further, the chip selector 502 permits the data holding unit 501 to execute data holding when the processed control signal is used. Chip selector 502
In advance, whether to use a control signal of the control unit 4 or use a signal obtained by processing the control signal is registered in the registration unit 502a in advance corresponding to each memory and peripheral IO provided at each address.

Reference numeral 505 denotes a read signal generator, which is an XIO
A read signal XIORD1 is generated based on RD0 and the CPU clock CLK. The read signal XIORD1 generated here is a signal having the timing as described in FIG. A read signal generation unit 506 generates a read signal XMRD1 for performing a read process that does not affect the next cycle, based on XMRD0 and the CPU clock CLK. The timing of XMRD1 is basically the same as that of XIORD1.

Reference numeral 503 denotes a selector which outputs either XIORD0 or XIORD1 as XIORD based on a select signal from the chip selector 502.
Similarly, the selector 504 outputs either XMRD0 or XMRD1 as XMRD based on the select signal from the chip selector 502.

FIG. 6 is a flowchart showing the operation of the timing control section of the present embodiment. Step S101
In the read operation, the access target ROM2, R
The control unit 4 determines whether the AM 3 or the peripheral IO unit 8 can directly perform a read operation. Here, an access target that can perform a direct read operation refers to an access target whose read data output does not affect the next bus cycle. In this example, the determination is made based on the content registered in the registration unit 502a of the chip selector 502.

Here, if the access target can directly perform the read operation, the process proceeds to step S102, where the control unit 4 directly accesses and ends the read operation. That is, the chip selector 502 issues a select signal to the selectors 503 and 504 to select XIORD0 and XMRD0, respectively.

On the other hand, if it is determined in step S101 that the read operation cannot be performed directly, the process proceeds to step S103.
In step S103, the timing control unit 5 creates an execution read signal at a timing such that the read data does not affect the next bus cycle, based on the read signal and the address signal output from the control unit 4, Output to the access target. That is, the chip selector 502
For selectors 503 and 504, XIORD1
And a select signal to select XMRD1.

In step S104, when the read signal output from the timing controller 5 is terminated, the access target (memory or peripheral I / O) accessed by the controller 4 is terminated.
The read data output by O) is taken into the timing control unit 5. Further, in Step S105, Step S
The data fetched at 104 is output together with the end of the execution read signal output by the timing controller 5.

In step S106, it is determined whether or not the read signal output from the control unit 4 has been terminated. If not, the termination of the read signal is continuously monitored. If the read signal output from the control unit 4 is terminated, the process proceeds to step S107, and the read data output from the timing control unit 5 is terminated. The operations of steps S104 to S107 described above are executed by the chip selector 502 and the data holding unit 501.

The present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but can be applied to a single device (for example, a copier, a facsimile). Device).

[0040]

As described above, according to the present invention,
Even if the read signal of the CPU is delayed and a read access is made to an integrated circuit having a long data hold time, collision with the next cycle data can be avoided, and destruction and malfunction of the circuit can be prevented.

[0041]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a data processing terminal device according to an embodiment.

FIG. 2 is a diagram illustrating a connection state between a control unit, a timing control unit, a memory, and a peripheral IO unit according to the embodiment.

FIG. 3 is a timing chart showing an access defined by the CPU of the control unit 4 at the timing of fetching read data at the rising edge of the CPU clock in the next cycle.

FIG. 4 is a diagram illustrating a state in which a control signal is supplied via a timing control unit 5 to a control unit and peripheral IOs that operate at the timing shown in FIG.

FIG. 5 is a block diagram illustrating a configuration of a timing control unit 5 of the embodiment.

FIG. 6 is a flowchart illustrating an operation of the timing control unit according to the embodiment.

[Explanation of symbols]

 1 display unit 2 ROM 3 RAM 4 control unit 5 timing control unit 6 operation unit 7 data processing terminal 8 peripheral IO unit 9 XMRD0 10 XIORD0 11 XCS 12 XMRD1 13 XIORD1 14 XCS0 15 XCS1 16 XC2 17 bus line

Claims (9)

[Claims] 1. A timing control device for controlling access timing between an access unit and a accessed unit connected by a data bus, comprising: input means for inputting a control signal for accessing the accessed unit from the access unit. Generating means for generating a new control signal for terminating access to the accessed portion at a timing earlier than access by the control signal based on the control signal; and a new control signal generated by the generating means. Supply means for supplying the accessed section with the data, holding the data output from the accessed section based on the new control signal, and holding the data held until the end of the access is detected by the control signal. An output unit for outputting the data to a data bus. 2. The access timing to the accessed part by the new control signal is a timing to terminate data output to the data bus by the accessed part before completion of the access cycle. The timing control device according to claim 1, wherein 3. The timing control device according to claim 1, wherein the output unit starts outputting the held data at the end of the access by the new control signal or before that. . 4. A control indicating whether to use a control signal of the access unit or to use the new control signal for each of a plurality of accessed units connected to the access unit via the data bus. Registering means for registering information; detecting an access target to be accessed based on an access destination address issued by the access unit; and performing access based on the control information registered by the registering means. The timing control device according to claim 1, further comprising: a determination unit that determines a control signal to be used. 5. A method for controlling an access timing between an access unit and a accessed unit connected by a data bus, comprising: an input step of inputting a control signal for accessing the accessed unit from the access unit; Generating a new control signal for terminating the access to the accessed portion at a timing earlier than the access by the control signal based on the signal; and transmitting the new control signal generated in the generating step to the received control signal. Supplying the data to the access unit; holding the data output from the accessed unit based on the new control signal; and holding the data held until the end of the access is detected by the control signal on the data bus. And outputting to the timing control method. 6. An access timing to the accessed portion by the new control signal is a timing for terminating a data output on the data bus by the accessed portion before completion of the access cycle. The timing control method according to claim 5, wherein 7. The timing control method according to claim 5, wherein in the output step, the output of the held data is started at the end of the access by the new control signal or before that. . 8. A control indicating, for each of a plurality of accessed units connected to the access unit via the data bus, whether to use a control signal of the access unit or to use the new control signal. A registration step of registering information; detecting an accessed part to be accessed based on the access destination address issued by the access unit; and performing the access based on the control information registered in the registration step. The timing control method according to claim 5, further comprising: determining a control signal to be used. 9. A timing control device according to claim 1, comprising: a CPU as the access unit; and a memory or a peripheral input / output device as the accessed unit. Information processing device.