JPH11353223A - Flash memory controller and access method of flash memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute a program and data processes by simple control procedures and to greatly improve software development efficiency by providing a memory control means which gains access to a flash memory according to data and addresses from a processor. SOLUTION: To the flash memory 203, an address bus, a data bus, and a control signal are connected through ASIC 202, which performs its own control over the flash memory 203. Namely, a data selector 107 selects either of data generated by a data generation block 300 or data on a CPU data bus 101. Then an access request from the CPU 201 to the flash memory 203 is recognized and while a specific command is generated to have transition to a program cycle, a memory control means executes specific memory access according to data and addresses from the CPU 201.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash memory control device for controlling access to a flash memory by a processor and a method of accessing the flash memory control device.

[0002]

2. Description of the Related Art Heretofore, memory access control in this type of flash memory access device has been performed mainly by software.

[0003]

However, in the above-mentioned conventional example, since control is performed by software, there has been a problem that the load of software processing increases and the speed is inferior.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to recognize a request for access to a flash memory from a processor, generate a predetermined command, and transition to a program cycle. By executing predetermined memory access based on data and addresses from the processor, the processor can access the flash memory as if it were a general-purpose memory device such as a ROM or a RAM, and execute the memory via the flash memory. An object of the present invention is to provide a flash memory control device and an access method of the flash memory control device, which can execute a program and data processing to be executed by a simple control procedure, and can significantly improve software development efficiency.

[0005]

A first invention according to the present invention is a flash memory control device for controlling access to a flash memory by a processor, and a recognizing means for recognizing an operation request for the flash memory by the processor. Command generation means for generating a command for causing the flash memory to transition to a predetermined memory cycle based on the operation request recognized by the recognition means; and a notification for detecting an operation state of the flash memory and notifying the processor. Means and memory control means for executing memory access to the flash memory based on data and addresses from the processor.

A second invention according to the present invention has a first FIFO memory for holding data from the processor, and a second FIFO memory for holding an address from the processor, The memory control means,
A memory access to the flash memory is executed based on data and addresses prefetched into the first and second FIFO memories.

A third invention according to the present invention is an access method of a flash memory control device for controlling access to a flash memory by a processor, wherein the operation request of the processor for the flash memory is recognized, and the recognized request is recognized. A command for causing the flash memory to transition to a predetermined memory cycle based on an operation request is generated, and after the command is generated, a memory access to the flash memory is performed based on data and addresses from the processor.

A fourth invention according to the present invention is to detect an operation state of the flash memory and notify the processor of the operation state.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment of the present invention.

Referring to FIG. 1, reference numeral 101 denotes a data bus (CPU
data bus) and a microprocessor (CP
U). Reference numeral 102 denotes a FIFO memory which stores data to be written to a flash memory. 103, 1
Registers 04 and 105 latch data D1, data D2, and data D3 used when a write command is issued to the flash memory.

Reference numeral 106 denotes a CPU data buffer (data).
buffer), the data output from the FIFO memory 102 is temporarily stored. 107 is a data selector.
One data is selected from the data bus 101 and the registers 103 to 106. 108 is a flash memory (flat
sh memory) and a data bus (fla)
sh memory data buffer).

Reference numeral 111 denotes a (CPU) address bus (add)
connection with the microprocessor. An address FIFO memory 112 stores addresses to be written to the flash memory. Reference numeral 113 denotes a register for the flash memory.
Address A used when issuing a write command
Latch D1. A register 114 latches an address AD2 used when a write command is issued to the flash memory. A register 115 latches an address AD3 used when a write command is issued to the flash memory.

Reference numeral 116 denotes a CPU address buffer (add)
The address output from the FIFO memory 112 is temporarily stored in a “resuffer buffer”. Reference numeral 117 denotes an address selector which includes a CPU address bus 111, a register 11
3 to 115, one address is selected from the CPU address buffer 116. 118 is an address bus (addr)
(ESS BUS), and is connected to the flash memory.

Reference numeral 120 denotes a write (CPU WR) signal.
The write signal 120 from the microprocessor is input to the signal generation circuit 122. Reference numeral 121 denotes a flash memory chip select (flash memory CS) signal. The flash memory chip select signal 121 is input from the microprocessor to the signal generation circuit 122. Note that the signal creation circuit 122 creates an internal control signal.

Reference numeral 123 denotes a write signal, which is output from the signal generation circuit 122 and generated to recognize the fact that the CPU has written to the flash memory and to enable a FIFO dedicated to write data to capture data. Is done. Reference numeral 124 denotes a FIFO FULL status (FIFO FULL) signal, which notifies the timing controller 130 of empty information of the FIFO memory.

Reference numeral 125 denotes a FIFO status (status)
s) FIFO which can be read from CPU by register
Status memory status information
Inform as 126 is a CPU write request (C
A PU write request signal is output from the signal creation circuit 122 to the timing controller 130. Note that the timing controller 130
Determine the operation sequence of the flash memory controller. Further, the timing controller 130 receives a clock (CLK) 131 and a read signal (CP) from the CPU.
URD) 132, weight for CPU (CPU
wait *) signal 133 is input.

Reference numeral 134 denotes an RDY / BUSY * signal output from the flash memory. When this signal is "1", it indicates that the flash memory can be read or a new command can be accepted. Conversely, RDY / BUSY *
When the signal 134 is “0”, it indicates that the flash memory is performing a program cycle or an erase operation.

Reference numeral 135 denotes a selector control (SELELE).
ctor Control) signal and the data selector 1
07, the selector of the address selector 117 is controlled. 136 is a read (read) signal, FIFO
The data is output from the timing controller 130 when data is extracted from the memories 102 and 112.

Reference numeral 140 denotes a timing generation circuit (timing generator) which generates a control signal for an actual flash memory. Reference numeral 141 denotes a plurality of drive signals which are output from the timing controller 130. 1
Reference numeral 42 denotes a read (flash) output to the flash memory.
h memory RD) signal. Reference numeral 143 denotes a write (flash memo) output to the flash memory.
ry WR) signal. 144 is a chip select (flash memory) output to the flash memory.
CS) signal. Hereinafter, the actual operation will be described.

After the power is turned on, the CPU first operates the data registers 103 to 105 and the address registers 113 to 1.
Set 15 For example, in the case of a flash memory manufactured by AMD, "AAH",
"55H" is stored in the data register 104, "A0H" is stored in the data register 105, and the address register 1
13 is “5555h”, the address register 114 is “2AAAh”, and the address register 115 is “555”.
5H "will be set.

Next, the contents of the flash memory are erased by software control. Thus, the preparation before writing is completed.

On the other hand, when performing a write operation,
U performs a normal write operation on this controller. At this time, the signal creation circuit 122 outputs the write signal 120
Then, a write operation to the flash memory is detected from the signal state of the chip select signal 121 and the FIFO memories 102 and 112 are enabled in accordance with the write timing to fetch addresses and data.

The fetched data is stored in a CPU.
The data is sent to the data buffer 106 and latched. The fetched address is sent to the CPU address buffer 116 and latched.

The signal creation circuit 122 is a start signal CP for starting a write operation to the flash memory.
A U write request signal 126 is output to the timing controller 130.

In response to this start signal, the timing controller 130 that has started operation controls the data selector 107 to select the data D1 of the data register 103, and the timing controller 13 that has started operation.
0 controls the address selector 117 to select the address AD1 of the address register 113.

At the same time, the timing generator 1
Activate the selected address and data at the timing required for the flash memory to be used.
The control signals 142 to 144 are output, and the first write cycle is performed. After this cycle ends, the timing controller 130 performs the next write cycle.

Next, the timing controller 130
By controlling the data selector 107, the data register 104
The timing controller 130 that has started the operation while selecting the data D2 of the
To select the address AD2 of the address register 114.

At the same time, the timing generator 1
40, and outputs control signals 142 to 144 for the selected address AD22 and data D2 at a timing necessary for the flash memory to be used.
The second write cycle is performed.

After this cycle, the timing controller 130 performs the next write cycle.

Next, the timing controller 130
By controlling the data selector 107 and the data register 105
The timing controller 130 that has started the operation while selecting the data D3 of the
To select the address AD3 of the address register 115.

At the same time, the timing generator 1
40 and activates the selected address AD3 and data D
3, the control signals 142 to 144 are output at the timing required for the flash memory to be used.
Perform the second write cycle. This means that the flash memory has completed the command setting for entering the program cycle.

Next, the program is actually started.

First, the timing controller 130
By controlling the selector 107, the data line selects the CPU data buffer 106 and the address selector 1
17 to select the CPU address buffer 116.

At the same time, the timing generator 1
Activate the selected address and data at the timing required for the flash memory to be used.
The control signals 142 to 144 are output, and the fourth write cycle is performed.

Since the end of the actual program is determined by the fact that the RDY / BUSY * signal 134 output from the flash memory has become "1", this signal becomes "0".
During this period, the timing controller 130 is in the wait state.

At this time, when there is a read request from the CPU to the flash memory, the timing controller 130 outputs a CPU wait * signal 133 to the CPU and causes the CPU to wait.

Since the flash memory controller of this embodiment has the data and address FIFOs of the FIFO memory 102 and the FIFO memory 112, even if the previous program operation is not completed, as long as there is free space in the FIFO memory, the CPU Can write the next value to the FIFO memory.

From the FIFO memory status 125 to FI
When data remains in the FO memory 102, a read signal 136 is output, the next program data and its address are taken out, transferred to the buffers of the CPU data buffer 106 and the CPU address buffer 116, and after the transfer, Will be repeated.

FIG. 2 is a block diagram for explaining the correspondence between a custom IC (hereinafter referred to as an ASIC) incorporating the flash memory controller shown in FIG. 1 and its peripheral circuits.

In the figure, 201 is a CPU, 202 is A
A flash memory controller is built in the SIC. 203 is a flash memory. The flash memory 203 is connected to an address bus, a data bus, and control signals via an ASIC 202, and the ASIC 202 is configured to perform its own control on the flash memory.

FIG. 3 is a block diagram for explaining the detailed configuration of the ASIC 202 shown in FIG. 2, and the same components as those in FIG. 1 are denoted by the same reference numerals.

In the figure, reference numeral 300 denotes a data creation block (data generator) for creating data for the flash memory 203, and one of the created data and data on the CPU data bus 101 is selected by the data selector 107.

Reference numeral 310 denotes an addressless creation unit (data) for creating an address for the flash memory 203.
generator), the created address and CPU
One of the addresses on the address bus 111 is selected by the address selector 117. 320 is a CPU (C
PU control) and a bus controller 32
Sent for one. Reference numeral 322 denotes a control signal for the flash memory 203, which is sent from the bus controller 321.

[Second Embodiment] FIG. 4 is a block diagram for explaining a main configuration of a memory control device according to a second embodiment of the present invention. In FIG. I have.

In the figure, reference numeral 400 denotes a data set in which data D1 for issuing a write command of the registers 103 to 105 shown in FIG. 1 is set. Reference numeral 401 denotes a data set which is added data D for issuing an erase command.
2 is set. Reference numeral 402 denotes a data set for temporarily stopping erasing, in which data D3 for temporarily stopping erasing is set.
Reference numeral 403 denotes a data set for starting erasing, in which data D4 for starting erasing is set.

An address set 410 is used to set an address AD1 for issuing a write command of the registers 113 to 115 shown in FIG. An address set 411 for issuing an erase command is set with an added address AD2 for issuing an erase command.

450 is an erase sector address (era)
(sector address), which is the address of the sector to be erased in the address set 411. A comparison circuit (comparator) 451 compares the erase sector address 450 with the CPU address bus 111. 452 is an erase sector hit (erases
(Elector hit) signal, which is output when the comparison result of the comparator 451 matches.

Note that a CPU read (CPU RD) signal 420 is additionally input to the
A circuit for outputting a CPU read request signal 421 when the CPU reads a flash memory is added. In addition, an erase request signal (erase request) 430 is added to the timing controller 130. Hereinafter, an operation sequence of the flash memory controller will be described with reference to FIG.

FIG. 5 is a diagram for explaining the operation of the timing controller 130 shown in FIG. In addition, 501-
509 indicates each state.

The state 501 includes a reset (rese
t) state, and starts from this state after the power is turned on. State 502 is an initialization (initia)
(Lize) state. First, the data set 400
In addition to setting data in .about.402, an address is set in address sets 410 to 411, and an actual value is written from the CPU.

After the completion of the initialization, the state shifts to the normal state (normal) of the state 503. here,
The flash memory controller itself is not operating at all.

Here, when a read operation is performed from the CPU to the flash memory, the state shifts to a read state of state 505. Since all signal lines of the flash memory are output via the flash memory controller, the following signal processing is performed in this state.

First, in the first stage, the data selector 107
Disables the output, and although not shown in the figure, data of the flash memory is directly output to the CPU data bus 101. In the second stage, address selector 1
17 selects the CPU address bus 111 and outputs it to the flash memory.

Next, in the third stage, the signal creation circuit 122
Recognizing the read cycle to the flash memory,
A U read request 421 is output. In the next, fourth step, the timing controller 130 receives the CPU read request signal 421 and outputs a start signal 141 for generating an actual read signal. And the fifth
In the stage, the timing generator 140
41, the control signals 142 to 144 are generated in accordance with the read cycle of the flash memory using the clock 131 as a basic pulse. In this manner, the state 503 returns to the normal state after all the operations in the first to fifth steps are completed.

When a write operation is performed from the CPU to the flash memory, the state shifts to a write state 504. In this case, the following operation is performed.

First, in the first stage, the data selector 107
Sequentially selects and outputs the data sets 400. Second
At this stage, the address selector 117 sets the address set 4
10 are sequentially selected and output. Then, in the third stage, the signal creation circuit 122 recognizes a write cycle to the flash memory and outputs a write request 126.

Next, in a fourth stage, upon receiving the request signal 126, the timing controller 130 switches the selector control signal 135 to perform a program operation, and performs a plurality of start signals for generating an actual write signal. 141 is output. Then, in the fifth stage, the timing generation circuit 140 receives the start signal 141 and uses the clock 131 as a basic pulse to generate the control signal 14 corresponding to the write cycle of the flash memory.
Create 2-144. This operation is repeated as many times as necessary to perform the program operation. After all of the above-described operations in the first to fifth stages are completed, the state returns to the normal state 503.

When an erase operation is performed from the CPU to the flash memory, the state shifts to an erase state of state 506. In this case, the following operations from the first stage to the fifth stage are performed.

First, in the first stage, the data selector 107
Sequentially selects and outputs the data sets 400. Second
At this stage, the address selector 117 sets the address set 4
10 are sequentially selected and output. In the third stage, the timing controller 130 sends the erase request signal 430
In response to this, while switching the selector control signal 136 to perform the erase operation, the activation signal 141 for generating the actual write signal is output a plurality of times.

Then, in the fourth stage, the timing generator 140 receives the start signal 141 and receives the clock 131
Are used as basic pulses to generate control signals 142 to 144 in accordance with the write cycle of the flash memory. This operation is repeated as many times as necessary to perform the erase operation. After all the above operations in the first to fourth stages have been completed in this way, the actual erase operation starts, and when the erase operation ends, the state returns to the normal state 503.

When the read request 421 is received during the erase operation and the address at that time is the sector currently being erased, the comparison circuit 451 outputs the erase sector hit signal 452. At this time, the timing controller 130 sends the wait signal 1 to the CPU.
When the erase operation is completed, the process proceeds to the read state of the state 505 and the read operation is executed.

If the read request signal 421 is input during the erase operation and the address at that time is not the sector currently being erased, the comparison circuit 451 does not output the erase sector hit signal 452. At this time, the timing controller 130 enters a suspend state of the state 507. in this case,
The following first-stage and second-stage operations are performed.

First, in the first stage, the data selector 107
Selects the data set 402 and outputs it. In the second stage, the timing controller 130 receives the CPU read request signal 421, and switches the selector control signal 135 to stop the erase operation, while activating the activation signal 141 for generating the actual write signal.
Is output and a suspend command is issued.

Here, the timing controller 130
Indicates the stop of the erase operation by the RDY / BUSY * signal 13
4 is monitored, the erase operation is stopped, and the process enters the read state 508. The operation in this state is exactly the same as the read state of state 505.

After the end of the read state of the state 508, the timing controller 130 sets the state 5
Enter the restart state 09. In this case, the following first and second stage operations are performed.

First, in the first stage, the data selector 107
Selects the data set 403 and outputs it. In the second stage, the timing controller 130 outputs a start signal 141 for generating an actual write signal while switching the selector control signal 135, issues a restart command, and returns to the erase state of the state 506. .

Hereinafter, a characteristic configuration of the present embodiment will be described with reference to FIG.

The processor (CP) configured as described above
U201) for controlling access to the flash memory 203, comprising: a recognition unit (signal creation circuit 122) for recognizing an operation request for the flash memory by the processor; and an operation request recognized by the recognition unit. Command generation means (registers 103 to 103) for generating a command for causing the flash memory to transition to a predetermined memory cycle based on
105, registers 113 to 115, selectors 107, 1
17), notifying means (timing controller 130) for detecting the operating state of the flash memory and notifying the processor, and memory controlling means for executing memory access to the flash memory based on data and addresses from the processor (Timing controller 130, timing generator 140), the flash memory access request by the processor can be recognized and high-speed access can be performed, and the access processing load on the processor can be greatly reduced.

A first FIFO memory (FIFO 102) for holding data from the processor.
And a second FIFO memory (FIFO 112) for holding an address from the processor, wherein the memory control means is configured to read the first and second FIFO memories based on data and addresses. Since the memory access to the flash memory is executed, the access request from the processor to the flash memory can be sequentially processed while accumulating without depending on the operation state of the flash memory. And the intended memory access can be reliably performed while significantly improving the data processing efficiency of the processor.

Further, there is provided an access method of a flash memory control device for controlling access to a flash memory by a processor, wherein the processor (CPU 2
01), a command for transitioning the flash memory to a predetermined memory cycle based on the recognized operation request is generated, and after the command is generated, data from the processor is generated. Since the memory access to the flash memory is performed based on the address, the flash memory access request by the processor can be recognized and the access can be performed at a high speed, and the access processing load on the processor can be greatly reduced.

Further, since the operating state of the flash memory is detected and notified to the processor, the processor can accurately recognize the operating state of the flash memory in the flash memory controller.

In the present embodiment, the flash memory (MBM29F400 series) manufactured by AMD is described as an example. Therefore, the ASIC 202 stores predetermined addresses and data in the data sets 103 to 105 and the address sets 113 to 115. Example of a command generated in a data write sequence, for example: data "555H" /
Address “AAH”, data “2AAH” / address “55Hh”, data “555H” / address “A0
H ") and a chip erase command (example of command generated during chip erase sequence: data" 555H ")
/ Address "AAH", data "2AAH" / address "55Hh", data "555H" / address "80
H, data "555H" / address "AAH", data "2AAH" / address "55Hh", data "55
5H "/ address" 10H "or the like is automatically generated, and a predetermined command for the flash memory 203 can be automatically generated. The command sequence is executed by six bus operations, while the write sequence is executed by four bus operations.

According to each of the above embodiments, when the microprocessor performs a write operation on the flash memory, the means of the flash memory controller for recognizing the operation of the microprocessor on the flash memory performs the write operation. The flash memory is detected and determined to perform a write operation to the flash memory, and then the flash memory controller transmits a command necessary for performing the write operation to a command generation unit for controlling the flash memory.

On the other hand, means for informing the microprocessor of the status of the flash memory of the flash memory controller to the microprocessor that a command is being transmitted and a write operation is being performed provides the microprocessor with information. The processor performs an operation optimized for the flash memory.

As a result, the flash memory controller has a function of automatically recognizing the operation of the CPU and issuing a command specific to the flash memory.
The same access to the flash memory as that of a normal RAM or ROM can be performed. Therefore, creation of software is also greatly simplified.

Further, since the program operation and the erase operation are immediately determined from the RDY / BSY * signal of the flash memory and are performed by hardware, the speed is higher than the conventional control performed by software. To be peeled off.

Further, since the flash memory controller issues commands automatically by hardware, there is no load on the CPU and the throughput of the entire system can be improved.

[0078]

As described above, the first embodiment according to the present invention is described.
According to the invention, there is provided a flash memory control device for controlling access to a flash memory by a processor, comprising: recognition means for recognizing an operation request for the flash memory by the processor; and an operation request based on the operation request recognized by the recognition means. Command generation means for generating a command for causing the flash memory to transition to a predetermined memory cycle, a notifying means for detecting an operation state of the flash memory and notifying the processor of the operation state,
A memory control unit for executing a memory access to the flash memory based on the data and address from the processor; therefore, the flash memory access request by the processor can be recognized and the access can be performed at a high speed, and the access processing load on the processor is greatly reduced. Can be reduced.

According to the second invention, the first FIFO memory for holding data from the processor and the second FIFO memory for holding an address from the processor.
An IFO memory, and the memory control means executes a memory access to the flash memory based on data and addresses prefetched into the first and second FIFO memories. Requests can be sequentially processed while accumulating irrespective of the operation state of the flash memory, eliminating the burden of synchronizing the memory access request of the processor and the access state to the flash memory, and significantly improving the data processing efficiency of the processor. Memory access can be performed reliably.

According to a third aspect of the present invention, there is provided an access method of a flash memory control device for controlling access to a flash memory by a processor, wherein the operation request to the flash memory by the processor is recognized, and the recognized operation request is recognized. Generating a command to cause the flash memory to transition to a predetermined memory cycle based on the command. After the command is generated, a memory access to the flash memory is performed based on data and an address from the processor. The access request can be recognized at a high speed by recognizing the access request, and the access processing load on the processor can be greatly reduced.

According to the fourth aspect, since the operating state of the flash memory is detected and notified to the processor, the processor can accurately recognize the operating state of the flash memory in the flash memory controller.

Therefore, the processor can access the flash memory as if it were a general-purpose memory device such as a ROM or a RAM, and can execute programs and data processing to be executed through the flash memory with simple control procedures. This has the effect of significantly improving the software development efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating the correspondence between a custom IC incorporating the flash memory controller shown in FIG. 1 and its peripheral circuits.

FIG. 3 is a block diagram illustrating a detailed configuration of an ASIC illustrated in FIG. 2;

FIG. 4 is a block diagram illustrating a main configuration of a memory control device according to a second embodiment of the present invention.

FIG. 5 is a diagram illustrating the operation of the timing controller shown in FIG.

[Explanation of symbols]

 Reference Signs List 101 data bus 102 FIFO memory 106 CPU data buffer 107 data selector 108 data bus 111 address bus 112 FIFO memory 116 CPU address buffer 117 address selector 118 address bus 122 signal generation circuit 130 timing controller 140 timing generator

Claims (4)

[Claims] 1. A flash memory control device for controlling access to a flash memory by a processor, comprising: recognition means for recognizing an operation request for the flash memory by the processor; and, based on the operation request recognized by the recognition means. Command generation means for generating a command for causing the flash memory to transition to a predetermined memory cycle; notification means for detecting an operation state of the flash memory and notifying the processor; data based on data and addresses from the processor; A flash memory control device, comprising: memory control means for executing a memory access to a flash memory. A first FIFO memory for holding data from the processor; and a second FIFO memory for holding an address from the processor. 2. The flash memory control device according to claim 1, wherein a memory access to the flash memory is executed based on data and an address pre-read into the second FIFO memory. 3. An access method of a flash memory control device for controlling an access to a flash memory by a processor, wherein the flash memory controller recognizes an operation request of the processor for the flash memory, and based on the recognized operation request, Generating a command that causes a transition to a predetermined memory cycle, and after generating the command, executing a memory access to the flash memory based on data and an address from the processor. . 4. The access method according to claim 3, wherein an operation state of the flash memory is detected and notified to the processor.