JPH0877061A - Information processor - Google Patents

Abstract

PURPOSE: To shorten an access time and enable fast access when access is caused as expected by detecting an address advanced output cycle and outputting an estimated address to a high-speed access target in advance. CONSTITUTION: A CPU state deciding means 102 specifies storage devices 108 and 109 to be accessed fast for which an address is determined in advance if possible from a CPU address and a state signal, and sends an indication for latching the address to an address storage means 104. An estimated address output means 105 generates an address that a CPU 101 should access next as an estimated address on the basis of the CPU address latched by the address storage means 104. When the CPU 101 outputs an actual CPU address, a coincidence deciding means 103 compares the CPU address with the estimated address and reads and writes data out of and to the storage device 108 (109) in fast timing when the comparison result shows a coincidence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus composed of a CPU and a storage device, and more particularly to a memory control system for reducing the access time of the CPU to the storage device and improving the processing speed.

[0002]

2. Description of the Related Art In order to improve the processing speed of an information processing apparatus including a CPU and a storage device, one method is to increase the operating frequency of the CPU. However, as the operation of the CPU becomes faster, the access time to the storage device read and written by the CPU has become the majority of the processing time. As a method of speeding up the storage device access, for example, R, which has a relatively slow access time compared to the operation of the CPU
Japanese Patent Laid-Open No. 3-294945 discloses a method for speeding up access to an OM (read-only storage device). In the related art, a means for latching the data output from the ROM is provided, and after the data latch, the current address is incremented by 1 before the access is completed and the address is output to the storage device. Next, when the address actually output by the CPU matches the count-up address, the memory access time can be secured from the output start timing of the count-up address, and the access time can be shortened.

[0003]

The conventional technique has the advantage that the ROM of which access time is slow can be accessed at high speed.

However, a ROM and a storage device other than the ROM,
For example, in a storage device configuration including a DRAM (readable / writable storage device), since no consideration is given to the case where the ROM and the DRAM are randomly accessed, the DR
ROM access after AM access cannot be speeded up.

In addition, the storage device configuration is changed to R with different data widths.
In the case of the OM, the added value for adding to the current address to generate the expected address must be changed according to the data width. However, since the data width is not taken into consideration, the storage device cannot be composed of ROMs having different data widths.

Further, it is necessary to provide a means for latching the data output from the ROM, which causes a problem such as an increase in the number of parts. Further, there is a problem that the access time increases because a delay time occurs when the ROM data passes through the latch.

An object of the present invention is to realize a high-speed access system for a storage device which can be applied to an information processing device in which at least one storage device is mixed and which does not require a data latching device.

[0008]

In order to solve the above-mentioned problems, the present invention outputs a state signal including a CPU address indicating an access data address and a signal for distinguishing access start timing and read / write access. A CPU (Central Processing Unit) and a storage unit for storing data are provided, and an address storage unit for latching a CPU address, an expected address output unit for generating an address to be accessed next by the CPU, and an output to the storage unit. Switching means for switching the address to either the CPU address or the expected address, a coincidence judging means for comparing the expected address with the CPU address and outputting the result, CP
A CPU state determination means for generating a control signal from the state signal output by U and the CPU address is provided.

[0009]

The CPU state means (1) specifies a memory device to be accessed at high speed, which determines the address in advance from the CPU address and the state signal if possible, and (2) accesses which can end the address at least in the middle of the access cycle. Is specified, and (3) the start timing of the access cycle is determined. (1) If the access is to the storage device targeted for high-speed access, the address storage device is instructed to latch the address. Further, (2) in the case of an access in which the output of the address can be completed in the middle of the access period, the switching means is switched to A when the output of the address is completed.
Further, (3) at the start timing of the access cycle, the coincidence determination means is instructed to make a determination.

The address storage means latches the CPU address when receiving the latch instruction from the CPU state determination means.

The expected address output means generates an address to be accessed next by the CPU as an expected address in consideration of the data width of the storage device to be accessed, based on the CPU address latched by the address storage means. .

Upon receiving the judgment instruction from the CPU state judging means, the coincidence judging means compares the predicted address output from the predicted address output means with the CPU address and notifies the command generating means of the result.

The command generation means determines the length of the access cycle based on the state state of the CPU and the result of the address comparison by the coincidence determination means, and the memory command signal and the I / O command signal are accordingly sent to the memory / I. Output to / O. Further, the access cycle control signal controls the access cycle time of the CPU.

The switching means determines the timing of switching the input signals A and B and outputting the address in accordance with the switching instruction of the CPU state determination signal.

[0015]

EXAMPLE An example of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing the constituent means of the information processing apparatus of this embodiment. In FIG. 1, reference numeral 101 denotes a CPU that executes control of the entire information processing apparatus according to a program stored in the memories A and B. 102 is the CPU 1
The state signal indicating the start timing of the access cycle of 01 and the type of access to be executed, and the CPU address indicating the access target of the CPU 101 are input (1)
Address latch instruction of the address storage means 104, (2)
Matching determination instruction from the matching determination means 103, (3) switching means 1
The CPU state determination means outputs a switching instruction of 06. Reference numeral 103 denotes a CPU address and expected address output means 10 according to the output result of the CPU state determination means.
5 is a coincidence determining means for comparing the expected addresses output by the reference numeral 5. Reference numeral 104 is an address storage unit that stores a CPU address according to a determination instruction from the CPU state determination unit. 105 is a CP stored in the address storage means 104
It is a predicted address output means for predicting / specifying the next access address according to the U address. 106 is a CPU
According to the instruction of the state determination means, the memories A and B and I /
It is a switching means for switching the address output to O or the like. Reference numeral 107 denotes a command generation unit that determines a required access cycle period according to the determination result of the coincidence determination unit 103, controls the access period of the CPU 101, and outputs a command signal according to the access period to the memory / I / O. is there.

The operation of this embodiment will be described below with reference to FIGS. In this embodiment, the access to the memory A 108 of the memories A and B and the I / O to be accessed by the CPU is speeded up by the preceding output of the address. FIG. 3 shows the CPU state determination means 102.
4 is a flowchart showing the processing procedure of the address storage means 104, FIG. 5 is a flowchart showing the processing procedure of the expected address output means 105, and FIG. 6 is a flowchart showing the processing procedure of the match determination means 103. FIG. 7 is a flowchart showing the processing procedure of the command generating means 107.

In the CPU state judging means 102, as shown in FIG.
The process is executed according to the procedure. In process 3001, CPU1
01 state signal is monitored and access cycle (CP
U cycle) start is detected. At the beginning of the access cycle, the address select signal is designated as B in process 3002. As a result, the switching means 106 selects and outputs the CPU address. Further, it issues a match determination instruction to the match determining means 103. In the match determination processing 103, a determination is made based on the CPU address and the expected address. If the address of the address storage means 104 is updated during the determination, the correct determination cannot be made. In order to prevent this, a process 3004 of waiting for a specified time until the end of the matching determination process is performed. After the match determination process is completed, the state information is acquired in process 3005, and the memory A10 is acquired in processes 3006 and 3007.
In the case of access to 8, the address latch instruction is issued to the address storage means. Next, processing 3008 to 3010
The cycle in which the address output can be completed at the point when the current access cycle is earlier than the end of the access cycle (hereinafter,
In the case of "address preceding output enable cycle"),
After waiting in step 3009 until the address output is completed, in step 3010 the address select signal notified to the switching means 106 is switched to the expected address. As a result, the predicted address of the next access cycle can be output from the middle of the access cycle. Examples of the address preceding output enable cycle include an access cycle in which an address holding period is shorter than an access cycle such as a DRAM access cycle, and a cycle in which no address output is particularly required such as an idle cycle.

The address storage means 104 executes the processing shown in FIG. In process 401, CPU state determination means 1
02 detects the notification of the CPU address latch instruction output in process 3007, and latches (stores) the CPU address in process 402. By the above processing, if the CPU state determination unit 102 can output an address in the middle of the previous access cycle, the memory to be output in advance (hereinafter,
In the case of access to a "high-speed access target"), an address latch instruction is issued and the address of the previous high-speed access target can be latched and held in the address storage means 104.

The expected address output means 105 executes the processing shown in FIG. In process 501, the address storage unit 1
The access address for the previous high-speed access target held by 04 is acquired. Next, in process 502, an expected address is generated. As a method of generating the expected address, it is assumed that byte access is continuous, a method in which one is added to the address of the address storage means is used as the expected address, and that word access is continuous, It is possible to apply a method such as adding two to the address as the predicted address, but the method of generating the predicted address is not particularly limited.
Next, it is determined whether the predicted address generated in processing 503 and 504 is within the area of the memory A that is the high-speed access target, and if it is outside the area, the predicted address is corrected so that it is included in the area in processing 504. .

The match determining means 103 executes the processing shown in FIG. In processing 601, the CPU state determination means 102
Detects the match determination instruction notified in process 3003. If there is a match determination instruction, the CPU address and the expected address are compared in process 602, and if the addresses match, the process 603 sets the match determination result signal to the shortening instruction. If the addresses do not match, the match determination result signal is set to the normal instruction in step 604.

The command generating means 107 executes the processing shown in FIG. In process 701, the state information of the CPU 101 is acquired, the type of access cycle is specified, and the timing of the access cycle is synchronized. Then process 702
Then, the match determination means 103 detects the state of the match determination signal notified in the processing 603 or 604, and the expected address is C
If it matches the PU address and the access cycle can be shortened, the processes 703 and 704 are executed. Also, in the case of normal processing in which the addresses do not match, processing 703 and 704
To execute. In the processes 703 and 704, since the address is output prior to the memory A 108 which is the high-speed access target, the access time from the beginning of the access cycle can be shortened, and the command can be issued at the early access timing (cycle 3 in FIG. 2). Output a signal. further,
For the CPU 101, access cycle timing control (WAIT control) is performed in accordance with the early access timing by the access period control signal. Processing 705
In 706, since the preceding addresses are not output to the memories A and B and I / O, the normal access time is required from the beginning of the access cycle, and the normal access timing (see FIG.
The command signal is output in cycle 1 and 2). Further, the CPU 101 executes the access cycle timing control (WAIT control) matched with the normal access timing by the access period control signal.

By performing the above processing, the address preceding output enable cycle is detected, and in the case of the address preceding output enable cycle, the expected address for the high speed access target is output in advance, and the access to the high speed access target is performed as expected. If the error occurs, the access time can be shortened.

An operation example of the above-described embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing the timing of the access cycle of the information processing apparatus of this embodiment. In FIG. 2, cycles 1 and 3 are access cycles for the high-speed access target, and cycle 2 is an address preceding output enable cycle. CPU in cycle 1
The state determination means 102 issues an address latch instruction to the address storage means, and the address storage means 104 stores the CPU address N. The predicted address output means 105 generates and outputs the predicted address N + 1. In cycle 1, it is assumed that the determination result of the coincidence determination means 103 does not match.

The next cycle 2 is an address preceding output enable cycle. The CPU state determination means 101 detects that the address preceding output is possible, and the switching means 106 uses the address M required for the cycle 2 access.
The output is switched from B to A at the output completion timing. As a result, the predicted address of the next access cycle can be output in advance during the cycle 2 period after the completion of the output period of the address M required for the cycle 2 (period R in FIG. 2). In cycle 3, the match determination means 103 compares the CPU address N + 1 with the expected address N + 1 according to an instruction from the CPU state determination means 102, and determines that they match. As a result, an instruction to shorten the access period is output to the command generation unit 107, a command signal is output from the command generation unit 107 at an early access timing (period S in FIG. 2), and the access timing of the CPU is controlled.

As a result, in cycle 3, the access period can be shortened as compared with the normal access to the high-speed access target, and high-speed access can be performed.

In the present embodiment, the CPU state judging means 102, the coincidence judging means 103, the address storing means 10
4, expected address output means 105, command generation means 1
Part or all of the means 07 can be implemented by hardware or an executable software program such as a CPU, and the implementation method is not particularly limited.

Further, processing 502 of the expected address output means
As an expected address generation method in the above, paying attention to the data width of the high-speed access target (memory), when the data width is 8 bits, the expected address = memory address + 1, and when the data width is 16 bits, the expected address = memory address + 2. A method of determining the expected address according to the data width is also possible. Further, when the high-speed access target is composed of a plurality of types of memories, it is possible to change the method of generating the expected address in accordance with the type of the high-speed access target memory in the previous period.

Regarding the method of generating the expected address, there is at least one method of generating the expected address regardless of the type of the high-speed access target memory, and the generation method can be rebelled according to the user setting or the system status judgment. It is also possible to have a configuration.

Further, the address storage means 104 for holding the latch address which is the original data for generating the expected address.
In addition to the configuration that unconditionally latches the address information of the high-speed access target, for example, only the read access, the write access, the code fetch operation only, the address is latched, and the address is latched only when a specific condition occurs. A latch configuration is also possible, and the address and latch conditions are not particularly limited.

Further, the high-speed access target may be a device other than the memory, such as an I / O device, or a combination of the memory and the device other than the memory.

[0031]

According to the present invention, the CPU access period to the memory of the high speed access target can be shortened, and the high speed access can be realized.

Furthermore, in an information processing apparatus which requires high-speed access but expensive memory, the access period is shortened, and thus the same high-speed access can be performed by using a low-speed and inexpensive memory, and the cost of the information processing apparatus can be reduced. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment.

FIG. 2 is an explanatory diagram showing shortening of access time by output of an expected address in the first embodiment.

FIG. 3 is an operation flowchart of CPU state determination means 102.

FIG. 4 is an operation flowchart of address storage means 104.

5 is an operation flowchart of expected address output means 105. FIG.

FIG. 6 is an operation flowchart of the match determination means 103.

FIG. 7 is an operation flowchart of command generation means 107.

[Explanation of symbols]

101 ... CPU (Central Processing Unit), 102 ... CPU
State determining means, 103 ... Matching determining means, 104 ... Address storage means, 105 ... Expected address output means, 10
6 ... Switching means, 107 ... Command generating means, 108, 1
09 ... Storage device.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhisa Nishimoto 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Stock Company Hitachi Image Information Systems (72) Inventor Tsukasa Yamauchi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa (72) Inventor Masahito Fukushima, 1-1 1-1 Higashitaga-cho, Hitachi-shi, Ibaraki Ltd. Information & Media Division, Hitachi, Ltd.

Claims (5)

[Claims] 1. An information processing apparatus comprising a CPU (Central Processing Unit) and at least one storage means such as a memory for storing information, comprising: an address storage means for holding a CPU address output from the CPU; and a CPU address. An expected address output means for generating an expected address from the CPU, a match determination means for comparing the CPU address with the expected address, a switching means for switching the address output to the storage device to either the CPU address or the expected address, and the storage device. A command generation means for generating a command necessary for access of the CPU and a signal for controlling an access period, and a CPU state determination means for controlling each of the above means by receiving a state signal indicating an access start and an access type of the CPU, When the CPU accesses the storage device, the memory address is When the output period is shorter than the access period, when the expected address is output to the storage device as the memory address before the CPU address is instructed after the end of the memory address output period, and the actual CPU address is output by the CPU. An information processing apparatus comprising means for reading and writing data in the storage device at an early timing when the CPU address and the expected address are compared and the compared results match. 2. The information processing apparatus according to claim 1, wherein at least one of the storage devices is a DRAM, and access for which the memory address output period is shorter than the access period is DR.
An information processing apparatus comprising a CPU state determination means for AM access. 3. The information processing apparatus according to claim 1, wherein the CPU state determination is such that the access in which the memory address output period is shorter than the access period is either the internal processing cycle of the CPU or the idle cycle without an execution instruction, or both. An information processing apparatus comprising means. 4. The information processing apparatus according to claim 1, 2 or 3, further comprising: expected address output means for changing a method of generating the expected address according to a data width of a device to be accessed by the expected address. Information processing device. 5. An information processing apparatus according to claim 4, further comprising: a CPU state determining means for determining at least one of a determination condition, such as a device type or an access type such as read / write, as an address condition stored in the expected address storage means. An information storage device provided.