JP2000132452A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor which can shorten the loading time of a memory. SOLUTION: When a CPU 1 issues a format load request to a ROM C3 (state A), the ROM C3 starts accessing a ROM 2 at the formal load request (state B) and when 4th data is passed to the CPU 1 (state E), the ROM C3 predicts the formal load request of the CPU 1 and start a speculative load request (state F). When the CPU 1 issues the formal load request (state G), it is judged whether or not speculatively loaded data comply with the formal load request and when so, the data requested formally to be loaded are passed without any delay of access to the ROM 2 (state H).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus in which a control unit issues a request for loading an instruction or data in a memory.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional data processing device is a control unit which issues a load request for instructions and data, a CPU 11 serving as a master, and a ROM 12 serving as a memory for storing instructions and data. And a ROM controller (ROM) that is a memory control unit and a slave that controls a bus connected to the CPU 11 and to the ROM 12.
C) 13 and three are connected by a common bus.

[0003] Such a data processing device is a CPU 1
1 issues a load request to the ROMC13,
3 controls the CPU 1 to load instructions and data stored in the ROM 12 and stores the loaded instructions and data in the CPU 1.
I was loading one.

[0004]

However, in the conventional data processing device, the processing capacity of the CPU 11 has been increased,
There is a problem in that the lead time delay of the ROM 12 directly affects the processing performance of the entire data processing device.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a control unit for issuing an instruction or data load request, a memory for storing the instructions or data, and A memory control unit connected to a control unit and controlling a bus connected to the memory, wherein the memory control unit predicts a command or a data load request of the control unit, This is a data processing device that performs loading prior to a command or a data loading request from the control unit.

With this configuration, before the memory controller issues a load request before the controller issues a load request, the memory controller loads the memory controller in order to predict and load the issued load request. When a load request is made, the delay in the memory lead time can be reduced, and the load processing time can be reduced.

In the present invention, the load request of the control unit is defined as a normal load request, the memory control unit predicts the normal load request, and the load request to be performed before issuing the normal load request is speculative load request. Is defined.

Further, the present invention provides a data processing device in which the control unit and the memory control unit are connected in one chip.

With this configuration, the bus does not collide between the control unit, the memory control unit, and the memory. Therefore, the memory control unit speculatively loads the instruction and data from the memory while continuously loading the instruction and data from the memory. Completed data can be returned.

Further, the present invention comprises a cache which can be accessed at a higher speed than the memory, stores a part of the instructions and data stored in the memory also in the cache, The data processing device is configured to first make a load request to the cache and connect a signal line of the load request to the cache to the memory control unit.

With such a configuration, a normal load request that may be requested from the memory control unit can be grasped in advance, so that a more precise speculative load request can be made.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a data processing apparatus according to the present invention, which includes a CPU 1 which is a control unit and a master which issues a request for loading instructions and data, a ROM 2 which is a memory for storing instructions and data, A ROM controller (ROM) that is a memory control unit and a slave that controls a bus connected to the CPU 1 and to the memory 2
C) 3.

According to the present invention, the ROMC 3 has a request for loading instructions and data of the CPU 1 (hereinafter abbreviated as a normal load request).
And a load request (hereinafter abbreviated as a speculative load request) is made from the ROM 2 prior to the normal load request.

FIG. 2 is a diagram showing the operation of the present invention, and the time axis is from the top to the bottom of FIG. First, 4w from CPU1
ROMC3 for normal load request of ord Line data
(State A), the ROMC3 starts accessing the ROM2 in response to a normal data load request as usual (State B), and after a lapse of t1 (State C), 4w
The loading of the first data of the ord is completed, and this data is transferred to the CPU 1 (state D). Hereinafter, the same is repeated up to the fourth data.

When the fourth data is passed to the CPU 1 (state E), the ROMC 3 starts a speculative load request (state F). The speculative load predicts a regular load request of the CPU 1 and loads 4-word Line data. In this embodiment, a state in which the speculative load for 4 words (time of t1 + t2 + t3 + t4) is completed before the next regular load request from the CPU 1 is shown.
A regular load request may be issued during speculative loading.

When a normal load request is issued from the CPU 1 at a certain point in time after completion of the speculative load (state G), it is determined whether or not the normal load request matches the speculatively loaded data. If they match, RO
Since MC3 holds 4 words worth of data,
The data requested to be loaded normally is transferred without delay to access to the ROM 2 (state H). If they do not match, that is, if the speculative loading has failed, the ROMC 3 starts accessing the ROM 2 in response to the normal load request as usual (state I), and loads 4-word data.

In this embodiment, when the speculative loading succeeds, that is, when the regular load request and the data that has been speculatively loaded match, the time can be reduced by the time T. Even when the normal load request does not match the speculatively loaded data, a general memory such as ROM, SRAM, or SynchronousS
Since the RAM and the like can start a new access without receiving the previous state, a normal load can be started if there is a normal load request before the speculative load is completed. No delay occurs.

In the case of an instruction, the speculative load may be performed continuously after the completion of the loading of the regular load request by the CPU 1 based on the local continuity of the program. In the case of the data, a large number of regularly arranged data may be arranged. When accessing the data in succession, the data may be accessed in an arbitrary pattern following the normal load request. For example, as shown in FIG. 2 described above, if it is known before the access that data is accessed every 4 words due to the data structure, the condition for accessing the ROMC 3 every 4 words is set as the attribute of the speculative load request. I just need.

For example, in the execution of a 4 word speculative load, a normal load request is issued from the CPU 1 to the RO in a state where the 2 word data speculative load has already been completed.
If issued to the MC3 and the speculative loading has been successful, the CPU1, ROMC3, RO as shown in FIG.
In a configuration in which M2 shares the same data bus, once ROM
2, the speculative load must be stopped, and the speculated data must be returned to the CPU 1. However, in the configuration shown in FIG. 1, since the CPU 1 and the ROMC 3 are connected by a bus in one chip, it is necessary to return speculative data to the CPU 1 while continuously loading data speculatively from the ROM 2. Can be. In the configuration shown in FIG. 4, two types of data buses from the ROMC3 are required to return speculative data to the CPU 1 while continuously speculatively loading data from the ROM2 as described above. Thus, the number of bins increases and the cost increases. On the other hand, the configuration shown in FIG. 1 can be realized without increasing the number of bins.

FIG. 3 shows a configuration in which a cache 4 such as an SRAM that can be accessed at a higher speed than the ROM 2 is added to the configuration of FIG.
1 and a part of the instructions and data stored in the ROM 2 are also stored in the cache 4 so that the CPU 1 makes a load request to the cache 4 before the ROM 2, and a signal for a load request to the cache 4 FIG. 3 is a diagram showing a data processing device in which lines are connected to a ROMC3. With such a configuration, when loading instructions and data stored in the cache 4, the read time can be reduced as compared with loading from the ROM 2. Note that the instructions and data stored in the cache 4 may be the latest ones that are loaded or the ones that are frequently loaded.

Next, the operation of FIG. 3 will be described. CP
Normal load request from U1 (for example, address signal)
Is first output to the cache 4 (state A). If there is no requested data in the cache 4, the CP
U1 outputs a normal load request to the bus (state B). After arbitration, the normal load request reaches ROMC3 (state C), and ROMC3 starts loading data from ROM2 based on the normal load request (state D).
Return data to PU1. In this embodiment, since the signal line for the normal load request to the cache 4 is connected to the ROMC3 (state E), the ROMC3 is faster than the CPU1 than the normal load request from the CPU1 to the ROMC3 via the bus.
, The ROMC 3 can make a speculative load request using this information, and if no instruction or data is stored in the cache 4, the ROMC 3 always makes a normal load request via the bus. Since the data is issued to the ROMC3, more accurate and more reliable speculative loading can be performed, and the loading time can be reliably reduced. When there is an instruction or data in the cache 4, the speculative load may be continued while correcting the speculative load request each time.

[0022]

As described above, according to the data processing apparatus of the present invention, the memory control unit predicts the instruction and the data load request of the control unit and precedes the instruction and the data load request of the control unit. Therefore, it is possible to provide a data processing device capable of shortening the load time from the memory.

Further, since the signal line for requesting a load to the cache is connected to the memory control unit, more accurate and more reliable speculative loading can be performed, and data processing that can surely reduce the load time can be performed. An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a data processing device of the present invention.

FIG. 2 is a diagram showing a loading state of the data processing device of the present invention.

FIG. 3 is a diagram showing another data processing device of the present invention.

FIG. 4 is a diagram showing a conventional data processing device.

[Explanation of symbols]

 1, 11: CPU (control unit) 2, 12: ROM (memory) 3, 13: ROMC (memory control unit) 4: cache

Claims (3)

[Claims] 1. A control unit for issuing a load request for an instruction or data, a memory for storing the instruction or data, and a memory control unit for controlling a bus connected to the control unit and connected to the memory. Wherein the memory control unit predicts an instruction or a data load request of the control unit, and performs loading prior to the instruction or data load request of the control unit. Characteristic data processing device. 2. The data processing apparatus according to claim 1, wherein said control unit and said memory control unit are connected in one chip. 3. A cache which can be accessed at a higher speed than the memory, stores a part of instructions and data stored in the memory in the cache, and the control unit stores the instruction and data in the cache before the memory. 2. The data processing apparatus according to claim 1, wherein a load request is made, and a signal line for the load request to the cache is connected to the memory control unit.