JPH10335829A - Multilayered wiring board and its manufacture - Google Patents

Multilayered wiring board and its manufacture

Info

Publication number
JPH10335829A
JPH10335829A JP15309597A JP15309597A JPH10335829A JP H10335829 A JPH10335829 A JP H10335829A JP 15309597 A JP15309597 A JP 15309597A JP 15309597 A JP15309597 A JP 15309597A JP H10335829 A JPH10335829 A JP H10335829A
Authority
JP
Japan
Prior art keywords
wiring board
layer
hole
holes
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15309597A
Other languages
Japanese (ja)
Inventor
Keiichi Kishimoto
圭一 岸本
Masaki Uemae
昌己 上前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Carbide Industries Co Inc
Original Assignee
Nippon Carbide Industries Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Carbide Industries Co Inc filed Critical Nippon Carbide Industries Co Inc
Priority to JP15309597A priority Critical patent/JPH10335829A/en
Publication of JPH10335829A publication Critical patent/JPH10335829A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To execute drilling with a prescribed condition by forming conductor layers on the surface of an insulating resin layer and holes by an additive method and electrically connecting the circuit conductor pattern of a wiring board and the conductor layers in via holes. SOLUTION: A graphitization is executed on the surface of the conductor layer 6, and a copper oxide layer is formed. Then, a processing for chemically reducing the copper oxide layer into metallic copper is executed and the insulating resin layer 3 is stacked. The hole whose diameter is smaller than that of the via hole is formed in the same position as the via hole 15 by the irradiation with a laser and the hole reaching the conductor layer 6 is formed in the other position. Then, smearing in the holes is executed, and copper is deposited by a semi-additive method and a conductor layer 7 and via holes 13 and 16 are formed. In the multilayered wiring board which is thus generated, the drilling of the small diameter is easy and wiring density is high.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多層配線板のビアホー
ルの形成に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of via holes in a multilayer wiring board.

【0002】[0002]

【従来の技術】近年、電子機器の小型化に伴い、銅張り
の多層配線板の小型化、高密度化、軽量化などのために
多層配線板の導体幅、導体間隙、スルホール、ビアホー
ルなどの微細化、小径化などが求められている。これら
の要求のうちスルホール、ビアホールが積層された多層
配線板の表面から加工、形成されている。
2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, the conductor width, conductor gap, through hole, via hole and the like of a multilayer wiring board have been developed in order to reduce the size, density, and weight of a copper-clad multilayer wiring board. Miniaturization and small diameter are required. Of these requirements, the through hole and the via hole are processed and formed from the surface of the multilayer wiring board on which the through hole is laminated.

【0003】たとえば、積層された多層配線板の表面か
らドリルにより貫通孔をあける、ドリルにより途中まで
孔あけする。積層された多層配線板の表面からレーザに
より貫通孔、非貫通孔を形成するなどである。
[0003] For example, a through hole is drilled from the surface of a laminated multilayer wiring board by a drill, and a hole is partially drilled by a drill. For example, through holes and non-through holes are formed by laser from the surface of the laminated multilayer wiring board.

【0004】[0004]

【発明が解決しようとする課題】上記のような従来の多
層配線板の孔あけ加工の方法では製造工程に問題があ
る。ドリルによる方法においては、孔径が大きい、導体
層および絶縁層が薄い多層配線板の途中で孔あけを終了
することが非常に難しい、導体層と絶縁層を同時に孔あ
けするなどの問題がある。レーザによる方法において
は、積層した導体層および絶縁層並びに内装の導体層お
よび内装の絶縁層の孔あけ加工のコントロールが非常に
困難である問題がある。これらの孔あけ加工工程の困難
さを解決することである。
However, the conventional method for forming a hole in a multilayer wiring board as described above has a problem in the manufacturing process. The method using a drill has problems such as a large hole diameter, it is very difficult to complete the drilling in the middle of a multilayer wiring board having a thin conductive layer and an insulating layer, and a simultaneous drilling of the conductive layer and the insulating layer. In the method using a laser, there is a problem that it is very difficult to control the drilling of the laminated conductor layer and insulation layer, and the interior conductor layer and interior insulation layer. It is an object of the present invention to solve the difficulties of these drilling steps.

【0005】[0005]

【課題を解決するための手段】本発明は、導体層間を接
続するスルホール、ビアホールを有する多層配線板およ
びその製造方法において、回路導体パターンを形成した
配線基板に絶縁樹脂層を積層し、レーザにより該絶縁樹
脂層に該回路導体パターンに到達する孔を形成し、アデ
ィティブ方法により該絶縁樹脂層の表面および該孔に導
電体層を形成し、該配線基板の該回路導体パターンおよ
び該導電体層をビアホールにて電気接続してなることで
ある。最外層の絶縁樹脂層に孔あけするのみであり、比
較的弱いエネルギーのレーザでよく、また一定の条件で
孔あけできるコントロールの安易な加工工程である多層
配線板およびその製造方法を提供することである。
SUMMARY OF THE INVENTION The present invention relates to a multilayer wiring board having through holes and via holes for connecting conductive layers and a method for manufacturing the same, comprising: laminating an insulating resin layer on a wiring board on which a circuit conductive pattern is formed; A hole reaching the circuit conductor pattern is formed in the insulating resin layer, and a conductor layer is formed on the surface and the hole of the insulating resin layer by an additive method, and the circuit conductor pattern and the conductor layer of the wiring board are formed. Are electrically connected in a via hole. Provided is a multilayer wiring board and a method for manufacturing the same, which is an easy-to-control processing step capable of only drilling holes in the outermost insulating resin layer, using a laser having a relatively weak energy, and drilling holes under certain conditions. It is.

【0006】以下、本発明に係る多層配線板およびその
製造方法について詳述する。図1は、本発明に係る多層
配線板およびその製造方法の一実施態様を示す断面図で
ある。図2(a)はスルホールを形成した配線基板の断
面図である。図2(b)は配線基板に絶縁樹脂層積層
し、レーザで孔あけした断面図である。図2(c)は
(b)で孔あけした絶縁樹脂層にアディティブ方法によ
り導電体層およびビアホールを形成した断面図である。
図2(d)は(c)に更に絶縁樹脂層を積層し、レーザ
により孔あけした断面図である。
Hereinafter, a multilayer wiring board and a method of manufacturing the same according to the present invention will be described in detail. FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board and a method for manufacturing the same according to the present invention. FIG. 2A is a cross-sectional view of a wiring board in which a through hole is formed. FIG. 2B is a cross-sectional view in which an insulating resin layer is laminated on a wiring board and holes are formed by a laser. FIG. 2C is a cross-sectional view in which a conductor layer and a via hole are formed in the insulating resin layer formed in FIG. 2B by an additive method.
FIG. 2D is a cross-sectional view in which an insulating resin layer is further laminated on FIG.

【0007】本発明に係る多層配線板およびその製造方
法は、図1及び図2に示す如くコア樹脂層1に導電体層
より成る回路導体パターン5を形成した配線基板の片面
または両面に絶縁樹脂層2をそれ自体公知の方法で積層
し、該絶縁樹脂層2に孔12,15をレーザを用いて孔
あけ加工し(該絶縁樹脂層の下層に位置する配線基板の
回路導体パターン(導電体層)を孔あけすることな
く)、該孔にアディティブ方法により導体回路パターン
5(導電体層)と電気接続するビアホール12,15の
形成及び絶縁樹脂層2の表面に導電体層6の形成をして
多層配線板を作成する。
A multilayer wiring board and a method of manufacturing the same according to the present invention are shown in FIGS. 1 and 2 in which an insulating resin is provided on one or both sides of a wiring board in which a circuit conductor pattern 5 composed of a conductor layer is formed on a core resin layer 1. The layer 2 is laminated by a method known per se, and holes 12 and 15 are formed in the insulating resin layer 2 by using a laser (a circuit conductor pattern (conductor) of a wiring board located under the insulating resin layer. Layer), via holes 12 and 15 electrically connected to the conductor circuit pattern 5 (conductor layer) and formation of the conductor layer 6 on the surface of the insulating resin layer 2 by an additive method. To produce a multilayer wiring board.

【0008】更に、所望により絶縁樹脂層3を積層し、
該絶縁樹脂層3に孔13、16をレーザを用いて孔あけ
加工し、アディティブ方法でビアホール13、16およ
び導電体層7を形成して、より層数の多い多層配線基板
を作成することができる。更に同様に繰り返すことによ
り、より多層の多層配線基板を作成することができる。
Further, if desired, an insulating resin layer 3 is laminated,
Holes 13 and 16 are formed in the insulating resin layer 3 by using a laser, and the via holes 13 and 16 and the conductor layer 7 are formed by an additive method to form a multilayer wiring board having a larger number of layers. it can. Further, by repeating the same operation, a multilayer wiring board having more layers can be produced.

【0009】本発明に係る多層配線板およびその製造方
法におけるアディティブ方法とは、絶縁基板上に導電性
材料をたとえば無電解メッキなどにより選択的に析出さ
せ導体パターンを形成するプリント配線板の製法であ
る。例えば、絶縁基板に孔を形成し、メッキレジストに
よる回路パターン模様を形成後に孔壁および表裏の絶縁
基板表面上に無電解銅メッキのみで配線パターンを形成
するフルアディティブ方法がある。また、絶縁基板に孔
を形成し、全面(孔壁および表裏)に無電解銅メッキ層
を析出し、メッキレジストによる回路パターン模様を形
成して後に再度無電解銅メッキおよび/または電解銅メ
ッキをし、メッキレジストを剥離し、クイックエッチン
グにより最初の無電解銅メッキ層を除去して配線パター
ンを形成するセミアディティブ方法がある。また、絶縁
基板に孔を形成し、全面に無電解銅メッキ、電解銅メッ
キを施して後に該銅メッキ層に回路形成する方法があ
る。
The additive method in the multilayer wiring board and the method of manufacturing the same according to the present invention is a method of manufacturing a printed wiring board in which a conductive pattern is formed by selectively depositing a conductive material on an insulating substrate by, for example, electroless plating. is there. For example, there is a full additive method in which a hole is formed in an insulating substrate, a circuit pattern pattern is formed by a plating resist, and a wiring pattern is formed only on the hole wall and the front and back surfaces of the insulating substrate by electroless copper plating. Also, holes are formed in the insulating substrate, an electroless copper plating layer is deposited on the entire surface (hole walls and front and back), a circuit pattern pattern is formed by a plating resist, and then electroless copper plating and / or electrolytic copper plating is performed again. Then, there is a semi-additive method in which the plating resist is peeled off, and the first electroless copper plating layer is removed by quick etching to form a wiring pattern. There is also a method in which holes are formed in an insulating substrate, electroless copper plating and electrolytic copper plating are applied to the entire surface, and a circuit is formed on the copper plating layer.

【0010】本発明に係る多層配線板およびその製造方
法におけるアディティブ方法にて析出された導電体層の
厚みを特に限定するものではないが0.5〜50μmで
あることが好ましい。更に好ましくは1〜40μmであ
る。特に好ましくは3〜20μmである。
The thickness of the conductor layer deposited by the additive method in the multilayer wiring board and the method of manufacturing the same according to the present invention is not particularly limited, but is preferably 0.5 to 50 μm. More preferably, it is 1 to 40 μm. Particularly preferably, it is 3 to 20 μm.

【0011】本発明に係る多層配線板およびその製造方
法における絶縁樹脂層は特に限定するものではないが好
ましくは、エポキシ、ポリイミド、ボリエステル、フェ
ノール、ポリフェニレンエーテル、ポリフェニレンオキ
シド、ビスマレイミド・トリアジンなどの少なくとも一
種類を主成分とする樹脂類である。また、これらの樹脂
類であり紫外線硬化型樹脂類、熱硬化型樹脂類であるこ
とが好ましい。特に好ましくは、熱硬化型樹脂類である
ことである。また該絶縁樹脂層は、ガラス、アラミド、
紙、多孔質ポリテトラフルオロエチレン、クォーツなど
の不織布、織布などに樹脂類を含浸させた絶縁樹脂でも
よい。また該絶縁樹脂層には樹脂ビーズ、アルミナ粉、
酸化チタン粉、炭酸カルシウム粉などの有機、無機の充
填剤が充填されていてもよい。
The insulating resin layer in the multilayer wiring board and the method of manufacturing the same according to the present invention is not particularly limited. Resins mainly composed of one type. Further, these resins are preferably ultraviolet curable resins and thermosetting resins. Particularly preferred are thermosetting resins. The insulating resin layer is made of glass, aramid,
An insulating resin obtained by impregnating a resin with a nonwoven fabric such as paper, porous polytetrafluoroethylene, or quartz, or a woven fabric may be used. In addition, resin beads, alumina powder,
Organic or inorganic fillers such as titanium oxide powder and calcium carbonate powder may be filled.

【0012】本発明に係る多層配線板およびその製造方
法における積層した絶縁樹脂層への孔の形成は、下層に
形成されたスルホールおよび/またはビアホールの径と
比較して任意の径の孔をレーザにより形成することがで
きる。孔の形成位置は、下層に形成されたスルホールお
よび/またはビアホールとの同位置に形成する(ビア・
オン・ビア方法)または異なる位置に形成する。このよ
うに形成される孔は、積層した絶縁樹脂層をレーザによ
り溶融、気化、分解して形成され下層の導電体層が露出
される。アディティブ方法による電気接続によりビアホ
ールが完全・容易に形成される。
In the multilayer wiring board and the method for manufacturing the same according to the present invention, the holes are formed in the laminated insulating resin layer by using a laser having an arbitrary diameter as compared with the diameter of the through hole and / or via hole formed in the lower layer. Can be formed. The hole is formed at the same position as the through hole and / or via hole formed in the lower layer (via / hole).
(On-via method) or at a different position. The holes formed in this manner are formed by melting, vaporizing, and decomposing the laminated insulating resin layer with a laser, exposing the lower conductive layer. Via holes are completely and easily formed by the electrical connection by the additive method.

【0013】レーザの種類としては、炭酸ガスレーザ、
Xeレーザ、エキシマノーザ、YAGレーザ、Arレー
ザ、紫外線レーザなどが例示できる。
As the type of laser, a carbon dioxide laser,
An Xe laser, an excimer laser, a YAG laser, an Ar laser, an ultraviolet laser and the like can be exemplified.

【0014】[0014]

【実施例】以下、本発明に係る多層配線板およびその製
造方法の実施例を説明する。尚、本発明に係る多層配線
板およびその製造方法は以下の実施例に限られるもので
はない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a multilayer wiring board and a method of manufacturing the same according to the present invention will be described below. The multilayer wiring board and the method of manufacturing the same according to the present invention are not limited to the following embodiments.

【0015】(実施例1)先ず、ガラス不織布にエポキ
シ樹脂を含浸したコア樹脂層1の両面に厚さ18μmの
銅箔5aをラミネートした銅張り両面板に貫通孔11を
形成し、該銅箔5aおよび該貫通孔11にメッキ銅5b
を析出させ、フォトエッチング方法により回路導体パタ
ーン5を形成し、コア樹脂層1にスルホール11および
回路導体パターン5より成る配線基板を作成した。この
後、該配線基板に黒化処理を施し酸化銅層を形成後、該
酸化銅層を金属銅に化学還元する処理を施した。図2
(a)
(Example 1) First, a through-hole 11 was formed in a copper-clad double-sided board in which a copper foil 5a having a thickness of 18 µm was laminated on both sides of a core resin layer 1 in which a glass nonwoven fabric was impregnated with an epoxy resin. 5a and plated copper 5b in the through hole 11.
Was deposited, and a circuit conductor pattern 5 was formed by a photo-etching method. Thus, a wiring board including the through holes 11 and the circuit conductor pattern 5 in the core resin layer 1 was prepared. Thereafter, the wiring substrate was subjected to a blackening process to form a copper oxide layer, and then subjected to a process of chemically reducing the copper oxide layer to metallic copper. FIG.
(A)

【0016】次に、該配線基板に紫外線硬化型エポキシ
樹脂を塗布してUV照射を行い、約50μmの絶縁樹脂
層2を形成した。
Next, an ultraviolet-curable epoxy resin was applied to the wiring substrate and irradiated with UV to form an insulating resin layer 2 of about 50 μm.

【0017】次に、炭酸ガスレーザ装置の加工テーブル
に該絶縁樹脂層2を積層した該配線基板を位置決めセッ
トし、レーザ(パルス幅25μs、周波数100Hz)
を照射して、該絶縁樹脂層2に約0.1mmの孔12,
約0.2mmの孔15の孔あけ加工をした。(図2
(b))
Next, the wiring board on which the insulating resin layer 2 is laminated is positioned and set on a processing table of a carbon dioxide laser apparatus, and a laser (pulse width 25 μs, frequency 100 Hz) is set.
To the insulating resin layer 2 to form a hole 12,
A hole 15 of about 0.2 mm was drilled. (Figure 2
(B))

【0018】次に、過マンガン酸カリウム法により該孔
12および該孔15の内部のスミア処理を行い、セミア
ディティブ方法(絶縁樹脂層の表面、孔壁を塩化パラジ
ウムにより活性化し、メッキ溶液のホルマリン還元によ
り全面に銅の無電解メッキ層を形成し、該絶縁樹脂層に
メッキレジスト(メッキ用マスク)を塗布・パターン模
様を形成し、電解メッキにより厚さ約12μmの銅をビ
アホール内およびパターン模様に析出し、メッキレジス
トを剥離し、全面をクイックエッチングして先の無電解
メッキ層を除去した。)により該絶縁樹脂層2の表面、
該孔12、該孔15に銅を析出させて回路パターン模様
の導電体層6並びに回路導体パターン5と接続するビア
ホール12およびビアホール15を形成した。(図2
(c))
Next, the insides of the holes 12 and 15 are smeared by the potassium permanganate method, and the semi-additive method (the surface of the insulating resin layer and the hole walls are activated with palladium chloride, A copper electroless plating layer is formed on the entire surface by reduction, a plating resist (plating mask) is applied to the insulating resin layer, a pattern pattern is formed, and copper having a thickness of about 12 μm is formed in the via hole and the pattern pattern by electrolytic plating. , The plating resist was peeled off, and the entire surface was subjected to quick etching to remove the electroless plating layer.)
Copper was deposited in the holes 12 and 15 to form a conductor layer 6 having a circuit pattern pattern and via holes 12 and 15 connected to the circuit conductor pattern 5. (Figure 2
(C))

【0019】次に、該導電体層6の表面に黒化処理を施
し酸化銅層を形成後、該酸化銅層を金属銅に化学還元す
る処理を施し、更に絶縁樹脂層3を積層した。
Next, a blackening treatment was performed on the surface of the conductor layer 6 to form a copper oxide layer, and then a treatment for chemically reducing the copper oxide layer to metallic copper was performed, and an insulating resin layer 3 was further laminated.

【0020】次に、レーザの照射によりビアホール15
の同じ位置に該ビアホール15より小さい径の約0.1
mmの孔16を形成した。(該孔16は、ビアホール1
5の内部の絶縁樹脂に孔を形成し、導電体層6を露出し
ていた。)また、他の位置には導電体層6に到達する約
0.1mmの孔13を形成した(図2(d))。次に、
孔の内部のスミア処理を行いセミアディティブ方法によ
り銅を析出し導電体層7、ビアホール13、ビアホール
16を形成した。(図1)
Next, the via holes 15 are irradiated by laser irradiation.
Of the diameter smaller than the diameter of the via hole 15 by about 0.1
A hole 16 of mm was formed. (The hole 16 is a via hole 1
A hole was formed in the insulating resin inside 5 and the conductor layer 6 was exposed. In addition, a hole 13 of about 0.1 mm reaching the conductor layer 6 was formed at another position (FIG. 2D). next,
Smear treatment was performed inside the holes, and copper was deposited by a semi-additive method to form conductor layers 7, via holes 13, and via holes 16. (Fig. 1)

【0021】次に、表面の配線導体を保護するレジスト
を半田付けのエリアを除いて印刷・乾燥・硬化して多層
配線板を製作した。
Next, a resist for protecting the wiring conductor on the surface was printed, dried and cured except for an area for soldering to produce a multilayer wiring board.

【0022】このように製作された該多層配線基板は、
レーザのコントロールが安易であり、小径の孔あけ加工
が容易であり、配線密度が高密度であり、層間密着性が
良好で、電気接続の信頼性が高かった。
The multilayer wiring board thus manufactured is
Laser control was easy, small-diameter drilling was easy, wiring density was high, interlayer adhesion was good, and electrical connection reliability was high.

【0023】(実施例2)実施例1における炭酸ガスレ
ーザ装置を紫外線レーザ装置(Nd:YAGの波長35
5nmを利用した個体UVレーザ)に変更して孔あけ加
工をする以外は実施例1の製造工程と略同様にして多層
配線板を製作した。
(Embodiment 2) The carbon dioxide gas laser device in Embodiment 1 is replaced with an ultraviolet laser device (wavelength of Nd: YAG 35
A multilayer wiring board was manufactured in substantially the same manner as in the manufacturing process of Example 1 except that a hole was formed by changing to a solid UV laser using 5 nm.

【0024】このように製作された該多層配線基板は、
レーザのコントロールが安易であり、導電体層へのダメ
ージがなく、小径の孔あけ加工が容易であり、絶縁樹脂
層はレーザにより化学変化を起こして分解除去されるた
め炭素化することがなくカーボンの残渣問題がなく、配
線密度が高密度であり、層間密着性が良好であり、電気
接続の信頼性が高かった。
The multilayer wiring board thus manufactured is
Laser control is easy, there is no damage to the conductor layer, small-diameter drilling is easy, and the insulating resin layer undergoes a chemical change by the laser and is decomposed and removed. There was no residue problem, the wiring density was high, the interlayer adhesion was good, and the reliability of electrical connection was high.

【0025】[0025]

【発明の効果】本発明に係る多層配線板およびその製造
方法では、比較的弱いパワーでコントロールが安易なレ
ーザにより絶縁樹脂層に孔あけを行うことであり、次層
の導電体層で孔が停止する効果があり、アディティブ方
法により回路を形成するため電気接続の信頼性が高い。
などの加工工程の困難さを除いた多層配線板およびその
製造方法を提供できる。
In the multilayer wiring board and the method of manufacturing the same according to the present invention, holes are formed in the insulating resin layer by a laser with relatively low power and easy to control, and holes are formed in the next conductive layer. There is an effect of stopping, and since the circuit is formed by the additive method, the reliability of the electrical connection is high.
It is possible to provide a multilayer wiring board and a method of manufacturing the same, which eliminate the difficulty of processing steps such as the above.

【0026】[0026]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る多層配線板およびその製造方法の
一実施態様を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a multilayer wiring board and a method for manufacturing the same according to the present invention.

【図2】(a)、(b)、(c)、(d)は、本発明に
係る多層配線板およびその製造方法の一実施態様の工程
の概略を示す断面図である。
FIGS. 2 (a), (b), (c) and (d) are cross-sectional views schematically showing the steps of an embodiment of a multilayer wiring board and a method of manufacturing the same according to the present invention.

【0027】[0027]

【符号の説明】[Explanation of symbols]

1 コア樹脂層 2 絶縁樹脂層2 3 絶縁樹脂層3 5 回路導体パターン 5a 銅箔層 5b 銅メッキ層 6 導電体層6 7 導電体層7 11 スルホール 12 ビアホール12、孔12 13 ビアホール13、孔13 15 ビアホール15、孔15 16 ビアホール16、孔16 DESCRIPTION OF SYMBOLS 1 Core resin layer 2 Insulating resin layer 2 3 Insulating resin layer 3 5 Circuit conductor pattern 5a Copper foil layer 5b Copper plating layer 6 Conductor layer 6 7 Conductor layer 7 11 Through hole 12 Via hole 12, Hole 12 13 Via hole 13, Hole 13 15 via hole 15, hole 15 16 via hole 16, hole 16

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 導体層間を接続するスルホール、ビアホ
ールを有する多層配線板およびその製造方法において、
回路導体パターンを形成した配線基板に絶縁樹脂層を積
層し、レーザにより該絶縁樹脂層に該回路導体パターン
に到達する孔を形成し、アディティブ方法により該絶縁
樹脂層の表面および該孔に導電体層を形成し、該配線基
板の該回路導体パターンおよび該導電体層をビアホール
にて電気接続してなることを特徴とする多層配線板およ
びその製造方法。
1. A multilayer wiring board having through holes and via holes for connecting conductive layers and a method of manufacturing the same.
An insulating resin layer is laminated on the wiring board on which the circuit conductor pattern is formed, a hole reaching the circuit conductor pattern is formed in the insulating resin layer by a laser, and a conductor is formed on the surface of the insulating resin layer and the hole by an additive method. A multilayer wiring board and a method of manufacturing the multilayer wiring board, wherein a layer is formed, and the circuit conductor pattern and the conductor layer of the wiring board are electrically connected to each other through a via hole.
JP15309597A 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture Pending JPH10335829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15309597A JPH10335829A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15309597A JPH10335829A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Publications (1)

Publication Number Publication Date
JPH10335829A true JPH10335829A (en) 1998-12-18

Family

ID=15554870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15309597A Pending JPH10335829A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Country Status (1)

Country Link
JP (1) JPH10335829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000041447A1 (en) * 1999-01-05 2000-07-13 Ppc Electronic Ag Method for producing a multilayer printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000041447A1 (en) * 1999-01-05 2000-07-13 Ppc Electronic Ag Method for producing a multilayer printed circuit board

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