JPH10335494A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device that is suited for miniaturization without reducing the reliability of a semiconductor storage element (data- retaining characteristics and the number of times for rewriting data). SOLUTION: By forming a recessed and projecting part at a region where a control gate and a floating gate on a semiconductor substrate 201 overlap, the capacity between the floating and control gates can be easily increased. A first photoresist 203 is formed on the semiconductor substrate 201 and the field insulation film 202, one portion of the semiconductor substrate 201 at a region where the control and floating gates overlap is eliminated by the dry etching method, thus forming a recessed and projecting part on the semiconductor substrate 201.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor memory device is as shown in FIG.

A field insulating film 3 is formed on a semiconductor substrate 301.
02, the insulating film 305, and the tunnel oxide film 306,
And an insulating film 307 between the floating gate and the control gate is formed.
2, and the insulating film 305, and the tunnel oxide film 3
06, and the floating gate 308 was formed on the insulating film 307 between the floating gate and the control gate. Then, a deep diffusion layer 303 and a control gate 304 are formed in the semiconductor substrate 301 below the tunnel oxide film. In addition, no irregularities were present on the semiconductor substrate in a region where the floating gate 308 and the control gate 304 overlapped.

The conventional method for manufacturing a semiconductor memory device is shown in FIGS. 4A to 4C. First, as shown in FIG. 4A, a field insulating film 402 is formed on a semiconductor substrate 401, and a sacrificial oxide film 403 is formed by a thermal oxidation method. Then, a first photoresist 405 is formed in a region other than the region where the tunnel oxide film is to be formed and the region where the control gate is to be formed, and a conductive impurity 406 is injected into the semiconductor substrate 401 to form a first photoresist 405 under the tunnel oxide film. A dark diffusion layer 404 and a control gate 407 are formed.

Next, as shown in FIG. 4B, after removing the first photoresist 405 and the sacrificial oxide film 403, an insulating film 408 is formed by a thermal oxidation method. And the second
A photoresist 409 is formed, and the insulating film 408 is formed in a region where a floating gate and a control gate insulating film are formed and a region where a tunnel oxide film is formed.
Is removed.

Next, as shown in FIG. 4C, after the second photoresist 409 is removed, a floating gate and an inter-control gate insulating film 411 are formed on the control gate 407 by a thermal oxidation method, and a thick layer below the tunnel oxide film is formed. A tunnel oxide film 410 is formed on the diffusion layer 404. Then, a floating gate 412 is formed on the tunnel oxide film 410, the insulating film between the floating gate and the control gate 411, the insulating film 408, and the field insulating film 402.

The above is the description of the prior art semiconductor memory device and its manufacturing method.

[0008]

However, in the above-mentioned prior art, there is a problem that the overlapping area between the floating gate and the control gate is large and the semiconductor memory element cannot be miniaturized. If the overlapping area between the floating gate and the control gate is reduced by using the conventional technology, the capacitance between the floating gate and the control gate is reduced, and the time required for rewriting data becomes longer. there were. If the thickness of the insulating film between the floating gate and the control gate is reduced in order to increase the capacitance between the floating gate and the control gate, the thickness of the tunnel oxide film becomes thinner and the data retention characteristics of the semiconductor memory element deteriorate. In addition, there is a problem that the reliability of the tunnel oxide film (such as the allowable charge passing amount Qbd of the tunnel oxide film) deteriorates and the number of times data can be rewritten decreases.

Therefore, the present invention solves such a problem, and an object of the present invention is to improve the reliability (data retention characteristics and the number of times data can be rewritten) of a semiconductor memory element.
An object of the present invention is to provide a semiconductor memory device suitable for miniaturization without lowering the size.

[0010]

[Means for Solving the Problems]

(Means for Solving the Problem 1) A semiconductor memory device of the present invention has a floating gate and a control gate, and a control threshold value of the characteristics of the control gate depends on the state of charge injection into the floating gate. In a semiconductor memory device, wherein a voltage changes and the control gate is formed in a semiconductor substrate, unevenness is formed in a semiconductor substrate in a region where a floating gate and a control gate overlap. And

(Means for Solving the Problem 2) A method of manufacturing a semiconductor memory device according to the present invention includes a floating gate and a control gate, and the control gate is controlled by the state of charge injection into the floating gate. In the method for manufacturing a semiconductor memory device, wherein the control threshold voltage of the characteristic is changed and the control gate is formed in the silicon substrate, the control gate is formed in a region where the floating gate and the control gate overlap. It is characterized by forming irregularities.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an example of the semiconductor memory device of the present invention.

Reference numeral 101 denotes a semiconductor substrate, 102 denotes a field insulating film, 103 denotes a control gate, 104
Is a deep diffusion layer below the tunnel oxide film; 105 is an insulating film between the floating gate and the control gate;
Is an insulating film, 107 is a tunnel oxide film of about 7 nm to 12 nm, and 108 is a floating gate.

The semiconductor substrate 101 is formed with irregularities in a region where the control gate 103 and the floating gate 108 overlap.

Next, an example of a method of manufacturing a semiconductor memory device according to the present invention will be described in detail with reference to FIGS.

In all of the drawings of the embodiment, those having the same symbols are given the same reference numerals, and their repeated explanation is omitted.

First, as shown in FIG.
A silicon nitride film is formed in a predetermined shape on 1. Then, thermal oxidation is performed to form a field insulating film 202. The field insulating film 202 has a thickness of 400 nm to 800 nm.
Degree formed. The silicon nitride film is removed and a first layer is formed on the semiconductor substrate 201 and the field insulating film 202.
A photoresist 203 is formed, and the semiconductor substrate 201 is formed in a region where the control gate and the floating gate overlap each other by using a dry etching method.
Is removed to form irregularities on the semiconductor substrate 201. The irregularities are formed in a thickness of about 30 nm to 400 nm.

Next, as shown in FIG. 2B, after the first photoresist 203 is removed, a sacrificial oxide film 204 is formed on the semiconductor substrate 201 from 15 nm to 40 nm by a thermal oxidation method.
m. Then, a second photoresist 205 is formed, and a conductive impurity 206 is implanted by an ion implantation method or the like, thereby forming a dense diffusion layer 2 under the tunnel oxide film.
07 and a control gate 208 are formed. The conductive impurities 206 may be, for example, a Group 5 element (a conductive impurity such as a phosphorus element or arsenic) in a range of 1 × 10 ¹³ to 1 × 1.
Implantation is performed at about ¹⁶ atoms / cm ⁻² .

Next, as shown in FIG. 2C, after the second photoresist 205 is removed, the conductive impurities 206 are activated in a nitrogen atmosphere of, for example, about 850 to 1000 degrees in order to activate the conductive impurities 206. Anneal for about a minute. After removing the sacrificial oxide film 204, an insulating film 209 of about 7 nm to 40 nm is formed on the semiconductor substrate 201 by a thermal oxidation method. Then, a photoresist is formed, and the insulating film 209 formed in the region for forming the tunnel oxide film and the region for forming the control gate is removed. Then, the tunnel oxide film 2 is formed by a thermal oxidation method.
11, an insulating film 210 between the floating gate and the control gate is formed to a thickness of about 7 to 12 nm. The thermal oxidation is performed, for example, at 1000 ° C. in a dry atmosphere having an oxygen concentration of about 60%. Then, the tunnel oxide film 211, the insulation 209, and the insulation film 2 between the floating gate and the control gate are formed by a CVD method or the like.
10 and a polycrystalline silicon film is formed on the field insulating film 202 to a thickness of about 100 nm to 400 nm. Usually, monosilane gas is thermally decomposed at about 620 degrees to deposit the polycrystalline silicon film. Then, in order to lower the resistance of the polycrystalline silicon, for example, an element of group V (consistent impurities such as phosphorus element and arsenic) is implanted by ion implantation.
Implantation is performed at about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ atoms · cm ⁻² . And by photo and etching method,
The polycrystalline silicon film is formed in a predetermined shape, and a floating gate 212 is formed.

The above is the method of manufacturing the semiconductor memory device according to the present invention.

As described above, by removing a part of the semiconductor substrate in a region where the floating gate and the control gate overlap, the capacitance between the floating gate and the control gate can be reduced, and the insulating film between the floating gate and the control gate can be thinned. It is possible to increase the overlap area without increasing the area, and to provide a semiconductor memory device suitable for miniaturization.

Although the present invention has been described in detail based on the embodiments, the present invention is not limited to the above-described embodiments, but may be modified without departing from the scope of the invention. It is. For example, in the method of manufacturing a semiconductor device according to the present invention, a polycrystalline silicon film is used for the floating gate. However, it is needless to say that a case where a high melting point metal silicide or the like is used is also effective. Further, in the embodiment of the present invention, the recess is formed in the semiconductor substrate after forming the field insulating film 202, but the same effect can be obtained by forming the recess in the semiconductor substrate before forming the field insulating film. .

[0024]

According to the present invention, there is provided a floating gate and a control gate, and the control threshold voltage of the characteristics of the control gate changes depending on the state of charge injection into the floating gate. In the method for manufacturing a semiconductor memory device, wherein the gate is formed in a silicon substrate, the area where the control gate and the floating gate overlap may be formed with irregularities to increase the overlapping area, The capacitance between the control gate and the floating gate can be increased without reducing the thickness of the insulating film 210 between the floating gate and the control gate, and the reliability of the semiconductor memory device (data retention characteristics and the number of times data can be rewritten). Without dropping It is possible to provide a semiconductor memory device suitable for thinning.

[Brief description of the drawings]

FIG. 1 is a main sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a main cross-sectional view for describing one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 3 is a main cross-sectional view for explaining a conventional semiconductor memory device.

FIG. 4 is a main cross-sectional view for describing a method for manufacturing a conventional semiconductor memory device.

[Explanation of symbols]

Reference Signs List 101 semiconductor substrate 102 field insulating film 103 control gate 104 dense diffusion layer under tunnel oxide film 105 insulating film between floating gate and control gate 106 insulating film 107 tunnel oxide film 108 floating gate 201 semiconductor substrate 202 field insulating film 203 first photo Resist 204 sacrificial oxide film 205 second photoresist 206 conductive impurity 207 dense diffusion layer under tunnel oxide film 208 control gate 209 insulating film 210 insulating film between floating gate and control gate 211 tunnel oxide film 212 floating gate 301 semiconductor substrate 302 field Insulating film 303 Deep diffusion layer below tunnel film 304 Control gate 305 Insulating film 306 Tunnel oxide film 307 Insulating film between the loading gate and the control gate 308 floating gate 401 semiconductor substrate 402 field insulating film 403 sacrificial oxide film 404 dense diffusion layer 405 below tunnel oxide film 405 first photoresist 406 conductive impurities 407 control gate 408 insulating film 409 2 photoresist 410 tunnel oxide film 411 insulating film between floating gate and control gate 412 floating gate

Claims (5)

[Claims] A control gate having a floating gate and a control gate, wherein a control threshold voltage of a characteristic of the control gate changes according to a state of charge injection into the floating gate; A semiconductor memory device characterized in that unevenness is formed in a semiconductor substrate in a region where a floating gate and a control gate overlap with each other. 2. A semiconductor device comprising a floating gate and a control gate, wherein a control threshold voltage of a characteristic of the control gate changes depending on a state of charge injection into the floating gate. A method of manufacturing a semiconductor memory device, characterized by forming irregularities on a semiconductor substrate in a region where a floating gate and a control gate overlap with each other. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the unevenness formed on the semiconductor substrate is formed using a photo and etching method. 4. A method for manufacturing a semiconductor memory device according to claim 3, wherein the unevenness formed on the semiconductor substrate is formed before forming an element isolation such as a field insulating film. . 5. The method of manufacturing a semiconductor memory device according to claim 3, wherein the unevenness formed on the semiconductor substrate is formed after forming an element isolation such as a field insulating film.