JPH11145430A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form two ion implanting layers which face opposite uniformly by a method, wherein a common diffused layer is formed on the region, which becomes a common source diffused layer, deeper than the source diffused layer. SOLUTION: A photoresist 8 is patterned in such a manner that the region, which becomes a common source diffused layer, is exposed, first ions are implanted and a source diffused layer 9 is formed. When a field oxide film 2 is etched anisotropically using the photoresist 8 as a mask, a silicon step is formed. When the second ion implantation of arsenic are conducted on the whole surface of a P-type semiconductor substrate in this state, a common source diffused layer 10 is formed deeper than the source diffused layer 9 on the P-type semiconductor substrate, where the field oxide film is removed, and on the inside of the region where the source diffusion layer 9 has already been formed. The ion implanted layer is uniformly diffused in the lateral direction and formed in a uniformly resisting state, without irregularities with the lower surface of a floatign gate 4 on the surface of the P-type semiconductor substrate 1 in the heat treatment process conducted subsequently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a nonvolatile semiconductor memory capable of electrically writing and erasing data.

[0002]

2. Description of the Related Art Among conventional semiconductor memory devices, a nonvolatile semiconductor memory, particularly a flash memory, has been receiving attention in recent years for a function of collectively erasing data, and a memory cell has been miniaturized in order to mount the flash memory in a microcomputer or the like. Demands are growing. Various manufacturing methods have been proposed for miniaturization of memory cells of a flash memory, but none of them has provided a sufficient manufacturing method in terms of minimizing variation in erase time.

A method of manufacturing a conventional nonvolatile semiconductor memory and its performance will be described with reference to the drawings. As a first example, JP-A-6-125092 and JP-A-7-106441
The manufacturing method disclosed in Japanese Patent Application Laid-Open Publication No. H10-26095 will be described. 8 to 1
FIG. 1 is a sectional view and a plan view showing a part of the steps of a conventional method for manufacturing a nonvolatile semiconductor memory. Fig. 8-
In each of FIGS. 11A and 11B, (c) is a plan view in a certain step, and (a) and (b) are cross-sectional views along line AA and BB in plan view (c), respectively.

A field oxide film 2 for element region isolation is formed on a P-type semiconductor substrate 1 to a thickness of 600 to 800 nm.
First insulating film 3 made of a thermal oxide film having a thickness of 0 to 20 nm
Is grown, and a chemical vapor deposition (hereinafter referred to as CVD)
8 (a) to 8 (c), a polysilicon is grown to a thickness of 100 to 300 nm by a method and selectively removed with a photoresist to form a floating gate 4 in a band shape. is there.

Next, a second insulating film 5 made of a thermal oxide film having a thickness of 10 to 30 nm or an ONO film having a three-layer structure of an oxide film / nitride film / oxide film is formed on the entire surface of the semiconductor substrate including the floating gate 4. Then, polysilicon is grown to a thickness of 200 to 400 nm by CVD. First
A state in which polysilicon having a thickness of 200 to 400 nm is coated on the entire surface of the semiconductor substrate on the laminated film sequentially laminated with the insulating film 3, the floating gate 4, the second insulating film 5, and the word line 18 is controlled. Select from 200 to 40 with photoresist to form gate 6
A stacked film including polysilicon having a thickness of 0 nm is patterned by using a known anisotropic etching technique. At this time,
As shown in FIG. 9C, the band-shaped laminated film including the control gate 6 is formed so as to be orthogonal to the band-shaped field oxide film 2. Next, after removing the photoresist, CV
The entire surface of the semiconductor substrate including the laminated film is covered with the protective insulating film 7 having a thickness of 100 nm (grown to a thickness of 100 nm in Japanese Patent Application Laid-Open No. 6-125092) by Method D. FIGS. 9A to 9C show this state.

[0006] Thereafter, as shown in FIGS. 10A to 10 C, the protective insulating film 7 on the region to become the common source diffusion layer 10 between the word lines 18 including the control gate 6.
The photoresist 8 is patterned so that the word line 18 including the control gate 6 can be removed from the field oxide film 2 as a self-aligned mask. Using the photoresist 8 as a mask, the field oxide film 2 and the protective insulating film 7 between the word lines 18 including the control gate 6 are used.
Is removed by anisotropic oxide film etching, and the P-type semiconductor substrate 1 is removed.
To expose. Further, in this state, ion implantation 21 of arsenic or phosphorus is performed using the word line 18 including the photoresist 8 and the control gate 6 as a mask, thereby forming the common source diffusion layer 1.
0 is formed.

Finally, as shown in FIGS. 11A to 11C, after forming a drain diffusion layer 11, an interlayer BPSG is formed over the entire surface.
A film 12 is formed, and a contact 13 is formed on the drain diffusion layer 11.
Open. An aluminum wiring 14 serving as a digit line is formed on the opened contact 13 to complete a nonvolatile semiconductor memory.

In a first example of a conventional manufacturing method, a photoresist having a thickness of 600 to 800 nm between word lines 18 including a control gate 6 is formed using a photoresist 8 as a mask to form a common source diffusion layer 10. The oxide film 2 and the protective insulating film 7 having a thickness of 100 nm are simultaneously removed by the conventional technique of anisotropic dry etching. When this etching is performed, as shown in FIG. 10A, in the element region between the word lines 18 including the control gate 6, the thickness of the protective insulating film 7 covering the region is small.
In addition to the protective insulating film 7 having a thickness of 0 nm, the P-type semiconductor substrate 1 thereunder is subjected to oxide film anisotropic dry etching. Since the etching selectivity between silicon and the oxide film is finite, a silicon step 17 is formed on the P-type semiconductor substrate 1 after the etching as shown in FIG. as a result,
Floating gate 4 immediately after anisotropic dry etching
The P-type semiconductor substrate 1 is exposed at a position lowered by the height of the silicon step 17 from the upper end of the floating gate 4. When arsenic or phosphorus is ion-implanted in this state, the common source diffusion layer 10 at the lower end of the floating gate 4 is exposed. FIG. 11 shows the impurity distribution.
It becomes almost round as shown in FIG. this is,
This is because the ion implantation is performed perpendicularly to the P-type semiconductor substrate 1 so that the implantation into the silicon step 17 side wall at the lower end of the floating gate 4 is less.

Next, as a second example of the conventional manufacturing method, Japanese Unexamined Patent Publication No. 6-125092 shows a manufacturing method in which the silicon step 17 in the first example is not generated. This manufacturing method is described by using a first example of a conventional manufacturing method and FIGS.
Since the steps are substantially the same, the description will be made with reference to FIGS. As shown in FIGS. 9A to 9C, the protective insulating film 7 is formed to a thickness of 50 nm on the top and side surfaces of the laminated film including the control gate 6 by the CVD method (the first example is the 7 is formed). Next, the photoresist 8 is patterned so that the 50-nm-thick protective insulating film 7 on the element region where the common source diffusion layer 10 between the word lines 18 including the control gate 6 is to be formed can be removed. When a 45 nm-thickness is etched by the second anisotropic dry etching and the remaining 5 nm-thickness is removed by wet etching of ammonium fluoride or the like, the P of the element region where the common source diffusion layer 10 is to be formed is formed. The surface of the mold semiconductor substrate is exposed. Next, as shown in FIGS. 12A to 12C, the surface of the P-type semiconductor substrate between the word lines 18 including the control gate 6 is
The tungsten film 15 is selectively grown to a thickness of 20 to 30 nm. Further, in this state, as shown in FIGS. 13A to 13C, a second anisotropic dry etching is performed to form a film having a thickness of 600 to 600 nm on a region to become the common source diffusion layer 10 between the control gates 6. 800 nm field oxide film 2
Is removed. At this time, since the surface of the P-type semiconductor substrate between the word lines 18 including the control gate 6 is protected by the tungsten film 15, the surface of the P-type semiconductor substrate thereunder is not etched, and Unlike the example, the silicon step 17 does not occur on the surface of the P-type semiconductor substrate in the element region between the word lines 18 including the control gate 6. Thereafter, by performing ion implantation 21 of arsenic or phosphorus, the common source diffusion layer 10 having a stable and constant facing area can be formed at the lower end of the floating gate 4 as shown in FIGS.

[0010]

As described above, the nonvolatile semiconductor memory completed by the conventional manufacturing method of the first example has the following characteristics. That is, a voltage of about 12 V is applied to the control gate 6 (the common source diffusion layer 10 is grounded, and a voltage of about 7 V is applied to the drain diffusion layer 11). By applying a voltage of 10 to 12 V to the diffusion layer 10 (the control gate 6 is grounded),
The electrons in the floating gate 4 are drawn out and erased. In this case, as shown in FIG. 11C, the common source diffusion layer 10 in the element region is mainly formed below the bottom surface of the silicon step 17, and the silicon step 17 is formed. 17 is difficult to be formed in the vicinity of the surface of the semiconductor substrate, and the facing area between the floating gate 4 and the common source diffusion layer 10 is not uniform within each memory cell, and is not uniform between each memory cell. The electron withdrawal time at the time varies, and the erase time varies. Since the performance of the nonvolatile semiconductor memory is determined by the longest erase time (electron extraction time) of the memory cell, the operation time of the nonvolatile semiconductor memory is long, and the erase time varies among the nonvolatile semiconductor memory products. Tends to occur.

In the nonvolatile semiconductor memory completed by the manufacturing method of the second conventional example, tungsten or molybdenum is selectively grown on the exposed semiconductor substrate 1 between the stacked films including the control gate 6. However, an atmosphere of about 200 ° C. is required for selective growth, and selective growth is performed with the photoresist 8 attached. In this case, the photoresist 8 is deformed during the growth, or a photoresist gas is generated from the surface, which hinders the selective growth or results in a non-uniform selective growth film thickness. Heat-resistant photoresists with improved photoresist characteristics have limitations in terms of miniaturization, and have a manufacturing problem that they cannot be used particularly for photoresists that require miniaturization. Further, in this manufacturing method, tungsten or molybdenum is used as a stopper for anisotropic dry etching, but the process is long and complicated, and as a result, the cost of a wafer or a chip is increased.

A method of manufacturing a semiconductor device according to the present invention is to realize a high-quality nonvolatile semiconductor memory with a small variation in erase time by a practical and economical manufacturing method.

[0013]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of arranging a plurality of element forming regions on a surface of a semiconductor substrate in a band shape in parallel with a field oxide film as a boundary; A first gate insulating film is formed on a formation region, and a plurality of floating gates are formed on the first gate insulating film so as to partially cover the plurality of element formation regions and to be separated from each other on the field oxide film. Forming a second gate insulating film on the plurality of floating gates, and forming a control gate on the second gate insulating film in a band shape at a predetermined interval so as to be orthogonal to the field oxide film. Forming a protective insulating film covering the entire semiconductor substrate including the control gate; and forming a common source diffusion layer between the control gates. Forming a photoresist so that the region is not covered, and forming a source diffusion layer having a predetermined depth in a self-aligned manner using the control gate as a mask in the plurality of element forming regions between the control gates Removing the field oxide film on the region to be the common source diffusion layer and the protective insulating film on the plurality of element formation regions using the photoresist as a mask; and forming the common source diffusion layer. Forming a common source diffusion layer deeper than the source diffusion layer in the region.

Further, in the method of manufacturing a semiconductor device according to the present invention, a plurality of element forming regions are arranged on a surface of a semiconductor substrate in a band shape in parallel with a field oxide film as a boundary. Forming a first gate insulating film on a region, a plurality of floating gates on the first gate insulating film, covering a part of the plurality of element formation regions, and being separated from each other on the field oxide film; Forming a second gate insulating film on the plurality of floating gates, and forming a control gate on the second gate insulating film in a strip shape at a predetermined interval so as to be orthogonal to the field oxide film; Forming a protective insulating film covering the entire semiconductor substrate including the control gate; and forming a common source diffusion layer between the control gates. Forming a photoresist so as not to be covered, removing the field oxide film on a region to be the common source diffusion layer and the protective insulating film on the plurality of element formation regions, and controlling the control gate. The common source diffusion layer to be formed in the plurality of element formation regions includes a region that overlaps with the floating gate via the first gate insulating film at least on the same surface as the semiconductor substrate. And a step formed so as to be formed.

[0015]

Next, a first embodiment of the present invention will be described. Since the first embodiment is substantially the same as the first example according to the conventional manufacturing method up to FIGS. 8 and 9, detailed description up to FIGS. 8 and 9 is omitted. FIG. 9 (a)-
As shown in FIG. 3C, after the strip-shaped word line 18 including the control gate 6 is formed so as to be orthogonal to the strip-shaped field oxide film 2, the photoresist is removed, and the entire surface of the semiconductor substrate including the laminated film is thermally oxidized. Oxidized, protective insulating film 7
It is formed to a thickness of 0 nm. Next, as shown in FIGS. 1A to 1C, the photoresist 8 is patterned so that a region to be a common source diffusion layer is exposed. In this state, an implantation energy of 40 KeV is applied to the entire surface of the P-type semiconductor substrate.
When the first ion implantation 22 of arsenic or phosphorus is performed, the source diffusion layer 9 is formed.

Subsequently, as shown in FIGS. 2A to 2C, the field oxide film 2 having a thickness of about 600 to 800 nm is formed from the state of FIGS. Is anisotropically etched. At this time, as in the first conventional example, the protective oxide film 7 on the source diffusion layer 20 is over-etched, and a silicon step 17 is formed. In this state, an implantation energy of 70 K is applied to the entire surface of the P-type semiconductor substrate.
When the second ion implantation 23 of arsenic or phosphorus is performed at eV, the second source diffusion is performed on the P-type semiconductor substrate from which the field oxide film 2 has been removed and inside the region where the source diffusion layer 9 has already been formed. As a layer, a common source diffusion layer 10 is formed deeper than the source diffusion layer 9.

Subsequently, the photoresist 8 is removed, a drain diffusion layer 11 is formed, an interlayer BPSG 12 is grown on the entire surface, and a contact 13 is opened on the drain diffusion layer 11.
Then, by forming the aluminum wiring 14 as a digit line on the entire surface, the nonvolatile semiconductor memory is completed as shown in FIGS.

As described above, after the entire surface of the semiconductor substrate including the word lines 18 is oxidized to form the protective insulating film 7, ions are selectively implanted into a region to be a source diffusion layer in the element region. When a uniform ion-implanted layer is formed on the surface of the P-type semiconductor substrate 1, the ion-implanted layer is uniformly diffused in the lateral direction in the subsequent heat treatment step, and the lower surface of the floating gate 4 and the irregularities are formed on the surface of the P-type semiconductor substrate 1. It is formed in the form of uniformly facing each other.

Next, a second embodiment of the manufacturing method of the present invention will be described. Since the present embodiment is substantially the same as the first example according to the conventional manufacturing method up to FIGS.
Detailed description of up to 10 is omitted. FIG.
As shown in (c), the field oxide film 2 and the protective insulating film 7 between the control gates 6 are removed by etching using the photoresist 8 as a mask, and the P-type semiconductor substrate 1 is removed.
To expose. Further, in this state, ion implantation of arsenic or phosphorus is performed using the word line 18 including the photoresist 8 and the control gate 6 as a mask.
As shown in (c), the ion implantation is performed at an implantation energy of 70 Ke.
The common source diffusion layer 10 is formed by oblique ion implantation 24 of V. By rotating and oblique ion implantation, the common source diffusion layer 10 in the element region becomes floating gate 4
A structure having a constant reproducible facing area with the lower surface is obtained. Subsequent steps are performed in the same manner as in the first embodiment, and the nonvolatile semiconductor memory is completed as shown in FIGS.

Next, a third embodiment of the present invention will be described. In the present embodiment, in FIG. 4 (a) to FIG. 4 (c), between the word lines 18 including the control gate 6 using the photoresist 8 as a mask. The process is the same as that of the second embodiment up to the point where the protective oxide film 7 and the field oxide film 2 on the region to be the common source diffusion layer 10 are removed by etching. Thereafter, the photoresist 8 is removed, and FIG.
As shown in (a) to (c), a PSG film 16 containing phosphorus as an impurity is grown to a thickness of 200 nm over the entire surface of the P-type semiconductor substrate 1 and heat-treated at 950 ° C. for 30 minutes in a nitrogen atmosphere. By this heat treatment, the phosphorus in the PSG film 16 undergoes solid-phase diffusion into the P-type semiconductor substrate 1, and the common source diffusion layer 10 is formed. Thereafter, the drain diffusion layer 11 and the interlayer BPSG film 1 are formed.
2, the contact 13, and the aluminum wiring 14 are formed, and the nonvolatile semiconductor memory is completed as shown in FIGS.

As described above, in the second and third embodiments, the non-uniform impurity distribution in the silicon step 22 of the source diffusion layer, which is generated in the first example of the conventional method of manufacturing a semiconductor device, is obtained by rotating oblique ion implantation. The impurity diffusion can be improved to a uniform impurity distribution by solid phase diffusion of phosphorus from the PSG film. As in the first embodiment of the method for manufacturing a semiconductor device of the present invention, the source diffusion layer is made of a P-type semiconductor substrate. It can be formed so as to uniformly face the lower surface of the floating gate 4 without unevenness on one surface.

[0022]

As described above, the method of manufacturing a semiconductor device according to the present invention is intended to improve the non-uniform impurity distribution in the silicon step of the source diffusion layer caused in the first example of the conventional method of manufacturing a semiconductor device. Before the formation of the silicon step, ions are implanted in advance through the protective insulating film into the region to be the source diffusion layer of the element region, or when the silicon step is formed, the oblique ion implantation or the PSG film is used. By performing solid phase diffusion of phosphorus from the element, the source diffusion layer in the element region can have a uniform impurity distribution. That is, the source diffusion layer in the element region can be formed on the surface of the P-type semiconductor substrate so as to be uniformly opposed to the lower surface of the floating gate via the gate oxide film without unevenness.

In addition, it is not necessary to grow a stopper film such as tungsten or molybdenum for protecting the surface of the element region in the element region between the word lines including the control gates. It will be economical.

As described above, since the facing area between the floating gate and the source diffusion layer can be uniformly and stably formed in each memory cell, the erasing operation time of the nonvolatile semiconductor memory does not vary among the cells, and the reproducibility can be improved. It will be good.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view and a plan view illustrating a first embodiment of the present invention, showing a state where a source diffusion layer of a nonvolatile semiconductor memory cell is formed.

FIG. 2 is a cross-sectional view and a plan view of a step following the embodiment of FIG. 1, illustrating a state where a common source diffusion layer of a nonvolatile semiconductor memory cell is formed.

FIG. 3 is a process sectional view and a plan view following the embodiment of FIG. 2, showing a state in which a nonvolatile semiconductor memory cell is completed.

FIG. 4 is a cross-sectional view and a plan view illustrating a second embodiment of the present invention, in which a state in which a common source diffusion layer of a nonvolatile semiconductor memory cell is formed is shown.

5 is a cross-sectional view and a plan view of a step following the embodiment in FIG. 4, showing a state in which a nonvolatile semiconductor memory cell is completed.

FIGS. 6A and 6B are a cross-sectional view and a plan view illustrating a third embodiment of the present invention, showing a state where a common source diffusion layer of a nonvolatile semiconductor memory cell is formed.

7 is a cross-sectional view and a plan view of a step following the embodiment in FIG. 6, showing a state in which a nonvolatile semiconductor memory cell is completed.

8A and 8B are a cross-sectional view and a plan view illustrating a first example of a conventional method for manufacturing a semiconductor device, showing a state where a floating gate of a nonvolatile semiconductor memory cell is formed.

9 is a cross-sectional view and a plan view of a step following FIG. 8, illustrating a state in which a control gate of the nonvolatile semiconductor memory cell is formed.

10 is a cross-sectional view and a plan view of a step following FIG. 9, illustrating a state where a common source diffusion layer of the nonvolatile semiconductor memory cell is formed.

FIG. 11 is a cross-sectional view and a plan view of a step following FIG. 10, showing a state where the nonvolatile semiconductor memory cell is completed.

FIG. 12 is a cross-sectional view and a plan view showing a second example of a conventional method for manufacturing a semiconductor device, in which a field oxide film over a region where a common source diffusion layer of a nonvolatile semiconductor memory cell is to be formed is removed; FIG. 3 is a diagram showing a state before the operation.

13 is a cross-sectional view and a plan view of a step following FIG. 12, showing a state after a field oxide film on a region where a common source diffusion layer of a nonvolatile semiconductor memory cell is to be formed is removed; is there.

FIG. 14 is a cross-sectional view and a plan view of a step following FIG. 13, showing a state where a common source diffusion layer of the nonvolatile semiconductor memory cell is formed.

FIG. 15 is a cross-sectional view and a plan view of a step following FIG. 14, showing a state where the nonvolatile semiconductor memory cell is completed.

[Explanation of symbols]

 Reference Signs List 1 P-type semiconductor substrate 2 Field oxide film 3 First insulating film 4 Floating gate 5 Second insulating film 6 Control gate 7 Protective insulating film 8 Photoresist 9 Source diffusion layer 10 Common source diffusion layer 11 Drain diffusion layer 12 Interlayer BPSG film 13 Contact 14 Aluminum wiring 15 Tungsten film 16 PSG film 17 Silicon step 18 Word line 21 Ion implantation 22 First ion implantation 23 Second ion implantation 24 Rotation oblique ion implantation

Claims (5)

[Claims] A step of arranging a plurality of element formation regions on a surface of a semiconductor substrate in a strip shape in parallel with a field oxide film as a boundary, a first gate insulating film and a first gate on the plurality of element formation regions; A plurality of floating gates are formed on the insulating film so as to partially cover the plurality of element formation regions and to be separated from each other on the field oxide film, and a second gate is formed on the plurality of floating gates. Forming an insulating film, forming a control gate in a strip shape on the second gate insulating film so as to be orthogonal to the field oxide film at a predetermined interval, and forming a protective insulation covering the entire semiconductor substrate including the control gate. Forming a film, and forming a photoresist so as not to cover a region to be a common source diffusion layer between the control gates Forming a source diffusion layer having a predetermined depth in a self-aligned manner using the control gate as a mask in the plurality of element formation regions between the control gates; and forming the common source using the photoresist as a mask. Removing the field oxide film on the region to be a diffusion layer and the protective insulating film on the plurality of element formation regions; and forming a common source deeper than the source diffusion layer in the region to be the common source diffusion layer. Forming a diffusion layer. 2. A step of arranging a plurality of element formation regions on a surface of a semiconductor substrate in parallel with each other with a field oxide film as a boundary, a first gate insulating film and a first gate on the plurality of element formation regions. A plurality of floating gates are formed on the insulating film so as to partially cover the plurality of element formation regions and to be separated from each other on the field oxide film, and a second gate is formed on the plurality of floating gates. Forming an insulating film, forming a control gate in a strip shape on the second gate insulating film so as to be orthogonal to the field oxide film at a predetermined interval, and forming a protective insulation covering the entire semiconductor substrate including the control gate. Forming a film, and forming a photoresist so as not to cover a region to be a common source diffusion layer between the control gates Removing the field oxide film on the region to be the common source diffusion layer and the protective insulating film on the plurality of element formation regions; and removing the protective oxide film on the plurality of element formation regions between the control gates. Forming the common source diffusion layer to be formed at least on the same surface as the semiconductor substrate so as to include a region overlapping with the floating gate via the first gate insulating film. A method for manufacturing a semiconductor device, comprising: 3. The method according to claim 1, wherein said protective insulating film has a thickness of 20 to 30 nm. 4. The method according to claim 2, wherein the common source diffusion layer is formed by oblique rotation ion implantation. 5. The photoresist is removed after the common source diffusion layer removes the field oxide film on a region to be the common source diffusion layer and the protective insulating film on the plurality of element formation regions. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the method is formed by a step of forming a phosphorus glass film covering the entire semiconductor substrate including the control gate, and a step of heat-treating the entire semiconductor substrate.