JPH11330274A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure that can prevent the deterioration of transistor characteristics and make ease the injection of hot carrier to a floating gate, with respect to the manufacturing method of semiconductor device having a nonvolatile memory. SOLUTION: A gate insulation film 4, a floating gate FG consisting of a first semiconductor, an intermediate insulation film 6, a control gate CG consisting of a second semiconductor, and a protective insulation film 9 are formed like a stripe in order, and then a covering insulation film 10 which covers the side surfaces of the stripe-like films, the upper surface of the protection insulation film 9 and the surface of a semiconductor substrate 1 on both sides of the control gate CG is formed at 50 nm or lower of thickness by the vapor phase growth method. Further impurities are introduced to the semiconductor substrate 1 through the covering insulation film 10 on both sides of the control gate CG, forming impurity introduction layers 12s and 12d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a nonvolatile memory.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device (LSI) that has been miniaturized, a system LSI in which many circuits are formed in one chip has been developed. In this context, there is a demand for higher integration of non-volatile memory cells, miniaturization and higher performance of logic circuit elements, and integration of these non-volatile memory cells and logic circuits. I have.

A conventional nonvolatile memory cell is generally formed by the following steps. First, steps required until a state shown in FIG. In the cell formation region of the silicon substrate 101 surrounded by the field oxide film 102, the gate insulating film 103 and the impurity-containing first polycrystalline silicon film 10 are formed.
4. An intermediate insulating film 105 made of SiO ₂ is formed. Thereafter, the first polycrystalline silicon film 104 and the intermediate insulating film 105 are patterned by photolithography to leave those films in and around the cell formation region.

Subsequently, a second polycrystalline silicon film 106 containing impurities, a refractory metal silicide film 107, and a protective insulating film 108 made of silicon oxide are formed on the intermediate insulating film 105 and the field oxide film 102. Next, the films from the protective insulating film 108 to the gate insulating film 103 are sequentially etched using one resist mask (not shown). As a result, the second polycrystalline silicon film 105 is patterned into the shape of the strip-shaped control gate wiring cg, and the upper and lower films are formed in a shape corresponding to the control gate wiring cg. By such patterning, the first polycrystalline silicon film 104 in one cell forming region is separated from the first polycrystalline silicon film 104 in another cell forming region and becomes electrically floating. Polycrystalline silicon film 104
Are used as floating gate electrodes fg.

Next, as shown in FIG. 9B, a first polycrystalline silicon film forming the floating gate electrode fg is formed.
The exposed side surfaces of the second polycrystalline silicon film 106 constituting the control gate wiring 104 and the control gate wiring cg are thermally oxidized to form a coating insulating film 109. Due to the thermal oxidation, the thickness of the SiO ₂ film 110 on the surface of the silicon substrate 101 increases. Control gate wiring cg and floating gate electrode f
The reason why the coating insulating film 108 is formed on the side surface of the gate electrode g is to suppress the introduction of impurities due to ion implantation in a later step and to prevent the charge injected into the floating gate electrode fg after the completion of the device from leaking. .

Thereafter, impurities are ion-implanted into the silicon substrate 101 to form a low-concentration and shallow impurity diffusion layer. Next, as shown in FIG.
An insulating sidewall 111 is formed on the side surfaces of the gate g and the floating gate fg. Further, using the protective insulating film 108 and the insulating sidewall 111 as a mask, the silicon substrate
101 is ion-implanted with a second impurity.

[0007] By two times impurity ion implantation, FIG.
A source layer 112s and a drain layer 112d having an LDD structure as shown in FIG. 3C are formed on the silicon substrate 101 on both sides of the floating gate electrode fg.

[0008]

[SUMMARY OF THE INVENTION Incidentally, the control gate lines cg, the side surfaces of the floating gate electrode fg at the time of forming the insulating cover film 109 is thermally oxidized, SiO ₂ film 110 is also the surface of the silicon substrate 101 is oxidized Is deeper than the gate insulating film 103, and the boundary between the floating gate electrode fg and the silicon substrate 101 is oxidized.

Therefore, it is difficult for hot carriers generated at the end of the drain layer 111d to tunnel through the gate insulating film 103, so that hot carriers are less likely to be injected into the floating gate electrode fg. Further, the ends of the source layer 112s and the drain layer 112d having the LDD structure are farther from the floating gate electrode fg and the drain current is reduced.
There is a disadvantage that the transistor characteristics are deteriorated.

[0010] Such inconvenience becomes more noticeable as the element becomes finer. An object of the present invention is to provide a method of manufacturing a semiconductor device for preventing deterioration of transistor characteristics and obtaining a structure that facilitates hot carrier injection into a floating gate.

[0011]

Means for Solving the Problems The above-mentioned problems are solved in FIGS.
As illustrated in FIG. 4, a gate insulating film 4, a first impurity-containing semiconductor film 5,
Forming an intermediate insulating film 6, a second impurity-containing semiconductor film 7, and a protective insulating film 9; and forming the first impurity-containing semiconductor layer 5, the intermediate insulating film 6, the second impurity-containing semiconductor film 7, Patterning the protective insulating film 9 so that the first impurity-containing semiconductor layer 5 has a shape of a floating gate FG and the second impurity-containing semiconductor layer 7 has a shape of a control gate CG; A gate insulating film 10 covering the gate FG, the intermediate insulating film 6, the control gate CG, the side surfaces of the protective insulating film 9, the upper surface of the protective insulating film 9, and the surface of the semiconductor substrate 1 on both sides of the control gate CG. Forming the film to a thickness of 50 nm or less and 5 nm or more by vapor phase epitaxy; and forming the coating insulating film 10 on both sides of the control gate CG. And forming impurities introducing layers 12 s and 12 d by introducing impurities into the semiconductor substrate 1 through the semiconductor device 1.

In the above-described method of manufacturing a semiconductor device,
Forming a second gate insulating film 24 in a logic circuit formation region of the semiconductor substrate 1 and forming the second impurity-containing semiconductor film 7 and the protective insulating film 9 on the second gate insulating film 24 And patterning the second impurity-containing semiconductor film 7 and the protective insulating film 9 to form the second impurity-containing semiconductor layer 7 into the gate electrode 21.
And forming the covering insulating film 10 on the side surfaces of the gate electrode 24 and the protective insulating film 9, the upper surface of the protective insulating film 9, and the surface of the semiconductor substrate 1 on both sides of the gate electrode 24. And a step of introducing impurities into the semiconductor substrate 1 through portions of the coating insulating film 9 on both sides of the gate electrode 24 to form impurity introduction layers 31s and 31d.

In the method of manufacturing a semiconductor device described above,
The covering insulating film 10 is a single-layer film of silicon oxide or a single-layer film of silicon nitride. Alternatively, the coating insulating film 9 is formed by forming a single-layer film of silicon oxide and then heat-treating the surface of the single-layer film in an oxidizing atmosphere. Alternatively, the coating insulating film is formed by forming a single-layer film of silicon nitride and then heat-treating the surface of the single-layer film in an oxidizing atmosphere. Alternatively, the coating insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film. Alternatively, the covering insulating film is formed by sequentially forming a silicon oxide film and a silicon nitride film, and then performing a heat treatment on the silicon nitride film in an oxygen-containing atmosphere. Alternatively, the coating insulating film is formed by forming a silicon nitride film and a silicon oxide film in this order, and then performing a heat treatment on the silicon oxide film in an oxygen-containing atmosphere. Or
The covering insulating film 10 is formed by forming a silicon film and then heating and oxidizing the silicon film in an oxygen-containing atmosphere.

In the method of manufacturing a semiconductor device described above,
The second impurity-containing semiconductor film 7 and the protective insulating film 9
The method further comprises a step of forming a refractory metal silicide film 8 therebetween. Next, the operation of the present invention will be described. According to the present invention, when the control gate and the floating gate are each formed of an impurity-containing semiconductor film, the thermal insulation film is not used as the coating insulating film covering the side surfaces of the floating gate and the control gate, and the vapor-deposited coating insulating film is used. A film is used, and the film thickness is set to 50 nm or less and 5 nm or more.

Therefore, the side portion of the gate insulating film between the floating gate and the semiconductor substrate is prevented from being thickened by the reaction with oxygen. This makes it easier for hot carriers from the drain in the semiconductor substrate to move to the floating gate by tunneling through the gate insulating film,
Moreover, since it becomes difficult to form an insulating film deeper than the gate insulating film on the semiconductor substrate on both sides of the floating gate,
The distance between the source / drain layer and the floating gate formed there does not increase, and the transistor characteristics do not deteriorate.

Further, since the thickness of the coating insulating film is set to 50 nm or less, when the impurity is ion-implanted into the semiconductor substrate to form the source / drain layers, the impurity is implanted into the semiconductor substrate. A high-performance memory cell is formed without being blocked by the film. Such a process of forming the covering insulating film does not deteriorate the electrical characteristics of the MOS transistor when the MOS transistor is formed in the logic circuit region in parallel with the memory cell.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. 1 to 4 are cross-sectional views showing a process of forming a memory cell of a semiconductor device according to an embodiment of the present invention, and FIGS. 5 and 6 are plan views thereof. 7 and 8 are cross-sectional views illustrating a process of forming a MOS transistor in a logic circuit region of a semiconductor device.

First, steps required until a state shown in FIG. A field oxide film 2 is formed on the surface of a silicon substrate (semiconductor substrate) 1 by a selective oxidation method. The field oxide film 2 is formed in a portion surrounding the element formation region 3. Subsequently, the surface of the silicon substrate (semiconductor substrate) 1 in the element forming region 3 is thermally oxidized to form the gate oxide film 4 several times.
It grows to a thickness of not less than 50 nm and not more than 10 nm, for example.
The gate insulating film 4 is a film through which hot carriers tunnel.

Next, a first polycrystalline silicon film 5 is formed on the gate insulating film 4 and the field oxide film 2 to a thickness of 100 nm. Subsequently, phosphorus is introduced into the first polycrystalline silicon film 5 by an ion implantation method or a thermal diffusion method, whereby the sheet resistance of the first polycrystalline silicon film 5 is set to about 300.
Reduce to Ω / □. Note that phosphorus may be introduced simultaneously with the growth of the first polycrystalline silicon film 5.

After that, the surface of the first polycrystalline silicon film 5 is thermally oxidized to form SiO ₂ to be an intermediate insulating film 6 to a thickness of 8 nm. Thereafter, the intermediate insulating film 6 and the first polycrystalline silicon film 5 are patterned by a photolithography technique, so that these films cover the element formation region 3 and Y as shown in the plan view of FIG. The stripe shape extends in the direction.

In this patterning, the intermediate insulating film 6 and the first polycrystalline silicon film 5 are removed from a logic circuit region described later. Thereby, the surface of the silicon substrate 1 is exposed in the element formation region of the logic circuit. Therefore, the surface of the silicon substrate 1 in the element formation region of the logic circuit is thermally oxidized. According to this thermal oxidation, the first polycrystalline silicon film 5
Is also oxidized, and the thickness of the intermediate insulating film 6 increases to 18 nm.

Next, as shown in FIGS. 1 (b) and 5 (b), a second polycrystalline silicon film 7 is formed to a thickness of 120 nm by CVD over the entire area including the memory cell area and the logic area. I do. Thereafter, phosphorus is introduced into the second polycrystalline silicon film 7 in the same manner as the first polycrystalline silicon film 5 to reduce its sheet resistance to about 300 Ω / □. Furthermore, CV
By a method D, a refractory metal silicide film 8 such as a refractory metal silicide film and a protective insulating film 9 made of SiO ₂ are grown on the second polycrystalline silicon film 7 to a thickness of 175 nm and 100 nm, respectively. The refractory metal silicide film 8 is formed from the second polycrystalline silicon film 7 in order to reduce the resistance of the wiring or electrode used.

Subsequently, as shown in FIGS. 1C and 6A, X from the protective insulating film 9 to the gate insulating film 4 is patterned by photolithography.
A stripe pattern 11 having a width of 0.5 μm to 0.8 μm extending in the direction is formed. The stripe pattern 11 is a multi-layered pattern including the stripe-shaped protective insulating film 9 to the gate insulating film 4.

Thus, the second polycrystalline silicon film 7
Is the shape of the control gate CG. The control gate CG has a stripe shape crossing the center of the element forming region 3 as shown in FIG. The first polysilicon film 5 below the control gate CG is patterned to have the same width as the control gate CG, is isolated from other element formation regions in the element formation region 3, and is used as a floating gate FG.

Next, the silicon substrate 1 is put into a CVD apparatus (not shown), and a reaction gas containing nitrogen dioxide (N ₂ O) and silane (SiH ₄ ) is introduced into a chamber of the CVD apparatus.
The gas pressure in the chamber is reduced to 0.1 Torr, and the silicon substrate 1 is heated at 800 ° C. Under these conditions, as shown in FIGS. 2A and 6B, the upper surface and side surfaces of the stripe pattern 11, the upper surface of the silicon substrate 1, and the upper surface of the field oxide film 2 are formed to a thickness of 5 to 50 nm made of silicon dioxide. For example, a coating insulating film 10 of 10 nm is grown.

The growth of the coating insulating film 10 is performed by using ammonia (NH ₃ ) or silane (SiH ₄ ) as a reaction gas.
May be used to grow silicon nitride. The covering insulating film 10 may be a two-layer film of silicon dioxide 8a or silicon nitride 8b as shown in FIG. The lower layer of the two-layer structure film may be either silicon dioxide 8a or silicon nitride 8b. Further, the coating insulating film 10 may be made of silicon nitride oxide grown by using a reaction gas of SiH ₄ , N ₂ O and NH ₃ .

The step of forming the covering insulating film 10 may include a step of forming a silicon nitride film, a silicon oxide film, or a two-layer structure film and then heating the film in an oxygen-containing atmosphere.
Furthermore, the coating insulating film 10 may be a film obtained by forming a silicon film having a thickness of about 5 nm by CVD and then oxidizing the silicon film by heating in an oxygen-containing atmosphere. In the step of forming the coating insulating film 10, the reaction gas does not react with the control gate CG, the floating gate FG, and the silicon constituting the substrate 1, so that the surface of the silicon substrate 1 is not oxidized, and the bottom of the floating gate FG and There is no bird's beak of the SiO ₂ layer on the side as shown in FIG. 9 (b).

After the formation of the coating insulating film 10 as described above, an acceleration energy of 60 keV and a dose of 2 × 10 ¹³ ato
Under the condition of ms / cm ² , phosphorus is ion-implanted into the element formation region 3 of the silicon substrate 1. In this case, stripe pattern 1
1. The field oxide film 2 functions as a mask for etching. As a result, low-concentration impurity introduction layers 12s and 12d as shown in FIG. 2B are formed on the silicon substrate 1 on both sides of the floating gate FG. Since the floating gate FG and the control gate CG are not directly subjected to ion implantation by the covering insulating film 10, damage due to ion implantation is small. If the covering insulating film 10 has a thickness of about 50 nm, the implantation of impurity ions into the silicon substrate 1 is not prevented.

Thereafter, as shown in FIG.
The SiO ₂ film 13 is grown to a thickness of 250 nm entirely by the method. Further, the SiO ₂ film 1 is formed by reactive ion etching.
3 is etched in the vertical direction, and is left on the side surface of the pattern 11. Thus, an insulating side wall 13s as shown in FIGS. 3A and 6C is formed. Since the surface of the silicon substrate 1 is exposed in the element formation region 3 by this etching, the surface is heated in an oxygen atmosphere at 850 ° C. to form a 5-nm thick SiO ₂ film 14 as shown in FIG. .

Subsequently, arsenic is ion-implanted into the element formation region 3 of the silicon substrate 1 under the conditions of an acceleration energy of 50 keV and a dose of 3 × 10 ¹⁵ atoms / cm ² . In this case, the stripe pattern 11, the sidewalls 13s, and the field oxide film 2 function as a mask for preventing ion implantation. Thus, high-concentration impurity introduction layers 15s and 15d are formed on the silicon substrate 1 on both sides of the floating gate FG.

Subsequently, the silicon substrate 1 is placed in a nitrogen atmosphere, and the silicon substrate 1 is heated at 1000 ° C. for 10 seconds to activate the low-concentration impurity introduction layers 11 s and 11 d and the high-concentration impurity introduction layers 15 s and 15 d. This allows LDD
A source layer 16s and a drain layer 16d having a structure are formed.
In parallel with the formation of the above memory cells, MOS transistors are used in the logic circuit region of the silicon substrate 1 in FIGS.
It is formed in a process as shown in FIG.

First, the field oxide film 2 shown in FIG.
The gate insulating film 4, the first polycrystalline silicon film 5, and the like shown in FIG. However, at the time of patterning the first polycrystalline silicon film 5, those films are not etched and left from the element formation region 23. Then, as shown in FIG. 5A, after the patterning of the first polycrystalline silicon film 5 is completed, the surface of the element forming region 23 of the silicon substrate 1 is thermally oxidized to form the gate insulating film 24. This thermal oxidation increases the thickness of the intermediate insulating film 6 shown in FIG.

Thereafter, the second polycrystalline silicon film 7, the tungsten silicide film 8, and the protective insulating film 9 are similarly formed in the logic element forming region 23. Then, when these films are patterned as shown in FIG. 1 (c), those films in the element formation region 23 are also patterned at the same time as shown in FIG.
The gate electrode 21 of the S transistor is formed. The gate electrode 21 is composed of the second polycrystalline silicon film 7 and the refractory metal silicide film 8, on which the protective insulating film 9 is formed, and the gate insulating film 24 exists under the protective insulating film 9.

After that, as shown in FIG. 7B, the gate electrode 21 and the silicon substrate 1 are covered with the above-mentioned covering insulating film 10. Further, low-concentration impurity introduction layers 31s and 31d are formed on the silicon substrate 1 on both sides of the gate electrode 21. Next, on both sides of the gate electrode 21, when forming the side wall 13s shown in FIG. 3A, the side wall 13t shown in FIG. 7C is formed.

Subsequently, as shown in FIG. 8A, a high-concentration impurity-doped layer 34 is
s, 34d are formed. The low-concentration and high-concentration impurity introduction layers 31 s, 31 d, 34 s, and 34 d are activated by the heat treatment to form the LDD source layer 35 s and the drain layer 35.
d.

The low-concentration or high-concentration impurity introduction layer 3
1s, 31d, 34s, and 34d are low-concentration or high-concentration impurity introduction layers 11s and 11d in the memory cell region.
It may be formed by ion implantation at the same time as 15s and 15d, or may be formed by another ion implantation process.
Another ion implantation process is to change the conductivity type of the source layer 35s and the drain layer 35d to p-type using boron as an impurity. At this time, n is set in the logic circuit region 23 of the rear substrate 1.
A mold well must be formed.

After completing the steps of forming elements in the memory cell forming region 3 and the logic element forming region 23 as described above, as shown in FIGS. 3C and 8B, A block layer 16 made of SiO ₂ having a thickness of 200 nm is entirely formed, and an interlayer insulating film 17 made of PSG (phosphorus glass) is formed on the block layer 16 by a CVD method to a thickness of 600 nm.
Formed to a thickness of The block layer 16 is formed to prevent phosphorus contained in PSG from diffusing downward.

Next, the interlayer insulating film 17 is heated and melted at about 850 ° C. to flatten its upper surface. Further, the interlayer insulating film 17 is patterned by photolithography to form contact holes 18a to 18d on the source layers 16s and 35s and the drain layers 16d and 35d as shown in FIGS. 4 (a) and 8 (c). Form. Then, C
Tungsten 19 is selectively grown in contact holes 18a to 18d by the VD method.

Subsequently, a wiring material such as aluminum is formed on the interlayer insulating film by sputtering, and the wiring material is patterned to form an element connection wiring 20a to 20c shown in FIGS. 4 (b) and 8 (c). 20d is formed. Thereafter, although not particularly shown, a silicon nitride film is grown as a protective insulating film (not shown) for protecting the element by improving the moisture resistance, and further, the silicon nitride film is opened to expose the wiring, and the wiring is exposed. In general, a film forming process and a patterning process for forming an LSI, such as forming a pad in an opening, are performed.

[0040]

As described above, according to the present invention, when the control gate and the floating gate are each formed of an impurity-containing semiconductor film, the side surfaces of the floating gate and the control gate are covered with the coating insulating film grown by vapor phase. Moreover, the thickness of the coating insulating film is set to 50
The thickness is 5 nm or less and 5 nm or less.

Therefore, it is possible to prevent the side portion of the gate insulating film between the floating gate and the semiconductor substrate from being thickened by the reaction with oxygen. Therefore, hot carriers emitted from the drain in the semiconductor substrate tunnel through the gate insulating film and easily move to the floating gate,
Moreover, since it becomes difficult to form an insulating film deeper than the gate insulating film on the semiconductor substrate on both sides of the floating gate,
An increase in the distance between the source / drain layers formed there and the floating gate can be prevented.

Further, since the thickness of the covering insulating film is set to 50 nm or less, when the impurity is ion-implanted into the semiconductor substrate to form the source / drain layers, the implantation of the impurity into the semiconductor substrate is performed by the covering insulating film. The film can be prevented from being blocked.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views (part 1) illustrating a process of forming a memory cell of a semiconductor device according to the present invention;

FIGS. 2A to 2C are cross-sectional views (part 2) illustrating a process of forming a memory cell of the semiconductor device of the present invention.

FIGS. 3A to 3C are cross-sectional views (part 3) illustrating a process of forming a memory cell of the semiconductor device of the present invention.

FIGS. 4A and 4B are cross-sectional views (No. 4) showing a step of forming a memory cell of the semiconductor device of the present invention.

FIGS. 5A and 5B are plan views (part 1) illustrating a process of forming a memory cell of the semiconductor device of the present invention.

6 (a) to 6 (c) are plan views (part 2) illustrating a step of forming a memory cell of the semiconductor device of the present invention.

FIGS. 7A to 7C are cross-sectional views (part 1) illustrating a process of forming a MOS transistor of a logic circuit of the semiconductor device of the present invention.

FIGS. 8A to 8C are cross-sectional views (part 2) illustrating a process of forming a MOS transistor of a logic circuit of the semiconductor device according to the present invention.

FIGS. 9A to 9C are cross-sectional views illustrating a process of forming a memory cell of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate (semiconductor substrate), 2 ... Field oxide film, 3 ... Element formation area, 4 ... Gate insulating film, 5 ... First polycrystalline silicon film, 6 ... Intermediate insulating film, 7 ... Second polycrystalline Silicon film, 8: refractory metal silicide, 9: protective insulating film, 10: covering insulating film, 11: stripe pattern, 1
2s, 12d: low-concentration impurity introduction layer, 13: SiO ₂ film,
14: SiO ₂ film, 15s, 15d: high-concentration impurity introduction layer, 16s: source layer, 16d: drain layer.

Claims (10)

[Claims] A step of forming a gate insulating film, a first impurity-containing semiconductor film, an intermediate insulating film, a second impurity-containing semiconductor film, and a protective insulating film in a memory cell forming region of a semiconductor substrate; By patterning the impurity-containing semiconductor layer, the intermediate insulating film, the second impurity-containing semiconductor film, and the protective insulating film, the first impurity-containing semiconductor layer is formed into a floating gate, and the second impurity-containing semiconductor layer is formed. Forming a semiconductor layer in the shape of a control gate; and a side surface of the floating gate, the intermediate insulating film, the control gate and the protective insulating film, an upper surface of the protective insulating film, and a surface of the semiconductor substrate on both sides of the control gate. A coating insulating film covering 50
a thickness of 5 nm or less and a thickness of 5 nm or more, and a step of introducing an impurity into the semiconductor substrate through the coating insulating film on both sides of the control gate to form an impurity introduction layer. Semiconductor device manufacturing method. 2. A step of forming a second gate insulating film in a logic circuit forming region of the semiconductor substrate; and forming the second impurity-containing semiconductor film and the protective insulating film on the second gate insulating film. Forming the second impurity-containing semiconductor film and the protective insulating film into a shape of a gate electrode by patterning the second impurity-containing semiconductor film and the protective insulating film; and a side surface of the gate electrode and the protective insulating film. Forming the covering insulating film on the upper surface of the protective insulating film and on the surface of the semiconductor substrate on both sides of the gate electrode; and impregnating the semiconductor substrate through portions of the covering insulating film on both sides of the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an impurity-introduced layer by introducing the impurity. 3. The method according to claim 1, wherein the covering insulating film is a single-layer film of silicon oxide or a single-layer film of silicon nitride. 4. The method according to claim 1, wherein the covering insulating film is formed by forming a single-layer film of silicon oxide and then heat-treating the surface of the single-layer film in an oxidizing atmosphere. 3. The method for manufacturing a semiconductor device according to item 2. 5. The method according to claim 1, wherein the covering insulating film is formed by forming a single-layer film of silicon nitride and then heat-treating the surface of the single-layer film in an oxidizing atmosphere. 3. The method for manufacturing a semiconductor device according to item 2. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the covering insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film. 7. The method according to claim 1, wherein the covering insulating film is formed by forming a silicon oxide film and a silicon nitride film in that order, and then heat-treating the silicon nitride film in an oxygen-containing atmosphere. A method for manufacturing a semiconductor device according to claim 2. 8. The method according to claim 1, wherein the covering insulating film is formed by forming a silicon nitride film and a silicon oxide film in this order, and then heat-treating the silicon oxide film in an oxygen-containing atmosphere. A method for manufacturing a semiconductor device according to claim 2. 9. The method according to claim 1, wherein the covering insulating film is formed by forming a silicon film, and then heating and oxidizing the silicon film in an oxygen-containing atmosphere. Of manufacturing a semiconductor device. 10. The semiconductor device according to claim 1, further comprising a step of forming a refractory metal silicide film between said second impurity-containing semiconductor film and said protective insulating film. Manufacturing method.