JPH10335330A - Multilayered trench wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered trench wiring having high electromigration resistance, without forming voids in a lower layer wiring. SOLUTION: This wiring is constituted of connection holes 9 and an upper layer wiring 2 formed by filling a wiring material in upper layer wiring trenches and connection holes of a layer insulation film 1 on a lower wiring 5 which is connected to the upper layer wiring 2 via its connection holes 2. A first barrier layer 6 is provided on the surface of the lower wiring 5 at the connection hole side, and at least a slit-like second barrier layer 7 is provided at the lower wiring 5, so as to run across the length of the lower layer wiring 5 and divide the wiring 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer trench wiring. More specifically, the present invention relates to a multilayer grooved wiring having no voids in a lower wiring and having good electromigration (EM) resistance.

[0002]

2. Description of the Related Art With the increase in the degree of integration of LSIs, multilayer wiring and finer wiring are being developed. As a leading technology for that,
Wiring materials (for example, C) that are relatively easy to flatten between layers and to form fine wiring and are difficult to perform RIE processing
Attention has been paid to a trench wiring technique applicable to u).

In this groove wiring technique, a wiring material such as Al, Al-Cu, Cu or the like is formed on an interlayer insulating layer in which a groove is formed in advance, and the film is embedded in the groove, and is subjected to chemical mechanical polishing (CMP).
This is a technique for forming a wiring by removing a wiring material deposited on a portion other than the groove by a method or the like and leaving the wiring material only in the groove portion.

As an effective technique for embedding a wiring material in a groove, a wiring material is formed by sputtering (including high-temperature sputtering) on a substrate on which an interlayer insulating film having a groove is formed, and then heated and melted. A technique of embedding a material in a groove (a reflow method including a high-pressure reflow method) is known. here,
In the case of the reflow method, in order to bury the wiring material efficiently, it is necessary to heat the substrate before the film formation by sputtering, and to degas moisture and the like in the interlayer insulating film. This is because, if the degassing is insufficient, moisture and the like are released from the interlayer insulating film when the substrate is heated at the time of sputtering film formation or reflow, and therefore, the wiring material such as Al and the underlying layer (for example, TiN) are removed. This is because an oxidized layer is formed at the interface to cause poor filling.

[0005] When such a reflow method is actually applied to the trench wiring technique, the heat treatment of the substrate is performed in an annealing (preheating) step provided before the sputter film formation, or in a sputter film formation apparatus in a sputter film formation apparatus. And heating usually to about 400 to 500 ° C.

[0006]

However, when the reflow method of the wiring material is applied to the trench wiring technique, as shown in FIG. 3, Al or the like is formed at the bottom of the connection hole 32 formed in the interlayer insulating film 31. Since the substrate heating is performed while the lower wiring 33 is exposed, the exposed lower wiring 33 rises to form a raised portion 34, and a reaction generates a void 35 in the lower wiring 33, and as a result, There is a possibility that the wiring may be defective or the reliability may be reduced.

As a general problem associated with miniaturization of wiring, there is a problem that EM resistance is reduced due to an increase in current density.

By the way, for example, as shown in FIG. 4A, the EM of the linear wiring 40 is such that Al atoms move from the cathode side to the anode side according to the flow of electrons e ⁻ from the cathode side to the anode side. It progresses by doing. As a result, a dense region of Al atoms is formed on the anode side, and a sparse region of Al atoms is formed on the cathode side, and a concentration gradient of Al atoms occurs inside the wiring. Usually, in order to reduce the concentration gradient, as shown in FIG. 4B, the effect of diffusing Al atoms on the anode side to the cathode side (back-f
low effect) occurs in the wiring, and as a result, the progress of EM is suppressed. However, the wiring length (Blech length) at which this effect is effective is usually about 100 μm (longest) in a straight line under the actual device operating environment, whereas the actual LS
In many cases, the length of the straight line I is longer than the Blech length, so that an effective back-flow effect cannot be obtained. Therefore, it has been very difficult to suppress a decrease in EM resistance by the trench wiring technique.

An object of the present invention is to solve the above-mentioned problems of the prior art, and it is possible to eliminate voids in a lower wiring and to obtain a good electromigration (E)
M) An object of the present invention is to provide a multi-layer trench wiring having resistance.

[0010]

According to the present invention, by providing a barrier layer on a lower wiring, it is possible to suppress the formation of a bump and a void in the lower wiring, and to traverse the longitudinal direction of the lower wiring. The inventors have found that an effective back-flow effect can be realized by providing at least one slit-shaped barrier layer in the lower wiring so as to divide the lower wiring, and have completed the present invention.

That is, according to the present invention, a connection hole and an upper wiring are formed by burying a wiring material in a connection hole and an upper wiring groove formed in an interlayer insulating film on a lower wiring, respectively. In a multi-layer trench wiring having a structure in which a lower wiring and an upper wiring are connected via a hole, a first barrier layer is provided on a surface of the lower wiring on a connection hole side, and the lower wiring crosses a longitudinal direction of the lower wiring. To divide
A multilayer grooved wiring is provided, wherein at least one slit-shaped second barrier layer is provided in the lower wiring.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.

In the trench wiring according to the present invention, the connection hole and the upper wiring are respectively formed by burying a wiring material in the connection hole and the upper wiring groove formed in the interlayer insulating film on the lower wiring. It has a structure in which a lower wiring and an upper wiring are connected via the connection hole. A first barrier layer is provided on the surface of the lower wiring on the connection hole side, and at least one slit-shaped second barrier layer is provided on the lower wiring so as to cross the longitudinal direction of the lower wiring and divide the lower wiring. Is provided.

FIG. 1 shows an example of the trench wiring of the present invention. The trench wiring has a structure in which an upper wiring 2 is embedded in an interlayer insulating film 1 as shown in FIG.

When viewed from a cross section (AA cross section) along the longitudinal direction of the upper wiring 2 of FIG. 1A, FIG.
As shown in FIG. 1, a base layer 4 and a lower wiring 5 are formed on an interlayer insulating film 3, a first barrier layer 6 is formed on the lower wiring 5, and a longitudinal direction (arrow) of the lower wiring 5 is crossed. A slit-shaped second barrier layer 7 reaching the underlayer 4 is formed so as to divide the lower wiring 5, and further, the upper wiring 2 is formed.
And the lower wiring 5 are connected to each other via a base layer 8 and a connection hole 9. Here, FIG. 1C shows a case where the trench wiring is viewed from a BB section including the connection hole 9 in FIG.
FIG. 1D shows a case when viewed from a CC section including the slit-shaped second barrier layer 7 in FIG.

The underlayers 4 and 8 can be omitted in some cases.

As described above, the first wiring is formed on the lower wiring 5.
By providing the barrier layer, it is possible to suppress the protrusion and the generation of voids in the lower wiring 5, and at least one slit is formed in the lower wiring 5 so as to traverse the longitudinal direction of the lower wiring 5 and divide the lower wiring 5. Second barrier layer 7
Is provided, it is possible to obtain an effective back-flow effect.

In the present invention, the first barrier layer 6 and the second barrier layer 6
It is preferable that the barrier layers 7 are each independently formed of a high melting point metal or alloy layer, a high melting point metal nitride layer, or a laminate thereof. As such a high melting point metal, W,
Ta, Ti and the like can be mentioned. In particular, W is preferable because the first barrier layer 6 and the second barrier layer 7 can be simultaneously formed by the selective CVD method.

The thickness of the first barrier layer 6 is determined by the thickness of the connection hole 9.
Is etched when forming the first layer on the interlayer insulating film 1,
The thickness is set to at least 80 nm so that a part of the barrier layer 6 remains on the lower wiring 5. On the other hand, the upper limit of the thickness of the first barrier layer 6 is preferably 100 nm or less because the total thickness of the wiring increases even if the layer thickness is excessively increased, and the wiring aberration increases. .

If the width of the lower wiring 5 in the longitudinal direction (the division width of the lower wiring 5) of the second barrier layer 7 is too small, it becomes difficult to bury the wiring, and if it is too wide, the wiring resistance increases. 0.3 μm, more preferably 0.15-0.
25 μm.

The second barrier layer 7 has a back-fl
In order to efficiently realize the ow effect, it is preferable that the lower layer wiring 5 is provided so as to be perpendicular to the longitudinal direction of the lower layer wiring 5 and to vertically divide the lower layer wiring 5.

When the trench wiring of the present invention has a plurality of second barrier layers 7, the pitch between the second barrier layers 7 is 100 μm or less. Effective back-flow if it is wider than this
This is because the effect cannot be obtained.

In the trench wiring according to the present invention, components other than the above-mentioned first barrier layer 6 and second barrier layer 7, for example, lower wiring 5, interlayer insulating film 1, underlying layers 4 and 8, upper wiring 2 , The connection hole 9 and the like are not particularly limited.
I and the like used in high-density multilayer wiring boards such as I can be adopted.

For example, the lower wiring 5, the upper wiring 2, and the connection hole 9 are made of Al, Al--Cu, Al--Si, Al--Si--
Al alloys such as Cu and Al-Ge, Ag, Cu, Cu-Z
It can be formed by forming a wiring material such as r by a sputtering method or the like.

The upper wiring 2 and the connection hole 9 are preferably formed by embedding a wiring material into the connection hole and the upper wiring groove, respectively, by a reflow method, a high-pressure reflow method or a high-temperature sputtering method.

As the interlayer insulating films 1 and 3, for example, plasma CVD TEOS-SiO ₂ , O ₃ -TE
An insulating film made of an OS or the like can be used.

As the underlayers 4 and 8, W, Ta, Ti
Such as a high melting point metal having a melting point of 1500 ° C. or more or an alloy thereof, or a nitride thereof (for example, TiN, WN, Ti
WN). Also,
A laminate structure of two or more of these can be used.

Next, an example of a method for manufacturing a trench wiring according to the present invention will be described below with reference to FIG.

First, after an interlayer insulating film 3 is formed on a silicon substrate which has been subjected to LSI processing, a groove 3a for a lower wiring is formed (FIG. 2A).

Next, after the interlayer insulating film 3 is subjected to a heat treatment to remove moisture and gas, an underlayer 4 made of Ti / TiN or the like is formed.
Is formed by a DC magnetron sputtering method or the like, and then a lower wiring material 5a such as Al-Cu is formed (FIG. 2).
(B)).

Next, the lower-layer wiring material 5a is heated and reflowed (high-pressure reflow is also possible) and buried in the lower-layer wiring groove 3a (FIG. 2C).

The underlying layer 4 on the interlayer insulating film 3 and the lower wiring material 5a are removed by a CMP method or the like to form the lower wiring 5 (FIG. 2D).

Next, a slit 7a for a second barrier layer is formed in a vertical direction so as to cross the longitudinal direction of the lower layer wiring 5 at right angles by using a known photography technique and an etching technique (FIG. 2). (E1) Top view in the longitudinal direction of the lower wiring 5, FIG. 2 (e2) Cross sectional view in the longitudinal direction (DD) of the lower wiring 5).

Next, the slit 7 is formed by a selective CVD method or the like.
a, while embedding a barrier material, for example, W in the lower wiring 5
A barrier material is formed thereon (FIG. 2 (f1), a longitudinal sectional view of the lower wiring 5), and FIG. 2 (f2), a sectional view taken along line EE. Thereby, the first barrier layer 6 and the second barrier layer 7 are simultaneously formed.

Next, an interlayer insulating film 1 is formed on the entire surface of the first barrier layer 6, and a connection hole 9a and an upper wiring groove 2a are formed by using a known photographic technique and an etching technique. (FIG. 2 (g)). At this time, the connection hole 9a
It is preferable to stop the etching in the middle of the first barrier layer 6 so that the lower wiring 5 is not exposed at the bottom of the substrate.

Next, after the interlayer insulating film 1 is subjected to a heat treatment to remove moisture and gas, an underlying layer 8 made of Ti / TiN or the like is formed.
Is formed by a DC magnetron sputtering method or the like, then an upper wiring material such as AlCu is formed, and the upper wiring material is heated and reflowed under high pressure to be embedded in the connection hole 9a and the upper wiring groove 2a. Further, an underlayer 8 on the interlayer insulating film 1
And the upper wiring material are removed by a CMP method or the like. Thereby, the multilayer grooved wiring shown in FIG. 1 is obtained.

The diameter and depth of the connection hole 9 are not particularly limited as long as the first barrier layer 6 remains at the bottom of the connection hole 9.
Although it can be appropriately set according to the use of the groove wiring, the process of filling the connection holes 9, and the like, it is usually preferable that the diameter of the connection holes 9 is 300 to 500 nm and the depth is 600 to 1000 nm.

In the trench wiring of the present invention manufactured as described above, since the first barrier layer 6 is provided on the lower wiring 5, the protrusion of the lower wiring 5 and the generation of voids are suppressed. Further, since at least one slit-shaped second barrier layer 7 is provided in the lower wiring 5 so as to cross the longitudinal direction of the lower wiring 5 and divide the lower wiring 5, an effective back-flow effect can be obtained. Can be.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.

Example 1 (1) A groove for a lower wiring layer (with a groove width of 0.1 mm) was formed in an interlayer insulating film (SiO ₂ ) on a substrate which had been subjected to ordinary LSI processing by using a known lithography technique and etching technique. 5 μm;
A groove depth of 0.5 μm was formed (FIG. 2A).

Next, a preheat treatment (gas heating method from the back surface of the substrate) was performed under the following conditions to remove moisture and gas in the interlayer insulating film.

Preheating conditions Temperature: 500 ° C. Time: 1 minute Gas: Ar Backside gas pressure: 1000 Pa

(2) Next, by a DC magnetron sputtering method, the underlayer (TiN 50 nm / T
i20 nm), and a lower wiring material layer (Al-C
u1.5 μm) (FIG. 2B).

Ti film formation conditions DC power: 6 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film formation temperature: 200 ° C.

TiN film forming conditions DC power: 12 kW Process gas: Ar / N ₂ = 20/70 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C.

Al-Cu film forming conditions DC power: 15 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C.

(3) Next, the lower wiring material layer was buried in the lower wiring groove under the following reflow conditions (FIG. 2).
(C)). In this case, heating was performed by a gas heating method from the back surface of the substrate.

Reflow conditions Temperature: 500 ° C. Time: 1 minute Gas: Ar Backside gas pressure: 1000 Pa

The embedding was possible under the following high-pressure reflow conditions instead of the above-mentioned reflow conditions.

High pressure reflow conditions Process gas: Ar pressure: 70 Mpa Reflow time: 1 minute Substrate temperature: 450 ° C.

(4) Next, unnecessary underlayers and lower wiring material layers on the interlayer insulating film were removed under the following CMP conditions (FIG. 2D).

CMP conditions Polishing pressure: 100 g / cm ² Number of revolutions: Surface plate 30 rpm / polishing head 30 rpm Polishing pad: SUBAIV (trade name, manufactured by RODEL) Slurry: NH ₄ OH base (containing formed silica) Flow rate: 100 cc / Min Temperature: 25-30 ° C

(5) Next, using a well-known photographic technique and an etching technique, a slit (width 0.2 μm) for the second barrier layer is vertically set so as to cross the longitudinal direction of the lower wiring at right angles. , Depth 0.5μm, length 0.5μ
m) at intervals of 100 μm (FIG. 2 (e1) Longitudinal top view of lower wiring, FIG. 2 (e2) Longer wiring of lower wiring
(DD) sectional view).

(6) Next, under the following selective CVD conditions,
While burying W in the slit, 100 W
The film was formed to have a thickness of nm (FIG. 2 (f1), lower-layer wiring longitudinal sectional view, FIG. 2 (f2), EE sectional view). Thereby, a first barrier layer and a second barrier layer were formed.

Selective CVD Conditions Gas: WF ₆ / SH ₄ / H ₂ / Ar = 10/7/100 /
10sccm Temperature: 260 ° C Pressure: 30Pa

(7) Next, TEOS-SiO is used as an interlayer insulating film over the entire surface of the first barrier layer by a plasma CVD method.
₂ was deposited to a thickness of 600 nm, and was further preheated under the following conditions to form a connection hole and an upper wiring groove by using a known photographic technique and an etching technique (FIG. 2 (g)). .

Preheating conditions Temperature: 500 ° C. Time: 1 minute Gas: Ar Backside gas pressure: 1000 Pa

(8) Next, by a DC magnetron sputtering method, the underlayer (TiN 50 nm thick /
Ti 20 nm thick) and further upper wiring material layer (Al
-Cu 1.5 μm thick).

Ti film formation conditions DC power: 6 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film formation temperature: 200 ° C.

TiN film forming conditions DC power: 12 kW Process gas: Ar / N ₂ = 20/70 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C.

Al-Cu film forming conditions DC power: 15 kW Process gas: Ar 100 sccm Pressure: 0.4 Pa Film forming temperature: 200 ° C.

Next, the upper wiring material is heated and reflowed under the following high-pressure reflow conditions so as to fill the connection hole and the upper wiring groove. It was removed under the following CMP conditions. This allows
The groove wiring of FIG. 1 was obtained.

High pressure reflow conditions Process gas: Ar pressure: 70 Mpa Reflow time: 1 minute Substrate temperature: 450 ° C.

CMP conditions Polishing pressure: 100 g / cm ² Number of revolutions: surface plate 30 rpm / polishing head 30 rpm Polishing pad: SUBAIV (trade name, manufactured by RODEL) Slurry: NH ₄ OH base (containing formed silica) Flow rate: 100 cc / Min Temperature: 25-30 ° C

The state of connection between the lower wiring and the upper wiring of the multilayer groove wiring thus obtained was observed by SEM.
No bump was observed at the bottom of the connection hole, no void was observed in the lower wiring layer, and the lower wiring and the upper wiring were well connected to each other by the connection hole. In addition, it exhibited excellent EM resistance.

[0066]

According to the present invention, it is possible to provide a multilayer grooved wiring having no void in the lower wiring and having good electromigration (EM) resistance.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a groove wiring according to the present invention (FIG.
(B) AA cross-sectional perspective view, (c) BB cross-sectional view, and (d) CC cross-sectional view.

FIG. 2 is a manufacturing process diagram of the trench wiring of the present invention.

FIG. 3 is an explanatory view of a problem of a conventional trench wiring.

FIG. 4 is an explanatory diagram of a problem of a conventional trench wiring.

[Explanation of symbols]

1,3 ... interlayer insulating film, 2 ... upper wiring, 4,8 ... underlayer,
5 lower wiring, 6 first barrier layer, 7 second barrier layer,
9 Connection hole

Claims (9)

[Claims] A connection hole and an upper wiring are respectively formed by embedding a wiring material in a connection hole and an upper wiring groove formed in an interlayer insulating film on a lower wiring, and the connection hole and the upper wiring are formed through the connection hole. In a multi-layer trench wiring having a structure in which a lower wiring and an upper wiring are connected, a first wiring is provided on a surface of the lower wiring on a connection hole side.
A multilayer groove provided with a barrier layer, and provided with at least one slit-like second barrier layer in the lower wiring so as to cross the longitudinal direction of the lower wiring and divide the lower wiring. wiring. 2. The multilayer trench wiring according to claim 1, wherein the first barrier layer and the second barrier layer are formed of a refractory metal or alloy layer, a refractory metal nitride layer, or a laminate thereof. 3. The multilayer trench wiring according to claim 2, wherein the refractory metal is W, Ta or Ti. 4. The multilayer trench wiring according to claim 3, wherein the first barrier layer and the second barrier layer are W. 5. The multilayer trench wiring according to claim 1, wherein the first barrier layer has a layer thickness of at least 80 nm. 6. The multilayer trench wiring according to claim 1, wherein the width of the second barrier layer in the longitudinal direction of the lower wiring is 0.1 to 0.3 μm. 7. When a plurality of second barrier layers are provided, a pitch between the second barrier layers is 100 μm or less.
7. The multilayer grooved wiring according to any one of claims 6 to 6. 8. The method according to claim 1, wherein the first barrier layer and the second barrier layer are formed simultaneously by a selective CVD method.
8. The multilayer grooved wiring according to any one of 7. 9. The connection hole and the upper wiring are formed by embedding a wiring material into the connection hole and the upper wiring groove, respectively, by a reflow method, a high-pressure reflow method or a high-temperature sputtering method. 9. The multilayer grooved wiring according to any one of 8.