JPH10335258A - Method of forming insulation layer on silicide layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming an insulation layer on a silicide layer, suppressing the insulation layer from peeling in a semiconductor integrated circuit device. SOLUTION: This method comprises forming a conductive layer 18 as a wiring on a first insulation film 11, doping this layer 18 with an impurity to form a silicide layer 19 on the upper part of the conductive layer 18, patterning the conductive layer 18 and the silicide layer 19 to form emitter electrodes, annealing the silicide layer 19, chemically etching it to remove the oxide film, forming and annealing a second insulation layer 20 on the top of the silicide layer 19, forming a third insulation layer 21 on the upper part of the second insulation layer 20 and annealing the third insulation layer 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating layer on a silicide layer, and more particularly to a method for removing an oxide film containing impurities on a silicide layer by chemical etching and releasing stress of the silicide layer by annealing. The present invention relates to a method for forming an insulating layer on a layer without peeling.

[0002]

2. Description of the Related Art In a semiconductor integrated device composed of a bipolar transistor, a MOS transistor and the like,
Polysilicon is used as an electrode or a wiring layer. However, although polysilicon has conductive properties,
Due to the high resistance, they may not be suitable especially as conductive materials for ultra-high-speed semiconductor integrated devices.

For this reason, a configuration using a polycide layer in which a silicide layer is formed on polysilicon as an electrode or a wiring layer has been widely applied. For example, FIG.
In the semiconductor integrated device shown in FIG. 1, an insulating film 30 is formed on a surface of a semiconductor substrate 1 on which an element isolation insulating film 2 is formed.
Further, a polysilicon layer 4 is laminated thereon as a wiring layer. In order to reduce wiring resistance, a polycide layer in which a silicide layer 5 is formed on the polysilicon layer 4 is formed.

[0004]

However, an insulating layer 6 is formed directly on the polycide (polysilicon + silicide) layer, and furthermore, RTA for activating impurities in the substrate and flattening of the device structure are performed. BPS for the purpose of
When a high-temperature heat treatment is performed by reflowing the G layer 7, the insulating layer 6 and the BPSG layer 7 may be separated from the polycide layer. In particular, when the dopant in the polysilicon is arsenic, the occurrence of such peeling becomes remarkable. As a result, if the insulating layer 6 is peeled off in the manufacturing process, there arises a problem that it is impossible to fabricate the device and a problem that it causes dust.

[0005] The cause of the above-mentioned peeling is as follows.
At the interface between the polycide layers 4 and 5 and the insulating layer 6, there is a thin oxide film 8 on which impurities implanted into polysilicon are deposited, so that the adhesion between the thin oxide film 8 and the insulating layer 6 is poor. Also, a change in stress of polycide due to high-temperature heat treatment is considered.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and provides a method of forming an insulating layer capable of suppressing the occurrence of peeling of an insulating layer on a silicide layer in a semiconductor integrated device. The purpose is to do.

[0007]

According to a first aspect of the present invention, there is provided a method of forming an insulating layer on a silicide layer, comprising the steps of: forming a first insulating film or a semiconductor substrate on a semiconductor integrated device; Forming a conductive layer as a wiring on the first insulating film including: doping the conductive layer with an impurity; forming a silicide layer on the conductive layer; and forming the conductive layer and the silicide layer on the first insulating film. Patterning; annealing the silicide layer; chemically etching the silicide layer; forming a second insulating layer on the silicide layer and the first insulating film; It is constituted by combining the step of annealing the layer.

According to the above-described structure, the change in the stress of the silicide due to the annealing of the silicide layer and the removal of the oxide film by the chemical etching improve the bondability between the polycide layer and the second insulating layer.

According to the method of forming an insulating layer on a silicide layer according to a second aspect of the present invention, a conductive layer is formed as a wiring on a first insulating film or a first insulating film including a semiconductor substrate in a semiconductor integrated device. Doping the conductive layer with impurities, forming a silicide layer on the conductive layer, chemically etching the silicide layer, and forming a second insulating layer on the silicide layer Performing the step of: patterning the second insulating layer, the conductive layer, and the silicide layer; annealing the silicide layer; and forming a third insulating layer on the first insulating film and the second insulating layer. And a step of annealing the third insulating layer.

[0010] According to the above configuration, the bonding between the polycide layer and the second insulating layer is improved by suppressing the change in stress of the silicide by annealing the silicide layer and removing the oxide film by the chemical etching.

Alternatively, the method of forming an insulating layer on a silicide layer according to claim 3 of the present invention is the same as that of claim 1 or 2 except that the conductive layer is made of polysilicon.
The bonding property between the conductive layer and the insulating layer using an electrode / wiring material that is easy to process is improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 4 of the present invention, when the impurity is arsenic ion in the structure of claim 1 or 2, a relatively easy implantation technique is used. Can improve the bonding property between the conductive layer and the insulating layer.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 5 of the present invention, when the impurity is boron ions in the structure of claim 1 or 2,
Even with a configuration using a relatively easy implantation technique, it is possible to improve the bonding between the conductive layer and the insulating layer.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 6 of the present invention, when the silicide layer is made of tungsten silicide, the tungsten-based silicide layer is used. With this configuration, the bonding between the conductive layer and the insulating layer can be improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 7 of the present invention, if the silicide layer is made of titanium silicide in the constitution of claim 1 or 2, a titanium silicide layer is formed. With this configuration, the bonding between the conductive layer and the insulating layer can be improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 8 of the present invention, when the silicide layer is made of cobalt silicide according to the constitution of claim 1 or 2, a cobalt silicide layer is formed. With this configuration, the bonding between the conductive layer and the insulating layer can be improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 9 of the present invention, when the chemical etching is performed by hydrofluoric acid, It is possible to remove the oxide film with less amount.

Alternatively, the method for forming an insulating layer on a silicide layer according to claim 10 of the present invention is the same as that of claim 1 or 2, wherein the second insulating layer is an oxide layer.
With the configuration using the oxide layer, the bonding between the conductive layer and the insulating layer is improved.

Alternatively, the method for forming an insulating layer on a silicide layer according to claim 11 of the present invention is the same as that of claim 1 or 2, except that the second insulating layer is a nitride layer.
With the configuration using the nitride layer, the joining property between the conductive layer and the insulating layer is improved.

Alternatively, the method of forming an insulating layer on a silicide layer according to claim 12 of the present invention is the same as that of claim 1 or 2 except that the second insulating layer is a composite layer including an oxide layer. Also, in the configuration of the composite layer including the oxide layer, the bonding property between the conductive layer and the insulating layer is improved.

Alternatively, the method of forming an insulating layer on a silicide layer according to claim 13 of the present invention is the same as that of claim 1 or 2, wherein the second insulating layer is a composite layer including a nitride layer. In addition, even in the configuration of the composite layer including the nitride layer, the bonding property between the conductive layer and the insulating layer can be improved.

Alternatively, the method for forming an insulating layer on a silicide layer according to claim 14 of the present invention is the same as that of claim 1 or 2 except that the third insulating layer is an oxide layer.
With the configuration using the oxide layer, the bonding between the conductive layer and the insulating layer is improved.

Alternatively, the method for forming an insulating layer on a silicide layer according to claim 15 of the present invention is the same as that of claim 1 or 2 except that the third insulating layer is a nitride layer.
With the configuration using the nitride layer, the joining property between the conductive layer and the insulating layer is improved.

Alternatively, the method for forming an insulating layer on a silicide layer according to claim 16 of the present invention is the same as that of claim 1 or 2, wherein the third insulating layer is a composite layer including an oxide layer. Also, in the configuration of the composite layer including the oxide layer, the bonding property between the conductive layer and the insulating layer is improved.

Alternatively, the method of forming an insulating layer on a silicide layer according to claim 17 of the present invention is the same as that of claim 1 or 2, wherein the third insulating layer is a composite layer including a nitride layer. Also, in the configuration of the composite layer including the nitride layer, the joining property between the conductive layer and the insulating layer is improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 18 of the present invention, when the semiconductor integrated device is a bipolar transistor according to the structure of claims 1 to 17, the method uses a bipolar transistor. With respect to the structure, the bonding property between the conductive layer and the insulating layer is improved.

Alternatively, in the method of forming an insulating layer on a silicide layer according to claim 19 of the present invention, when the semiconductor integrated device is configured as a MOS transistor according to any one of claims 1 to 17, Also in the configuration using a transistor, the bonding between the conductive layer and the insulating layer is improved.

Alternatively, a method of forming an insulating layer on a silicide layer according to claim 20 of the present invention is the same as the structure of claims 1 to 17 except that the semiconductor integrated device is a bipolar analog / digital coexisting integrated device. In this case, the junction between the conductive layer and the insulating layer is also improved in the bipolar analog / digital coexistence integrated device.

[0029]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The embodiment described below is a part of a preferred embodiment of the present invention,
Although various limitations that are preferable in terms of the technical configuration are given, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description.

FIG. 1 is a schematic sectional view of a bipolar transistor integrated device BT according to an embodiment of the method for forming an insulating layer on a silicide layer according to the present invention. The structure of the bipolar transistor shown in FIG. 1 has an SST (Super S) characteristic especially in the base-emitter formation technology.
An element structure referred to as an "elf-aligned transistor", which can achieve device miniaturization and improvement in high-speed performance.

In the method of forming an insulating layer on a silicide layer according to the present invention, an epitaxial silicon layer 3 is formed after forming a buried layer 9 for reducing collector resistance in a semiconductor substrate 1. Thereafter, a known method such as L
The element isolation insulating film 2 is formed by OCOS.

Next, a plug 1 serving as a collector lead-out portion
0 is formed by ion implantation. Next, a first insulating film 11 is formed on the entire surface of the substrate, and a portion for forming a base and an emitter is opened by dry etching.

The polysilicon layer 14 serving as a base electrode is
It is formed by a CVD method. The graft base layer is formed by diffusion of boron from the polysilicon layer 14 by a heat treatment in a subsequent step.

Thereafter, an oxide film 16 is formed by a CVD method. Oxide film 16 is for insulating polysilicon 18 and silicide layer 19 described later. Next, an emitter contact portion is formed by patterning.

Next, a collector low resistance layer 12 is formed in the epitaxial silicon layer 3 by deep ion implantation, and a base layer 13 is formed by shallow ion implantation.

After that, the base electrode 14 and the oxide film 16 are patterned. Next, a sidewall 17 is formed in the emitter contact portion. Then, polysilicon 18
Is formed by a CVD method, then impurities (for example, arsenic) are ion-implanted, and then a silicide layer 19 is formed by a CVD method. As the silicide layer 19, tungsten silicide, titanium silicide, cobalt silicide, or the like can be used.

Next, the polysilicon 18, the silicide layer 1
9 is patterned to form an emitter electrode. Thereafter, in order to release the stress of the silicide layer 19, annealing is performed, for example, in a nitrogen atmosphere at 800 degrees Celsius for 10 minutes.

Next, the thin oxide film formed on the silicide layer 19 is removed by chemical etching using, for example, hydrofluoric acid.

Next, a second insulating layer 20 is formed by a CVD method. The second insulating layer 20 includes an oxide layer or a nitride layer,
In addition, a composite layer including an oxide layer or a nitride layer is applied. Then, in order to activate the impurities in the substrate,
Annealing is performed, for example, at 1050 degrees Celsius in a nitrogen atmosphere.
Perform for seconds. At this time, since the emitter electrode has been subjected to the annealing (at 800 degrees Celsius for 10 minutes) and the chemical etching, the second insulating layer 20 does not peel off.

Next, a third insulating layer 21 is formed by a CVD method. The third insulating layer 21 includes an oxide layer or a nitride layer,
In addition, a composite layer including an oxide layer or a nitride layer is applied. Thereafter, annealing is performed, for example, in a nitrogen atmosphere at 90 degrees Celsius.
The planarization is performed by performing the process at 0 degrees for 10 minutes. At this time, the above-mentioned annealing (10 degrees at 800 degrees Celsius) is applied to the emitter electrode.
Minute) and the chemical etching, the third
The insulating layer 21 does not peel off. Thus, the step of forming the insulating layer on the silicide layer is completed.

FIG. 2 is a sectional view of a wiring using a polysilicon film and a silicide layer. The element isolation insulating film 2 is formed by a known method. After that, the insulating layer 22 is formed by a CVD method. Next, a polysilicon layer 23 serving as a wiring layer is formed by CVD.
Then, arsenic is ion-implanted, and then a silicide layer 24 is formed by a CVD method.

Next, the thin oxide film formed on the silicide layer 24 is chemically etched using, for example, hydrofluoric acid. Next, an insulating layer 25 is formed on the silicide layer 24. After that, the insulating layer 25, the silicide layer 24, and the polysilicon layer 23 are patterned.

Next, in order to release the stress of the silicide layer 24, annealing is performed, for example, in a nitrogen atmosphere at 800 ° C.
Perform for 10 minutes in degrees.

Next, an insulating layer 26 is formed by a CVD method. Thereafter, in order to activate impurities in the polysilicon, annealing is performed at, for example, 1050 degrees Celsius in a nitrogen atmosphere for 10 seconds. At this time, the annealing (8 degrees Celsius) is applied to the wiring layer.
(At 100 degrees for 10 minutes), the insulating layer 25 is not peeled off because the chemical etching is performed.

Next, an insulating layer 27 is formed by a CVD method, and thereafter annealing is performed in a nitrogen atmosphere at 900 ° C., for example.
The surface is planarized by performing the process for 10 minutes. At this time, since the annealing (800 degrees Celsius for 10 minutes) and the chemical etching are performed on the wiring layer, the insulating layer 25 does not peel off.

In the above embodiment, the semiconductor integrated device is a bipolar transistor. However, the method of forming an insulating layer on a silicide layer according to the present invention is not limited to this. Also, the present invention can be applied to a bipolar / analog / digital coexistence type semiconductor integrated device.

[0047]

As described in detail above, the method for forming an insulating layer on a silicide layer according to the present invention is to remove the oxide film on the silicide by chemical etching and to release the stress of the silicide by annealing. In addition, it is possible to eliminate a residual oxide film having poor adhesion to the insulating layer formed on the silicide layer, and improve the bonding between the silicide layer and the insulating layer.

Therefore, it is possible to eliminate the peeling of the insulating layer on the silicide layer, and it is possible to manufacture a device having a structure using the insulating layer on the silicide layer. Specifically, a gate electrode and a wiring of a MOS transistor and an emitter electrode of a bipolar transistor can be formed.
Further, by eliminating the peeling of the insulating layer on the silicide layer in this manner, there is an effect that the cause of dust can be eliminated.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor integrated device according to an embodiment of a method for forming an insulating layer on a silicide layer according to the present invention.

FIG. 2 is a schematic cross-sectional view of a semiconductor integrated device according to one embodiment of a method for forming an insulating layer on a silicide layer according to the present invention.

FIG. 3 is a schematic cross-sectional view of a semiconductor integrated device according to a conventional method for forming an insulating layer immediately above a silicide layer.

[Explanation of symbols]

BT: Bipolar transistor integrated device, 1: silicon substrate, 2: element isolation insulating film, 3: epitaxial layer, 9
... buried layer, 10 ... collector lead layer, 11 ... first insulating film,
12: collector low resistance layer, 13: base layer, 14: base electrode, 15: graft base layer, 16: oxide film, 17
... Emitter contact portion side wall, 18... Polysilicon layer, 19... Silicide layer, 20.
1. Third insulating layer.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/73

Claims (20)

[Claims] 1. A step of forming a conductive layer as a wiring on a first insulating film or a first insulating film including a semiconductor substrate in a semiconductor integrated device, a step of doping the conductive layer with an impurity, and an upper part of the conductive layer. Forming a silicide layer on the substrate, patterning the conductive layer and the silicide layer, annealing the silicide layer, chemically etching the silicide layer, the silicide layer and the first insulating film. Forming an insulating layer on the silicide layer, wherein the step of forming the second insulating layer on the top of the substrate and the step of annealing the second insulating layer are combined. 2. A step of forming a conductive layer as a wiring on a first insulating film or a first insulating film including a semiconductor substrate in a semiconductor integrated device, a step of doping the conductive layer with an impurity, and an upper part of the conductive layer. Forming a silicide layer on the substrate, chemically etching the silicide layer, forming a second insulating layer on the silicide layer, and patterning the second insulating layer, the conductive layer, and the silicide layer. Performing a step of annealing the silicide layer, the first insulating film and the second
Forming a third insulating layer on top of the insulating layer;
A method for forming an insulating layer on a silicide layer, the method further comprising a step of annealing the insulating layer. 3. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the conductive layer is polysilicon. 4. The method according to claim 1, wherein the impurity is arsenic ion. 5. The method for forming an insulating layer on a silicide layer according to claim 1 or 2, wherein the impurities are boron ions. 6. A method for forming an insulating layer on a silicide layer, wherein the silicide layer according to claim 1 or 2 is tungsten silicide. 7. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the silicide layer is titanium silicide. 8. A method for forming an insulating layer on a silicide layer, wherein the silicide layer according to claim 1 or 2 is cobalt silicide. 9. A method for forming an insulating layer on a silicide layer, wherein the chemical etching according to claim 1 or 2 is etching with hydrofluoric acid. 10. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the second insulating layer is an oxide layer. 11. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the second insulating layer is a nitride layer. 12. The method for forming an insulating layer on a silicide layer according to claim 1 or 2, wherein the second insulating layer is a composite layer including an oxide layer. 13. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the second insulating layer is a composite layer including a nitride layer. 14. The method according to claim 1, wherein the third insulating layer is an oxide layer. 15. The method for forming an insulating layer on a silicide layer according to claim 1, wherein the third insulating layer is a nitride layer. 16. The method according to claim 1, wherein the third insulating layer is a composite layer including an oxide layer. 17. The method of forming an insulating layer on a silicide layer according to claim 1, wherein the third insulating layer 3 is a composite layer including a nitride layer. 18. The method for forming an insulating layer on a silicide layer according to claim 1, wherein said semiconductor integrated device is a bipolar transistor. 19. The method of forming an insulating layer on a silicide layer according to claim 1, wherein said semiconductor integrated device is a MOS transistor. 20. The method for forming an insulating layer on a silicide layer according to claim 1, wherein said semiconductor integrated device is a bipolar analog / digital coexisting integrated device.