JPH08264651A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing a semiconductor device in which the contact resistance of a diffused layer with a conductor layer in contact with the layer can be sufficiently reduced. CONSTITUTION: After a contact hole 6 is formed on an n<+> type diffused layer 4 formed in a p-type Si substrate 1, a TiN film 7 is deposited on the entire surface. Then, Si or As ion is, for example, implanted from above the film 7. The energy of the ion implantation is so selected that the peak of the distribution of the implanted Si or As is disposed near the boundary between the film 7 and the layer 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is suitable for application to, for example, manufacturing a semiconductor device using a barrier metal for a wiring contact portion.

[0002]

2. Description of the Related Art In a semiconductor device, when aluminum (Al) wiring is connected to a diffusion layer, titanium nitride (T) is formed on the diffusion layer in order to improve heat resistance of a wiring contact portion.
iN) film or the like is formed as a barrier metal, and the TiN
Al wiring is often contacted with the film.

This technique will be described in detail by taking a method of manufacturing a MOS type semiconductor device as an example.

That is, first, as shown in FIG. 3A, p
A field insulating film 102 made of a silicon dioxide (SiO ₂ ) film is formed by selectively thermally oxidizing the surface of a type silicon (Si) substrate 101 to perform element isolation, and then surrounded by the field insulating film 102. A gate insulating film 103 made of a SiO ₂ film is formed on the surface of the formed active region by a thermal oxidation method.

Next, the p-type S is formed through the gate insulating film 103.
An n-type impurity for forming a source region and a drain region, for example, arsenic (As) is ion-implanted into the i-substrate 101, and a heat treatment for electrically activating the implanted impurity is performed, as shown in FIG. 3B. An n ⁺ type diffusion layer 104 which constitutes a source region or a drain region is formed.

Next, as shown in FIG. 3C, for example, CVD
Interlayer insulating film 1 made of, for example, a SiO ₂ film by the method
After depositing 05, a predetermined portion of the interlayer insulating film 105 and the gate insulating film 103 on the n ⁺ type diffusion layer 104 is removed by etching to form a contact hole 106.

Next, as shown in FIG. 3D, after a TiN film 107 is deposited on the entire surface by, for example, a sputtering method, the TiN film 107 is patterned into a predetermined shape by etching.

After that, the desired MOS type semiconductor device is completed through necessary processes such as formation of Al wiring (not shown) contacting the TiN film 107.

[0009]

However, in the above-described conventional method for manufacturing a MOS semiconductor device, the n ⁺ type diffusion layer 10 inside the contact hole 106 is deposited before the TiN film 107 is deposited by the sputtering method.
The natural oxide film (not shown) formed on the surface of No. 4 is TiN
By that exists between the membrane 107 and the n ⁺ -type diffusion layer 104, there is a contact resistance between the TiN film 107 and the n ⁺ -type diffusion layer 104 impossible to sufficiently low.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of sufficiently lowering the contact resistance between a diffusion layer and a conductor layer made of titanium nitride or the like that contacts the diffusion layer.

[0011]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a conductor layer is brought into contact with a diffusion layer provided in a semiconductor substrate. After the layer is formed, the element is ion-implanted from above the conductor layer.

In the present invention, it is preferable that the peak of the distribution of the ion-implanted element is located near the interface between the diffusion layer and the conductor layer. This can be easily achieved by proper choice of ion implantation energy.

In one embodiment of the present invention, the element to be ion-implanted is a neutral element with respect to the semiconductor substrate, that is, an n-type impurity (donor impurity) and a p-type impurity (acceptor impurity) with respect to the semiconductor substrate. It is an element that does not become.

In another embodiment of the present invention, the ion-implanting element is an impurity of the same conductivity type as the diffusion layer, that is, an n-type impurity when the diffusion layer is n-type and a p-type impurity when the diffusion layer is n-type. Is a p-type impurity.

In the present invention, the semiconductor substrate is typically made of silicon. The conductor layer is typically made of a refractory metal compound such as TiN, Co ₂ N or TiC, but may be made of Al or polycrystalline Si.

In the present invention, the semiconductor device may be of various types, but an example thereof is a complete CMOS static RAM.

[0017]

According to the method of manufacturing a semiconductor device of the present invention configured as described above, since the element is ion-implanted from above the conductor layer, the surface of the diffusion layer is formed before the conductor layer is formed. It is possible to destroy the native oxide film formed on the. In particular, by selecting the energy of ion implantation so that the peak of the distribution of the ion-implanted element is located near the interface between the diffusion layer and the conductor layer, the natural oxide film formed on the surface of the diffusion layer. Can be effectively destroyed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are designated by the same reference numerals.

FIG. 1 shows a MOS according to the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device.

In the method of manufacturing a MOS type semiconductor device according to the first embodiment, first, as shown in FIG. 1A, for example, a surface of a p-type Si substrate 1 is selectively thermally oxidized to form a SiO ₂ film. After forming the field insulating film 2 and performing element isolation, the gate insulating film 3 made of a SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 2 by the thermal oxidation method. Here, the film thickness of the field insulating film 2 is 400 nm, and the film thickness of the gate insulating film 3 is 16 nm, for example.

Next, an n-type impurity for forming a source region and a drain region, for example, As is ion-implanted into the p-type Si substrate 1 through the gate insulating film 3 and further electrically activated for the implantation impurity. By performing heat treatment, as shown in FIG. 1B, an n ⁺ type diffusion layer 4 forming a source region or a drain region is formed. Here, the As ion implantation conditions are, for example, energy of 50 keV and dose of 3 × 10 ^15.
cm ^-2 . Further, the heat treatment for electrically activating the implanted impurities is performed by, for example, RTA (Rapid Thermal Annealing).
Method at 1050 ° C. for 10 seconds in a nitrogen (N ₂ ) atmosphere.

Next, as shown in FIG. 1C, for example, CVD
Interlayer insulating film 5 made of, for example, a SiO ₂ film by the
After depositing, a predetermined portion of the interlayer insulating film 5 and the gate insulating film 3 on the n ⁺ type diffusion layer 4 is removed by etching to form a contact hole 6. Here, the film thickness of the interlayer insulating film 5 is, for example, 200 nm.

Next, as shown in FIG. 1D, a TiN film 7 is deposited on the entire surface by, for example, a sputtering method, and then Si, for example, is ion-implanted from above the TiN film 7 (in FIG. 1D, the implanted Si is injected). Is indicated by a black circle). This S
The ion implantation energy of i is selected so that the distribution peak of the implanted Si is located near the interface between the TiN film 7 and the n ⁺ type diffusion layer 4. The conditions of this Si ion implantation are, for example, when the thickness of the TiN film 7 is 70 nm, the implantation energy is 80 keV and the dose amount is 3 × 10 ¹⁵ cm ⁻² . This Si ion implantation destroys the natural oxide film (not shown) formed on the surface of the n ⁺ type diffusion layer 4 before depositing the TiN film 7 by the sputtering method.
After this, for example, by the RTA method in an N ₂ atmosphere, 1000
Heat treatment is performed at a temperature of 10 ° C. for 10 seconds to recover the damage caused by the ion implantation and to sufficiently make contact between the TiN film 7 and the n ⁺ type diffusion layer 4.

Next, as shown in FIG. 1E, the TiN film 7 is patterned into a predetermined shape by etching.

Next, the desired MOS type semiconductor device is completed through necessary processes such as formation of Al wiring (not shown) contacting the TiN film 7.

As described above, according to the first embodiment,
After depositing the TiN film 7 on the entire surface,
^Since Si was ion-implanted at an energy such that the distribution peak was located near the interface with the ⁺ type diffusion layer 4, it was formed on the surface of the n ⁺ type diffusion layer 4 before the TiN film 7 was deposited. The natural oxide film can be destroyed effectively and surely. As a result, the TiN film 7 and the n ⁺ type diffusion layer 4 are formed.
Since it can be directly contacted with each other, the contact resistance between the TiN film 7 and the n ⁺ type diffusion layer 4 can be made sufficiently lower than in the conventional case.

FIG. 2 shows a MOS according to the second embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device.

In the method of manufacturing the MOS type semiconductor device according to the second embodiment, first, as shown in FIG. 2A, p
After the field insulating film 2 is selectively formed on the surface of the type Si substrate 1 to perform element isolation, the field insulating film 2 is formed.
A gate insulating film 3 is formed on the surface of the active region surrounded by.

Next, as shown in FIG. 2B, for example, As is ion-implanted into the p-type Si substrate 1 through the gate insulating film 3 and then heat-treated to form a source region or a drain region. ^{The +} type diffusion layer 4 is formed. The process up to this point is the same as the method of manufacturing the MOS semiconductor device according to the first embodiment.

Next, as shown in FIG. 2C, for example, CVD
After depositing an interlayer insulating film 5 made of a SiO ₂ film on the entire surface by the method, predetermined portions of the interlayer insulating film 5, the field insulating film 2 and the gate insulating film 3 at one end of the n ⁺ type diffusion layer 4 are removed by etching. Then, the contact hole 6 is formed. That is, the field insulating film 2 and the gate insulating film 3
A contact hole 6 is formed so as to extend over. At this point, inside the contact hole 6, n ⁺
There is a region where the mold diffusion layer 4 is not formed.

Next, as shown in FIG. 2D, after a TiN film 7 is deposited on the entire surface by, for example, a sputtering method, an n-type impurity such as As is ion-implanted from above the TiN film 7 (in FIG. 2D, The injected As is indicated by a black circle). The energy of the ion implantation of As is selected so that the peak of the distribution of the implanted As is located near the interface between the TiN film 7 and the n ⁺ type diffusion layer 4. The conditions for the ion implantation of As are, for example, when the thickness of the TiN film 7 is 70 nm, the implantation energy is 170 keV, and the dose amount is 3 × 1.
It is 0 ¹⁵ cm ^-2 . By the ion implantation of As, Ti
Before the N film 7 is deposited, the natural oxide film (not shown) formed on the surface of the n ⁺ type diffusion layer 4 is destroyed, and the n ⁺ type diffusion layer 4 spreads throughout the contact hole 6. It is formed. After that, heat treatment is performed, for example, by RTA in an N ₂ atmosphere at 1000 ° C. for 10 seconds. As a result, the damage caused by the ion implantation is recovered and the TiN film 7 and the n ⁺ type diffusion layer 4 are sufficiently contacted with each other.

Next, as shown in FIG. 2E, the TiN film 7 is patterned into a predetermined shape by etching.

Next, the desired MOS type semiconductor device is completed through necessary processes such as formation of Al wiring (not shown) that contacts the TiN film 7.

As described above, according to this second embodiment,
After depositing the TiN film 7 on the entire surface,
^Since As was ion-implanted at the energy at which the peak of the distribution was located near the interface with the ⁺ type diffusion layer 4, it was formed on the surface of the n ⁺ type diffusion layer 4 before depositing the TiN film 7. The natural oxide film can be destroyed effectively and surely. As a result, the TiN film 7 and the n ⁺ type diffusion layer 4 are formed.
The contact resistance with can be made sufficiently lower than the conventional one. Immediately after the contact hole 6 was formed, there was a region in which the n ⁺ type diffusion layer 4 was not formed.
By ion-implanting As into the substrate 4, the n ⁺ -type diffusion layer 4 is formed in the entire inside of the contact hole 6, so that the TiN film 7 and the n ⁺ -type diffusion layer 4 are also formed.
The contact resistance with can be reduced.

The manufacturing method of the MOS type semiconductor device according to the second embodiment is, for example, a complete CMOS static R
It can be applied to a case where a TiN film or the like is connected to a diffusion layer in a Si substrate in local interconnection in AM. In this case, by using a neutral element (for example, Si) as an element to be ion-implanted in order to destroy the natural oxide film formed on the diffusion layer, the TiN film and the n ⁺
Contact resistance of the contact portion with the type diffusion layer, and
Both the contact resistance of the contact portion between the TiN film and the p ⁺ type diffusion layer can be made sufficiently low.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above-described first and second embodiments, ion implantation for destroying the natural oxide film formed on the surface of the n ⁺ type diffusion layer 4 is performed after the TiN film 7 is deposited. Although this is performed before patterning, this ion implantation may be performed after patterning the TiN film 7.

Further, although the case where the present invention is applied to the manufacture of the MOS type semiconductor device has been described in the above-mentioned first and second embodiments, the present invention is applied to, for example, a bipolar type semiconductor device or a bipolar-CMOS. It is also possible to apply the present invention to manufacturing of semiconductor devices.

[0039]

As described above, according to the present invention, after the conductor layer is formed on the diffusion layer, the element is ion-implanted from above the conductor layer. Before forming the layer, the natural oxide film formed on the surface of the diffusion layer can be destroyed, whereby the contact resistance between the conductor layer made of titanium nitride or the like and the diffusion layer can be made sufficiently low.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a MOS semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view for illustrating the method for manufacturing a MOS semiconductor device according to the second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a MOS semiconductor device.

[Explanation of symbols]

1 p-type Si substrate 2 field insulating film 3 gate insulating film 4 n ⁺ type diffusion layer 5 interlayer insulating film 6 contact hole 7 TiN film

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device in which a conductor layer is brought into contact with a diffusion layer provided in a semiconductor substrate, wherein the conductor layer is formed on the diffusion layer, and then an element is applied from above the conductor layer. A method for manufacturing a semiconductor device, characterized in that the ion implantation is performed. 2. The manufacturing of a semiconductor device according to claim 1, wherein the peak of the distribution of the ion-implanted element is located substantially in the vicinity of the interface between the diffusion layer and the conductor layer. Method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the element is an element that is neutral to the semiconductor substrate. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the element is an impurity having the same conductivity type as the diffusion layer. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor layer is made of a refractory metal compound. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal compound is titanium nitride. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a complete CMOS static RAM.