JPH10321977A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH10321977A
JPH10321977A JP13344897A JP13344897A JPH10321977A JP H10321977 A JPH10321977 A JP H10321977A JP 13344897 A JP13344897 A JP 13344897A JP 13344897 A JP13344897 A JP 13344897A JP H10321977 A JPH10321977 A JP H10321977A
Authority
JP
Japan
Prior art keywords
multilayer printed
wiring board
printed wiring
connection reliability
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13344897A
Other languages
Japanese (ja)
Inventor
Hiroshi Kawazoe
宏 河添
義之 ▲つる▼
Yoshiyuki Tsuru
Masao Sugano
雅雄 菅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP13344897A priority Critical patent/JPH10321977A/en
Publication of JPH10321977A publication Critical patent/JPH10321977A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a interlayer connection element superior in connection reliability even in the case of a high aspect ratio by forming a via having a major and minor axes in plan view for electrically connecting between conductors partitioned by an insulation layer. SOLUTION: A via having a minor and major axes 12, 13 is formed by a laser or a drill and pref. moving it during boring of the via, thus forming an elongated circular hole. The major axis 13 is pref. longer than the distance between conductors to be connected; if not longer, the connection reliability will deteriorate. If it is an elongated circular hole of 0.1 mm×0.3 mm, a conductive resin cam be filled enough. This is effective for the case of the connection reliability reduced owing to the increase of the aspect ratio. In application to a multilayer printed board having vias at a high density, interlayer connection electrodes can be independently mounted.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層プリント配線
板に関する。
[0001] The present invention relates to a multilayer printed wiring board.

【0002】[0002]

【従来の技術】通常、バイアホールは、導体間にある絶
縁材を除去する工程と、絶縁材を除去した箇所に導体を
形成する工程と、によって形成される。絶縁材を除去す
る方法としては、薬液による化学的除去(エッチン
グ)、プラズマやレーザーによる熱的、物理的除去(ア
ブレーション)、ドリルによる機械的除去等があり、導
体を形成する方法としては、めっきや蒸着等による金属
の堆積、導電性樹脂液( インク) の充填・硬化等が
ある。
2. Description of the Related Art Generally, a via hole is formed by a step of removing an insulating material between conductors and a step of forming a conductor at a position where the insulating material is removed. Methods for removing the insulating material include chemical removal (etching) using a chemical solution, thermal and physical removal (ablation) using plasma or laser, and mechanical removal using a drill. The method for forming a conductor is plating. And deposition of metal by vapor deposition, filling and curing of conductive resin liquid (ink).

【0003】近年、携帯電話やハンドヘルドパーソナル
コンピュータ等の携帯機器の要求が高く、電子機器が小
型化されているため、それに用いられる各種電子部品の
サイズも益々小型化されている。ところで、多層プリン
ト配線板には、絶縁層に隔てられた導体間を接続するバ
イアホールが設けられているが、多層プリント配線板に
も小型化が要求されているので、バイアホールについて
も小型化をしなければならなくなってきている。
In recent years, there has been a high demand for portable devices such as cellular phones and hand-held personal computers, and the size of electronic devices has been reduced, so that the sizes of various electronic components used in the devices have been increasingly reduced. By the way, a multilayer printed wiring board is provided with a via hole for connecting between conductors separated by an insulating layer, but the multilayer printed wiring board is also required to be downsized. You have to do it.

【0004】[0004]

【発明が解決しようとする課題】ところで、バイアホー
ルの小型化には、バイアホールのアスペクト比(穴の深
さ/穴の直径の比)が大きくなるに従い、その接続信頼
性が著しく低下するという課題がある。すなわち、アス
ペクト比が大きくなるに従い、絶縁材を除去するための
エッチング液、導体を形成するためのめっき液、あるい
は導電性樹脂液などの液体の表面張力や粘性のため、絶
縁材を除去した箇所の開口面積が小さくなるほど内部へ
の浸透や除去部内での流動、拡散が起こりにくく、形成
したバイアホールにはボイド等の不良部が生じ、その結
果、接続信頼性が低下するのである。
In order to reduce the size of a via hole, as the aspect ratio of the via hole (the ratio of the depth of the hole to the diameter of the hole) increases, the connection reliability of the via hole significantly decreases. There are issues. That is, as the aspect ratio increases, the portion where the insulating material has been removed due to the surface tension or viscosity of an etching solution for removing the insulating material, a plating solution for forming a conductor, or a liquid such as a conductive resin solution. As the opening area of the hole becomes smaller, penetration into the inside and flow and diffusion in the removed portion are less likely to occur, and a defective portion such as a void is formed in the formed via hole, and as a result, connection reliability is reduced.

【0005】本発明は、接続信頼性に優れたバイアホー
ルを有する多層プリント配線板を提供することを目的と
する。
An object of the present invention is to provide a multilayer printed wiring board having via holes having excellent connection reliability.

【0006】[0006]

【課題を解決するための手段】本発明の多層プリント配
線板は、絶縁層で隔てられた導体間を電気的に接続する
ためのバイアホールの平面形状が、図1に示すように、
短軸12と長軸13とを持つ形状であることを特徴とす
る。
According to the multilayer printed wiring board of the present invention, the planar shape of the via hole for electrically connecting the conductors separated by the insulating layer is as shown in FIG.
It has a shape having a short axis 12 and a long axis 13.

【0007】本発明者らは、鋭意検討の結果、長軸の長
さは、接続する導体間の距離より長いことが好ましく、
接続する導体間の距離と同じか短いと、接続信頼性が充
分でないという知見を得ている。
As a result of intensive studies, the present inventors have found that the length of the long axis is preferably longer than the distance between the conductors to be connected.
It has been found that if the distance between the connecting conductors is the same or shorter, the connection reliability is not sufficient.

【0008】[0008]

【発明の実施の形態】短軸と長軸とを持つ形状は、図1
に示すように、楕円や長円があるが、加工の容易さから
長円であることが好ましい。本発明のバイアホールの形
成方法は、レーザやドリル穴あけによって行うことがで
き、通常の穴あけを、穴加工しながら一方向に移動する
という動作を追加するのみでよい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A shape having a short axis and a long axis is shown in FIG.
As shown in FIG. 5, there are ellipses and ellipses, but the ellipses are preferred from the viewpoint of ease of processing. The via hole forming method of the present invention can be performed by laser or drilling, and only needs to add an operation of moving a normal hole in one direction while drilling.

【0009】バイアホールに導体を形成する方法は、通
常のバイアホールに導体を形成する方法を使用すること
ができ、本発明の形状においては、小さいバイアホール
に、導電性樹脂を充填して使用することも可能で、穴径
が0.1mm程度では、従来、導電性樹脂が充分に充填
できなかったが、0.1mm×0.3mmの長円である
と、充分に充填でき、接続信頼性も高い。導電性樹脂を
充填する方法としては、スクリーン法、カーテンコート
法及びディップ法等が使用できる。導電性樹脂は、樹脂
に導電性粒子を含んだものであり、その樹脂には、多層
プリント板の絶縁層を形成する樹脂と同等の特性を有す
るものが好ましく、例えば、エポキシ樹脂、ポリイミド
樹脂等が好ましい。導電性粒子としては、金属粒子や樹
脂粒子表面に金属薄膜をコートしたもの等を使用するこ
とができる。
As a method of forming a conductor in a via hole, an ordinary method of forming a conductor in a via hole can be used. In the shape of the present invention, a small via hole is filled with a conductive resin. Conventionally, the conductive resin could not be filled sufficiently with a hole diameter of about 0.1 mm, but it could be filled sufficiently with a 0.1 mm × 0.3 mm ellipse, and the connection reliability was low. The nature is also high. As a method for filling the conductive resin, a screen method, a curtain coating method, a dipping method, or the like can be used. The conductive resin is a resin containing conductive particles, and the resin preferably has the same characteristics as the resin forming the insulating layer of the multilayer printed board, such as an epoxy resin and a polyimide resin. Is preferred. As the conductive particles, metal particles or resin particles whose surfaces are coated with a metal thin film can be used.

【0010】多層プリント板は、層数、絶縁材の種類、
配線パターン等の仕様を規定するものではなく、任意の
回路を実装してよい。導体層の材質は任意でよい。絶縁
材は多層プリント板用として一般に入手できる樹脂を使
用することができる。エポキシ樹脂、ポリイミド樹脂、
BT(ビスマレイミドトリアジン)樹脂、フェノール樹
脂等が好適である。これらの絶縁材料は、誘電率や誘電
正接等の電気的特性、熱伝導率、熱容量等の熱的特性、
或いは曲げ特性や熱膨張係数等の機械的特性等の諸特性
をコントロールする各種の添加剤や強化材を含んでよ
い。また、絶縁材の種類、そこに内含する添加剤や強化
材の種類は、層毎で設定できる。
[0010] The multilayer printed board has a number of layers, a kind of insulating material,
It does not specify the specifications of the wiring pattern and the like, and may mount an arbitrary circuit. The material of the conductor layer may be arbitrary. As the insulating material, a resin generally available for a multilayer printed board can be used. Epoxy resin, polyimide resin,
BT (bismaleimide triazine) resin, phenol resin and the like are preferable. These insulating materials have electrical properties such as permittivity and dielectric tangent, thermal conductivity, thermal properties such as heat capacity,
Alternatively, it may contain various additives and reinforcing materials for controlling various properties such as bending properties and mechanical properties such as a coefficient of thermal expansion. Further, the type of the insulating material and the types of the additives and the reinforcing materials contained therein can be set for each layer.

【0011】[0011]

【実施例】本発明の実施例は、図3(g)に示すよう
に、表面導体層2cとして下地銅9μm+めっき銅12
μm+はんだめっき15μmを両面に設け、絶縁層1a
として100μmの厚さのエポキシ接着フィルムAS−
3000(日立化成工業株式会社製、商品名)と、その
内側に内層導体層2aとして下地銅18μm+めっき銅
40μmと、その内側に絶縁層1bとして厚さ0.2m
mのガラス布エポキシ樹脂プリプレグを2層設け、その
間に形成したワイヤ布線層3を設け、その2層のプリプ
レグの内側に内層導体層2bとして下地銅35μmと、
その内側に内層絶縁層1cとして厚さ0.4mmのガラ
ス布エポキシプリプレグと、その内側に内層導体層2b
として銅35μmと、さらに内側に絶縁層1bとして厚
さ0.2mmのガラス布エポキシプリプレグを2層設
け、その間に形成したワイヤ布線層3を設け、その2層
のプリプレグの内側に内層導体層2bとして銅35μm
と、その内側に内層絶縁層1dとして厚さ0.6mmの
ガラス布エポキシプリプレグと、その内側に内層導体層
2bとして銅35μmと、そしてその内側にコア絶縁層
1eとして厚さ0.8mmのガラスエポキシ絶縁層を設
け、コア絶縁層を中心としてそれぞれの厚さを上下対象
の厚さとし、バイアホールとして表面導体層2cと内層
導体層2aとを接続するインタースティシャルバイアホ
ール(以下、IVHという。)4、内層導体層2bとワ
イヤ布線層の間を全て貫くスルーホール5、上記各導体
層間を絶縁する絶縁層を有する、厚さ約5mmのマルチ
ワイヤ配線板(日立化成工業株式会社製、商品名)であ
る。ワイヤ布線層3は、直径0.1mmの絶縁被覆され
た銅ワイヤ7を、0HAW−1IMW(日立電線株式会
社製、商品名)で形成した。この多層プリント配線板の
製造方法は、通常の多層プリント配線板を製造する方法
で、厚さ0.8mmのガラス布エポキシ絶縁層と35μ
mの銅箔からなる両面銅張り積層板であるMCL−E−
67(日立化成工業株式会社製、商品名)の両面の銅箔
の不要な箇所をエッチング除去して内層配線板とし、そ
の両面に厚さ0.6mmのガラス布エポキシプリプレグ
と35μmの銅箔を順に重ね、2.5MPa、180
℃、60分の条件で加熱加圧して積層一体化し、積層板
とし、その積層板の銅箔の不要な箇所をエッチング除去
し、ガラス布エポキシ樹脂製のアンダーレイをラミネー
トし、その上に絶縁被覆電線を数値制御布線機で接着固
定し、その上にガラス布エポキシ樹脂製オーバーレイを
重ね、さらに35μmの銅箔を重ね、2MPa、180
℃、60分の条件で加熱加圧して積層一体化し、その銅
箔の不要な箇所をエッチング除去し、その上に厚さ0.
4mmのガラス布エポキシプリプレグと35μmの銅箔
を重ね、2MPa、180℃、60分の条件で加熱加圧
して積層一体化し、その銅箔の不要な箇所をエッチング
除去し、ガラス布エポキシ樹脂製のアンダーレイをラミ
ネートし、その上に絶縁被覆電線を数値制御布線機で接
着固定し、その上にガラス布エポキシ樹脂製オーバーレ
イを重ね、さらに18μmの銅箔を重ね、2MPa、1
80℃、60分の条件で加熱加圧して積層一体化し、ス
ルーホール5となる穴をあけ、無電解めっきを厚さ40
μmに行って、その銅箔とめっき銅の不要な箇所をエッ
チング除去し、その上に厚さ100μmのエポキシ接着
フィルムであるAS−3000(日立化成工業株式会社
製、商品名)と、9μmの銅箔に70μmの銅箔を離型
処理して張り合わせた9μmキャリア付極薄銅箔(古河
電気工業株式会社製、商品名)を重ね、2MPa、18
0℃、60分の条件で加熱加圧して積層一体化し、キャ
リアを機械的に剥離し、その上に、エッチングレジスト
用ドライフィルム6をラミネートし、フォトマスクを介
して、露光・現像して、エッチングレジスト8を形成
し、9μmの銅箔がバイアホールを形成するときの絶縁
材料のエッチング用のマスクとなるように、短軸0.0
5mm、長軸0.15mmの長円の形状に銅箔をエッチ
ング除去して開口部9を形成し、その開口部9の上から
レーザを出力20.5kV、ショット数6、アパーチャ
径0.3mmの条件で照射し、次に、無電解めっきを行っ
て12μmの厚さに析出させ、次にめっきレジスト10
を形成してエッチングレジストの形状にはんだめっきを
行って、めっきレジスト10を剥離除去し、はんだめっ
きの間に露出した銅をエッチング除去し、210℃、7
0秒の条件ではんだをフュージングして16層のマルチ
ワイヤ配線板とした。IVH4の内壁導体にボイド等の
欠陥は無く、熱衝撃試験(MIL−STD−202,m
ethod107)に対しては、200サイクルで抵抗
上昇率は10%未満であった。スルーホール5は絶縁層
をドリルで除去し、銅めっきで内壁導体を形成した。層
方向の断面形状は直径が0.4mmの円である。その内
部は樹脂で充填した。
FIG. 3 (g) shows an embodiment of the present invention, in which 9 μm of base copper +
μm + 15 μm solder plating on both sides, insulation layer 1a
100 µm thick epoxy adhesive film AS-
3000 (trade name, manufactured by Hitachi Chemical Co., Ltd.), 18 μm of base copper + 40 μm of plated copper as an inner conductor layer 2 a inside thereof, and 0.2 m thick as an insulating layer 1 b inside thereof
m, two layers of glass cloth epoxy resin prepreg are provided, a wire wiring layer 3 formed therebetween is provided, and an inner conductor layer 2b is formed on the inside of the two layers of prepreg as base copper 35 μm;
A glass cloth epoxy prepreg having a thickness of 0.4 mm as an inner insulating layer 1c on the inside thereof, and an inner conductor layer 2b on the inner side thereof.
35 μm of copper, and two layers of a glass cloth epoxy prepreg having a thickness of 0.2 mm as an insulating layer 1 b are further provided inside, and a wire wiring layer 3 formed therebetween is provided, and an inner conductor layer is provided inside the two layers of prepreg. Copper 35 μm as 2b
Inside, a 0.6 mm thick glass cloth epoxy prepreg as an inner insulating layer 1d, 35 μm copper as an inner conductive layer 2b inside thereof, and 0.8 mm thick glass as a core insulating layer 1e inside thereof. An epoxy insulating layer is provided, the thicknesses of the core insulating layer are centered on the core insulating layer, and an interstitial via hole (hereinafter, referred to as IVH) connecting the surface conductor layer 2c and the inner conductor layer 2a is formed as a via hole. 4) a multi-wire wiring board having a thickness of about 5 mm (a product of Hitachi Chemical Co., Ltd.) having a through hole 5 penetrating all between the inner conductor layer 2b and the wiring layer, and an insulating layer for insulating the above conductor layers. (Product name). The wire wiring layer 3 was formed of a copper wire 7 having a diameter of 0.1 mm and coated with an insulating material, using 0HAW-1IMW (trade name, manufactured by Hitachi Cable, Ltd.). The method of manufacturing this multilayer printed wiring board is a method of manufacturing an ordinary multilayer printed wiring board.
MCL-E- which is a double-sided copper-clad laminate made of copper foil
Unnecessary portions of copper foil on both sides of 67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) are etched and removed to form an inner-layer wiring board, and a 0.6 mm thick glass cloth epoxy prepreg and 35 μm copper foil are provided on both sides. 2.5MPa, 180
Laminate and unify by heating and pressurizing at 60 ° C for 60 minutes to form a laminated board. Unnecessary portions of copper foil on the laminated board are removed by etching, and an underlay made of glass cloth epoxy resin is laminated, and insulation is performed on it. The coated electric wire was bonded and fixed by a numerically controlled wiring machine, an overlay made of glass cloth epoxy resin was overlaid thereon, and a copper foil of 35 μm was further overlaid thereon, and 2 MPa, 180
The laminate was integrated by heating and pressing at 60 ° C. for 60 minutes, unnecessary portions of the copper foil were removed by etching, and a thickness of 0.1 mm was formed thereon.
A 4 mm glass cloth epoxy prepreg and a 35 μm copper foil are superimposed and laminated under heat and pressure under the conditions of 2 MPa, 180 ° C., and 60 minutes, and unnecessary portions of the copper foil are removed by etching. An underlay was laminated, an insulated wire was bonded and fixed on the underlay with a numerical control wiring machine, a glass cloth epoxy resin overlay was further laminated thereon, and an 18 μm copper foil was further laminated thereon.
Laminate and unify by heating and pressing at 80 ° C for 60 minutes, make a hole to be a through hole 5, and apply electroless plating to a thickness of 40
μm, an unnecessary portion of the copper foil and plated copper is removed by etching, and AS-3000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is an epoxy adhesive film having a thickness of 100 μm, and 9 μm An ultra-thin copper foil with a 9 μm carrier (trade name, manufactured by Furukawa Electric Co., Ltd.) obtained by releasing a 70 μm copper foil onto a copper foil and laminating the same is superimposed on 2 MPa, 18
The carrier was mechanically peeled off by heating and pressing under the conditions of 0 ° C. and 60 minutes, the carrier was mechanically peeled off, and a dry film 6 for etching resist was laminated thereon, and exposed and developed through a photomask. An etching resist 8 is formed, and the short axis 0.0 is used so that a 9 μm copper foil serves as a mask for etching an insulating material when forming a via hole.
An opening 9 is formed by etching the copper foil into an elliptical shape of 5 mm and a major axis of 0.15 mm, and a laser is output from above the opening 9 with a laser output of 20.5 kV, 6 shots, and an aperture diameter of 0.3 mm. And then electroless plating is performed to deposit to a thickness of 12 μm.
Is formed, solder plating is performed on the shape of the etching resist, the plating resist 10 is peeled off and removed, and the copper exposed during the solder plating is removed by etching.
The solder was fused under the condition of 0 second to obtain a 16-layer multi-wire wiring board. There is no defect such as void in the inner wall conductor of IVH4, and thermal shock test (MIL-STD-202, m
For method 107), the resistance increase rate was less than 10% at 200 cycles. In the through hole 5, the insulating layer was removed by a drill, and the inner wall conductor was formed by copper plating. The cross-sectional shape in the layer direction is a circle having a diameter of 0.4 mm. The inside was filled with resin.

【0012】本発明のバイアホールは、複数の導体層を
有する任意の部品に適用できる。アスペクト比増大に伴
う接続信頼性低下が問題となる場合に有効であり、特に
バイアホールを高密度に配する多層プリント板に適用し
た場合、その効果は著しい。層間接続要素は、各々独立
して設置できる。その断面形状等も必要に応じた設計を
行って良い。本例では、サイズの微細化が必要であった
IVH4のみに本発明を適用した。面方向の断面形状を
短軸と長軸を有した長円とし、長軸長を0.15mmと
した。
The via hole of the present invention can be applied to any component having a plurality of conductor layers. This is effective when the decrease in connection reliability due to the increase in the aspect ratio becomes a problem. Especially when applied to a multilayer printed board in which via holes are densely arranged, the effect is remarkable. The interlayer connection elements can be installed independently of each other. The cross-sectional shape and the like may be designed as needed. In this example, the present invention was applied only to IVH4, which required miniaturization of the size. The cross-sectional shape in the plane direction was an ellipse having a short axis and a long axis, and the long axis length was 0.15 mm.

【0013】[0013]

【発明の効果】以上に説明したように、本発明によれ
ば、高いアスペクト比の場合でも、接続信頼性に優れた
層間接続要素を提供することができる。また、本発明の
多層プリント板によれば、端子密度が高く層間接続要素
の配設密度が高い場合でも、接続信頼性の低下を無くす
ことが可能となる。
As described above, according to the present invention, it is possible to provide an interlayer connection element having excellent connection reliability even in a high aspect ratio. Further, according to the multilayer printed board of the present invention, even when the terminal density is high and the arrangement density of the interlayer connection elements is high, it is possible to eliminate a decrease in connection reliability.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の構成を説明するための上面図である。FIG. 1 is a top view for explaining a configuration of the present invention.

【図2】本発明の一実施例を示す上面図である。FIG. 2 is a top view showing one embodiment of the present invention.

【図3】(a)〜(g)は、それぞれ本発明の一実施例
の製造法を説明するための各工程における断面図であ
り、(b)〜(f)は、要部断面図である。
FIGS. 3 (a) to 3 (g) are cross-sectional views in respective steps for explaining a manufacturing method according to one embodiment of the present invention, and FIGS. 3 (b) to 3 (f) are cross-sectional views of a main part. is there.

【符号の説明】[Explanation of symbols]

1a.接着シート 1b.ガラス布エポキシ樹脂プリプレグ 1c.プリプレグ 1d.プリプレグ 1e.コア絶縁層 2c.表面導体層 2a.内層導体層 2b.内層導体層 3.ワイヤ布線層 4.IVH 5.スルーホール 6.エッチングレジスト用ドライフィルム 7.銅ワイヤ 8.エッチングレジスト 9.開口部 10.めっきレジスト 12.短軸 13.長軸 1a. Adhesive sheet 1b. Glass cloth epoxy resin prepreg 1c. Prepreg 1d. Prepreg 1e. Core insulating layer 2c. Surface conductor layer 2a. Inner conductor layer 2b. 2. inner conductor layer Wire wiring layer 4. IVH5. Through hole 6. 6. Dry film for etching resist Copper wire 8. Etching resist 9. Opening 10. Plating resist 12. Short axis 13. Long axis

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】絶縁層で隔てられた導体間を電気的に接続
するためのバイアホールの平面形状が、短軸と長軸とを
持つ形状であることを特徴とする多層プリント配線板。
1. A multilayer printed wiring board, wherein a planar shape of a via hole for electrically connecting conductors separated by an insulating layer is a shape having a short axis and a long axis.
【請求項2】長軸の長さが、接続する導体間の距離より
長いことを特徴とする請求項1に記載の多層プリント配
線板。
2. The multilayer printed wiring board according to claim 1, wherein the length of the major axis is longer than the distance between the conductors to be connected.
【請求項3】短軸と長軸とを持つ形状が、長円であるこ
とを特徴とする請求項1または2に記載の多層プリント
配線板。
3. The multilayer printed wiring board according to claim 1, wherein the shape having a short axis and a long axis is an ellipse.
【請求項4】バイアホールが、導電性樹脂を充填されて
いることを特徴とする請求項1〜3のうちいずれかに記
載の多層プリント配線板。
4. The multilayer printed wiring board according to claim 1, wherein the via hole is filled with a conductive resin.
JP13344897A 1997-05-23 1997-05-23 Multilayer printed wiring board Pending JPH10321977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13344897A JPH10321977A (en) 1997-05-23 1997-05-23 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13344897A JPH10321977A (en) 1997-05-23 1997-05-23 Multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH10321977A true JPH10321977A (en) 1998-12-04

Family

ID=15105019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13344897A Pending JPH10321977A (en) 1997-05-23 1997-05-23 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH10321977A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004753A3 (en) * 1998-07-20 2002-09-19 Intel Corp Alignment of vias in circuit boards or similar structures
US6779262B1 (en) 1999-03-23 2004-08-24 Circuit Foil Luxembourg Trading Sarl Method for manufacturing a multilayer printed circuit board
US7102855B2 (en) * 2003-08-15 2006-09-05 Seagate Technology Llc Microelectronic device with closely spaced contact studs

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000004753A3 (en) * 1998-07-20 2002-09-19 Intel Corp Alignment of vias in circuit boards or similar structures
US6779262B1 (en) 1999-03-23 2004-08-24 Circuit Foil Luxembourg Trading Sarl Method for manufacturing a multilayer printed circuit board
EP1172025B2 (en) 1999-03-23 2006-04-26 Circuit Foil Luxembourg S.a.r.l. Method for manufacturing a multilayer printed circuit board and composite foil for use therein
KR100760432B1 (en) * 1999-03-23 2007-09-20 서키트 호일 룩셈부르크 트레이딩 에스.에이 알. 엘. Method for manufacturing a multilayer printed circuit board and composite foil for use therein
US7102855B2 (en) * 2003-08-15 2006-09-05 Seagate Technology Llc Microelectronic device with closely spaced contact studs

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