JPH10308090A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save power consumption and to improve computer speed in the case of refreshing of a DRAM by eliminating refresh operations in the memory area where zero clear processing is completed just before. SOLUTION: After completing the zero clear processing of the memory region where main memory 11 existent, the refresh executing flag corresponding to the memory address of this memory region installed in the memory table 17 is set to the invalid mode '0' so that refreshing is not executed even for the refresh request of this memory region. That is, since when the next memory access is the refresh request from the refresh timer 13, the refresh executing flag is in the invalid mode '0', the refresh executing flag is brought to the valid mode '1' and refreshing operation is omitted and the next operation is advanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device used for a main memory of an electronic computer, a frame memory of a printer, or the like.
ndom Access Memory).

[0002]

2. Description of the Related Art In recent years, as application software for handling images, sounds, and the like has been used more and more, main memories of electronic computers and their peripheral devices have been increasing in capacity. Such a memory has a large storage capacity,
DRAMs with a low manufacturing unit price per unit storage capacity are generally used. And, as is well known, in a DRAM, it is necessary to rewrite (hereinafter, referred to as "refresh") at regular intervals to hold internal data.

Conventionally, a refresh timer for periodically generating a refresh request signal has been prepared, and the DRAM has been refreshed in synchronization with the periodic refresh request signal from the refresh timer.

[0004]

However, it is desirable to omit refresh as much as possible from the viewpoint of improving the speed of the computer and reducing the power consumption. In particular, when dealing with a large-capacity memory, there is a problem that the operation of the circuit becomes unstable due to large power consumption, and it is desirable that refresh is not performed as much as possible.

In view of the fact that the number of pixels per screen can be set small in the case of an electronic still camera, Japanese Patent Application Laid-Open No. Hei 5-242671 only refreshes a row in the DRAM where an image area exists in the DRAM. A technique for reducing power consumption by a refresh operation has been disclosed.

On the other hand, a DRAM is used as a frame memory for image data of a printer or the like, for example, a PDL (Page Des
When used as an area for expanding data described in Cription Language), the area of the frame memory must be cleared to zero before expanding the image data. Therefore, when handling a large amount of data such as an image, the time required for clearing the memory becomes enormous.

If the memory area to be refreshed is the area which has just been read or written, the refresh operation can be omitted, and the memory refresh is replaced by zero clear processing. be able to.

However, in the prior art, an attempt is made to save power in refreshing the DRAM and to improve the speed of the computer by focusing on the point that the refresh operation can be omitted in the memory area where the zero clear processing has been performed immediately before. Technology did not exist.

Therefore, a first object of the present invention is to solve the above-mentioned problems and to focus on the point that the refresh operation can be omitted in a memory area where the zero-clear processing has been performed immediately before. It is intended to reduce the cost and improve the speed of the computer.

A second object of the present invention is to save power and improve the speed of a computer by omitting a refresh operation that is performed first after a zero clear process is performed.

A third object of the present invention is to save power and improve the speed of a computer by suspending a request for zero-clear processing and performing zero-clear processing at the first refresh operation after the suspension. is there.

A fourth object of the present invention is to facilitate memory access control and to simplify a DRAM control circuit.

A fifth object of the present invention is to enable a refresh method to be selected according to a situation.

A sixth object of the present invention is to ensure the reliability of data stored in a DRAM.

[0015]

According to a first aspect of the present invention, there is provided a memory device in which a memory area is formed of a DRAM, and the memory area is periodically refreshed to maintain data storage. Out of the system, a refresh management unit that replaces the refresh operation based on the first refresh request after the zero-clear processing request by performing the zero-clear processing based on the zero-clear processing request. It is a feature.

Therefore, the portion of the DRAM memory area for which the zero-clear processing request has been made can be replaced with a refresh operation based on the first refresh request after the zero-clear processing request by the zero-clear processing based on the zero-clear processing request. Therefore, unnecessary refresh operation can be omitted.

According to a second aspect of the present invention, the refresh management means performs first zero-clear processing on the memory area based on a zero-clear processing request from outside the system, and the zero-clear processing in the memory area. First memory address storing means for storing the memory address of the portion where the memory address is stored, and refresh omitting means for omitting the first refresh operation performed after the zero-clear processing on the memory area storing the memory address. It is characterized by having.

Therefore, a zero-clear processing is performed based on a zero-clear processing request from outside the system, and the memory address of the portion of the memory area subjected to the zero-clear processing is stored, and the stored memory address is displayed in the memory area indicated by the stored memory address. On the other hand, unnecessary refresh operation can be omitted by omitting the first refresh operation performed after the zero-clear processing.

According to a third aspect of the present invention, the refresh management means includes a zero clear suspending means for suspending a zero clear processing request from outside the memory area, and a memory address of the memory area in which the zero clear processing request is suspended. Second memory address storing means for storing, and second zero clear execution for performing a zero clear process in place of the refresh operation on the memory area in which the memory address is stored at the time of the first refresh operation after the suspension. Means.

Therefore, a request for zero clear processing from outside the system to the memory area is suspended, and the memory address of the part of the memory area in which the zero clear processing request is suspended is stored, and the first refresh operation performed after the suspension is performed. By performing zero-clear processing instead of the refresh operation on the memory area indicated by the stored memory address, unnecessary refresh operation can be omitted.

According to a fourth aspect of the present invention, the memory area is divided into a plurality of DRAM modules, and the refresh management means performs a refresh operation and a zero clear process in place of the refresh operation for each DRAM module. It is characterized by having.

Therefore, control such as refresh is performed by DRA
Since the control can be performed in units of M modules and control can be performed for each control signal given to each DRAM module, memory access control becomes easy and the control circuit of the DRAM can be simplified.

According to a fifth aspect of the present invention, the refresh operation is performed by the CAS before RA by the refresh management means.
It is characterized by being performed by an S refresh cycle.

Therefore, control such as refreshing is performed by CAS.
Since the refresh is performed in the before RAS refresh cycle, the refresh address can be made unnecessary.

According to a sixth aspect of the present invention, the refresh management means is a control signal indicating an address space, and
It is characterized by comprising a zero clear request judging means for judging a zero clear request by a device prepared separately from a memory address on a bus communicating with M.

Therefore, since the zero clear request is determined by the control signal indicating the address space prepared separately from the memory address on the bus, the zero clear request is determined as compared with the case where the bus is monitored to determine the zero clear request of a certain size. Can be simplified.

[0027] The invention according to claim 7 is characterized in that the refresh management means includes a selection means for selectively performing a zero-clear processing in place of the refresh operation based on a signal from outside the system. It is.

Therefore, it is possible to select a normal refresh operation, a substitute for the zero-clear processing, or a refresh method based on a signal from outside the system.

In a preferred embodiment of the present invention, the refresh management means includes a timer for counting an elapsed time after the zero clear processing, and the refresh operation is performed only when a refresh request signal is generated within a certain period from the zero clear request. Is omitted.

Therefore, the refresh operation is omitted only when the refresh request signal is generated within a certain period from the zero clear request, so that the refresh operation can be performed in an accurate time and the reliability of the data can be secured. .

According to a ninth aspect of the present invention, the refresh management means includes a period setting means for adjusting the size of a certain period counted from the zero clear request.

Therefore, the refresh operation can be omitted only when the refresh request signal is generated within a certain period from the zero clear request. In this case, the certain period can be made variable. The refresh operation can be performed, and data reliability can be ensured.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment of the Invention] FIG. 1 shows the overall configuration of an electronic computer system according to a first embodiment of the present invention.

As shown in FIG. 1, in this computer system, a main bus 2 is connected to a CPU 3, a memory device 1, and other I / O modules 4. The main bus 2 includes an address bus, a data bus, and a control bus.
Access to is made.

The main memory 11 is composed of a DRAM, and receives a RAS (row address strobe) signal and a RAS (row address strobe) signal sent from the memory controller 12 (refresh management means, first zero clear execution means, refresh omitting means). Read access, write access, and refresh are performed by a CAS (column address strobe) signal, a W (write) signal, and an OE (output enable) signal.

The refresh timer 13 periodically generates a refresh request, and
Requesting that the main memory 11 be refreshed. When the refresh operation is performed in the RAS-only refresh cycle, a row address to be refreshed in the refresh cycle is required, and therefore, the refresh address counter 14 is instructed to increment the address.

The memory controller 12 receives a memory read and memory write request from the main bus 2, and outputs a RAS signal to the main memory 11 and a CA signal.
Read access and write access of the main memory 11 are controlled by the S signal, the W signal, and the OE signal. At the same time, a control signal (SEL) for multiplexing the memory address is sent to the address generation circuit 15.
When a refresh request from the refresh timer 13 is detected, the RAS signal, the CAS signal, and the address signal are controlled to execute a refresh cycle of the main memory 11.
To select and output a memory address for refresh.

The refresh address counter 14
Generates a row address to be given to the main memory 11 when performing refresh by RAS only refresh. This row address becomes an address on the main memory 11 to be actually refreshed. And
In response to a refresh request from the refresh timer 13, the refresh address counter 14 is incremented, the row address of the refresh address given to the main memory 11 is changed, and the refresh is performed in order from the top address. When the refresh address has been counted up to the end of the main memory, the value of the refresh address counter 14 is returned to the start address.

The address generation circuit 15 receives a control signal (SE) from the memory controller 12 when a memory read or memory write from the main bus 2 is requested.
L), the access address is divided into a row address and a column address and applied to the main memory 11. Also, RA
At the time of S-only refresh, the row address created by the refresh address counter 14 is given to the main memory 11.

The zero-clear detection circuit 16 determines whether or not the access from the main bus 2 is a zero-clear request to any one of the memory areas of the main memory 11.

The memory table 17 (refresh management means, first memory address storage means) is a management table of a memory area which needs to be refreshed, and is divided into predetermined size units as shown in FIG. The memory area includes a memory address for displaying each memory area, and a refresh execution flag corresponding to each memory address. The refresh execution flag is indicated by 1 bit. For example, "0" indicates no refresh.
(Invalid mode) and “1” (valid mode) indicate that refresh is performed. When a zero-clear request is issued for one entire memory area and the zero-clear processing is completed, the refresh execution flag for the memory area is set to the invalid mode “0”, and thereafter, by referring to the memory table 17, the memory area 17 The next refresh operation is omitted. When a refresh request for the memory area is generated while the refresh execution flag is in the invalid mode “0”, the refresh execution flag is set to the valid mode “1”, and the next refresh request for the memory area is accepted.

When the memory device 1 is used as a frame memory of a printer in the above-described computer system,
The main memory 11 is configured as shown in FIG. For example, A
Assuming printing of a four-size 400 dpi monochrome image, a memory area required for a frame memory for developing the image requires approximately 2 MB. Further, in the case of a printer system, it is conceivable to have a plurality of image development memory areas in order to accept a plurality of print requests, and to simultaneously develop the images. It is necessary to manage the memory in these area units, and to perform the zero clear processing for each of these memory areas.

When n frame memories are prepared as shown in FIG. 3, a capacity of (n × 2) MB is required. Also,
In order to indicate whether or not refreshing is necessary for this frame (frame 0, frame 1,..., Frame n-1), as shown in FIG. Make it correspond. The presence or absence of a refresh operation for the memory area of each frame memory is indicated by a corresponding refresh execution flag.

Next, the operation of the above configuration will be described.

Reading and writing to the main memory 11 are performed by an AS (address strobe) signal and a DS (data
The process starts when the memory controller 12 detects a (strobe) signal. At this time, the address output on the main bus 2 is time-divided by a multiplexer built in the address generation circuit 15 and the divided row address and column address are sent to the main memory 11 in accordance with the RAS signal and the CAS signal. .

In the case of read access, when data on the main bus 2 becomes valid, and in the case of write access, when data is written to the main memory 11,
An ACK signal is output on the main bus 2 to notify an access source such as the CPU 3 that read / write access to the main memory 11 has been completed.

Further, since the main memory 11 is composed of a DRAM, refreshing is required after a certain period. Therefore, the refresh timer 13 internally waits for a refresh interval required by the DRAM, and outputs a refresh request to the memory controller 12 at regular intervals. By receiving this refresh request, the memory controller 1
2 controls the RAS, CAS, and row address as shown in the timing chart of FIG. 4, and performs a periodic refresh operation. When RAS-only refresh is performed, the row address to be refreshed needs to be incremented for each refresh operation, and the request is notified to the refresh address counter 14. Upon receiving the request, the refresh address counter 14 increments its own counter and changes the row address given to the main memory 11. In the example of FIG. 4, m, m +
Count up as 1, m + 2, m + 3,.

However, when receiving the refresh request, the memory controller 12 refers to the refresh execution flag on the memory table 17 corresponding to the memory address to be refreshed at the same time. For example, when the refresh execution flags for m + 1, m + 2, and m + 3 are in the valid mode “1”, a normal refresh operation is performed on the memory area indicated by the memory address as shown in FIG. When the refresh execution flag for m is in the invalid mode “0”, the refresh operation for that address is omitted as shown in FIG. 4, so that the operation immediately proceeds to the next operation.

When a memory read / memory write request and a refresh request overlap, the refresh operation has priority. That is, at the time of memory read and memory write, the memory controller 12 checks the refresh request from the refresh timer 13 and performs read and write access to the main memory 11 when there is no refresh request. If a refresh request has occurred,
Pending memory access from the main bus 2,
First, the main memory 11 is refreshed, and when the refresh operation is completed, the read and write accesses which have been pending are performed.

On the other hand, when the image data described in the PDL is expanded, it is necessary to clear the memory area to be expanded to zero beforehand and expand the image data in the memory area. At that time, a zero clear request is generated for the memory area for developing the image data, that is, for the memory area for one frame. One frame of the main memory 11 has a capacity of 2 MB as shown in FIG.
Zero clear processing is performed on the memory area of the MB.

Therefore, by performing zero-clear processing on the area of the frame memory, it is considered that the refresh operation is simultaneously performed on the memory area, and the processing of omitting the refresh operation is performed. Details of this processing will be described with reference to the flowchart of FIG. 5 for facilitating understanding.

That is, when a zero clear request is issued from the CPU 3 and other modules to a certain area, for example, a memory area for one frame, via the main bus 2, first, the request from the main bus 2 is sent to the zero clear detecting circuit 16. Is detected, and it is determined that this memory access is a zero clear request (step S1). This is when the zero-clear detection circuit 16 monitors the main bus 2 and detects when a zero-clear access of a certain size occurs, and notifies the memory table 17 of this.

Thereafter, when the zero clear processing of the memory area is completed (step S2), the corresponding refresh execution flag of the memory table 17 is set to the invalid mode "0" (step S3), and the subsequent refresh request of the memory area is performed. Even if refresh is not performed.

That is, when the next memory access is a refresh request from the refresh timer 13 (steps S1 and S4), the refresh execution flag of the memory table 17 is in the invalid mode "0". The execution flag is set to the valid mode "1", the refresh operation is omitted, and the operation proceeds to the next operation (steps S5 and S6). At this time, since the refresh execution flag is set to the valid mode "1", the refresh operation is performed at the next refresh request (steps S5 and S7). If the memory access is neither a zero clear access nor a refresh request, normal read and write accesses are performed (step S8).

[Second Embodiment of the Invention] An electronic computer system according to a second embodiment of the present invention has the following components except for the memory table 17, ie, the main memory 11,
Memory controller 12 (refresh management means, zero clear suspension means, second zero clear execution means), refresh timer 13, refresh address counter 1
4, the address generation circuit 15, the zero-clear detection circuit 16 and the like have the same configuration as that of the first embodiment shown in FIG. 1, so that the block diagram showing the overall configuration is omitted instead of FIG. A detailed description of each part common to the first embodiment will also be omitted.

Memory table 1 in this embodiment
7 is shown in FIG.

The memory table 17 (refresh management means, second memory address storage means) is a table for managing the presence / absence of a zero-clear request, and a memory area divided into a predetermined size unit has It comprises a memory address indicating a memory area, and a zero clear request flag corresponding to each of the memory addresses. The zero clear request flag is indicated by 1 bit, and indicates, for example, “0” (invalid mode) when there is no zero clear request and “1” (valid mode) when there is a zero clear request. FIG. 6 shows an example when a zero clear request is issued for frame 2.

Next, the operation will be described.

When receiving a refresh request from the refresh timer 13, the memory controller 12 refers to the memory table 17 and refers to a zero clear request flag corresponding to a memory address to be refreshed.

When the zero clear request flag is in the invalid mode “0”, the normal refresh operation is performed. When the zero clear request flag is in the valid mode “1”, the refresh operation is omitted and the zero clear processing is performed instead. As a result, when accessing a continuous memory area of a certain size, such as zero-clear access, the processing timing is changed to be performed at the time of the refresh operation, thereby omitting the actual refresh operation for the memory area. can do.

The processing in this case will be described with reference to the flowchart of FIG. 7 for easy understanding.

That is, when a zero clear request is issued from the CPU 3 and other modules to a certain area, for example, a memory area for one frame, via the main bus 2, first, the zero clear detecting circuit 16 detects the request from the main bus 2. Detected and determines that the current access is a zero clear request. This is because the zero-clear detection circuit 16 monitors the main bus 2 and detects when a zero-clear request of a certain size has occurred.
2 and the memory table 17.
The memory controller 12 suspends the zero clear request by this notification, sets the zero clear request flag for the memory area to the valid mode “1” in the memory table 17, and indicates that the zero clear request for the memory area is pending ( Step S
11, S12).

Thereafter, when a refresh request is output from the refresh timer 13, the refresh address counter 14 increments the address value and shifts to the RAS only refresh operation of the row address indicated by the refresh address counter 14.
At this time, with reference to the memory table 17, when the zero clear request flag of the memory area is in the invalid mode “0”, the normal refresh operation is performed (step S13,
S14, S15).

Conversely, when the zero clear request flag is in the valid mode "1", the normal refresh operation is omitted, and the pending zero clear processing is executed instead (steps S14 and S16). When the zero-clear processing is completed, the zero-clear request flag is set to the invalid mode “0” to indicate that there is no zero-clear request to the memory area (step S17). Thus, a normal refresh operation is performed at the next refresh request. If the memory access is neither a zero-clear request access nor a refresh request, normal read and write accesses are performed (step S18) [Third embodiment of the present invention] Third embodiment of the present invention The computer system according to the embodiment has a configuration as shown in FIG. 8 and does not include a refresh address counter 14 related to output of a row address in the memory device 1 and uses a CAS before RAS refresh cycle for refreshing. Except that the configuration of the main memory 11 and the memory table 17 (refresh management means) is different as described later.
(Refresh management means), refresh timer 13,
The address generation circuit 15, the zero-clear detection circuit 16, and the like have the same configuration as in the first embodiment, and a detailed description of each part common to the first embodiment will be omitted.

Generally, when configuring a large-capacity memory,
In many cases, a DRAM module equipped with a plurality of memory chips is used. Therefore, in this embodiment, FIG.
As shown in the figure, when a 4 MB DRAM module is used, one DRAM module corresponds to two frames.

Then, as shown in FIG. 10, each entry of the memory table 17 is set in DRAM module units,
A refresh execution flag is also provided for each DRAM module.

The refresh timer 13 periodically generates a refresh request, and
Of the main memory 11 is requested.

The address generating circuit 15 divides an access address into a row address and a column address by a control signal (SEL) from the memory controller 12 at the time of a memory read or memory write request from the main bus 2, and stores the access address in the main memory 11. give.

Next, the operation will be described.

In this embodiment, the above-described configuration allows zero clear processing for the main memory 11,
The refresh operation can be performed for each DRAM module.

That is, when a zero-clear request is issued from the CPU 3 and other modules to the memory area of the DRAM module (two frames in this example) via the main bus 2, the request from the main bus 2 is first cleared to zero. The detection circuit 16 detects and determines that this memory access is a zero clear request. This is because the zero clear detection circuit 16 monitors the main bus 2 and
This is performed by detecting the occurrence of a zero-clear access of a certain size and notifying the same to the memory table 17.

Thereafter, when the zero clear processing of the DRAM module is completed, the refresh execution flag of the corresponding memory table 17 is set to the invalid mode “0”, so that the refresh is not executed even for the refresh request of the memory area.

That is, when the next memory access is a refresh request from the refresh timer 13 by the above-described operation, the refresh execution flag of the memory table 17 is in the invalid mode “0”. 1 "to skip the refresh operation and proceed to the next operation. At this time,
Since the refresh execution flag has been set to the valid mode “1”, the DRA will be
A refresh operation is performed on the M module.

As described above, control such as refreshing is performed by D
By using a RAM module unit, control can be performed for each control signal given to each DRAM module, so that memory access control is facilitated and a control circuit can be simplified.

The refresh operation is performed as follows. That is, the refresh timer 13 internally waits for a refresh interval required by the main memory 11 and outputs a refresh request to the main memory 11 at regular intervals. Upon receiving this refresh request, the memory controller 12 performs a periodic refresh operation. The refresh operation is performed in a CAS before RAS refresh cycle.

However, when receiving the refresh request, the memory controller 12 refers to the refresh execution flag on the memory table 17 corresponding to the DRAM module to be refreshed at the same time. For example,
When the refresh execution flags for m + 1, m + 2, and m + 3 are in the valid mode “1”, as shown in FIG.
The address performs a normal refresh operation. Also,
m is invalid mode "0"
In the case of (1), as shown in FIG. 11, the refresh operation for the memory address is omitted, so that the operation immediately proceeds to the next operation.

As described above, the control such as the refresh
Since it is performed in the AS before RAS refresh cycle,
There is no need to generate a row address unlike the RAS only refresh, so that memory access control becomes easy and the control circuit can be simplified.

[Fourth Embodiment of the Invention] An electronic computer system according to a fourth embodiment of the present invention comprises a main memory 11, a memory controller 12 (refresh management means), a refresh timer 13, and a refresh address counter 14. The address generation circuit 15, the zero clear detection circuit 16 (zero clear request determination means), the memory table 17 (refresh management means), and the like have the same configuration as in the first embodiment. A detailed description of each part common to the first embodiment described above will be omitted.

This embodiment differs from the first embodiment of the present invention in that the address space is changed instead of monitoring the main bus 2 to determine a zero-clear request of a fixed size as described above. The point is that the zero clear request is assigned to the control signal shown and prepared on the main bus 2 separately from the memory address.

That is, the zero clear detection circuit 16 checks the control signal indicating the address space in response to the access request from the main bus 2 to determine whether the request is a zero clear request for a certain area of the main memory 11. Make a decision.

As described above, by allocating the zero clear request to the control signal indicating the address space and prepared on the main bus 2 separately from the memory address,
The circuit scale of the zero clear detection circuit 16 can be reduced.

[Fifth Embodiment of the Invention] An electronic computer system according to a fifth embodiment of the present invention comprises a main memory 11 and a memory controller 1 as shown in FIG.
2 (refresh management means), refresh timer 1
3, refresh address counter 14, address generation circuit 15, zero clear detection circuit 16, memory table 1
7 (refresh management means) and the like have the same configuration as that of the first embodiment, and detailed description of each part common to the first embodiment will be omitted.

In this embodiment, the memory device 1 is provided with a register 18 (selection means). The register 18 can be accessed from the main bus 2 and can be freely written. The register 18 indicates whether or not the next refresh operation in response to the zero clear request is omitted, or whether or not the zero clear process is performed at the next refresh operation with one bit.
By accessing this register 18, the refresh method can be selected.

Next, the operation will be described.

For example, when the value of the register 18 is "0", the next refresh operation for the zero clear request is not omitted, and when the value of the register 18 is "1", the next refresh operation for the zero clear request is omitted. And When the value of the register 18 is “0”, the normal refresh operation is performed, and the refresh operation is not omitted even in response to the zero clear request from the main bus 2. When "1" is written from the main bus 2 to the register 18, the next refresh operation for the zero clear request is omitted from that point, and the same operation as in the first embodiment is performed, for example.

[Sixth Embodiment of the Invention] An electronic computer system according to a sixth embodiment of the present invention, as shown in FIG.
2 (refresh management means), refresh timer 1
3, refresh address counter 14, address generation circuit 15, zero clear detection circuit 16, memory table 1
7 (refresh management means) and the like have the same configuration as that of the first embodiment, and detailed description of each part common to the first embodiment will be omitted.

In this embodiment, an interval timer 19 (timer) is provided in the memory device 1. The interval timer 19 measures a period during which the omission of the refresh after performing the zero clear processing is effective.

Next, the operation will be described.

FIG. 14 for easy understanding will be described below.
This will be described with reference to the flowchart of FIG. For the memory area subjected to the zero clear processing by the zero clear request (steps S21 and S22), the refresh execution flag of the memory table 17 is set to the invalid mode “0” (step S23), and the refresh is also performed for the refresh request for the memory area. Not be executed.

In this embodiment, at the same time, the interval timer 19 is started (step S24), and a certain time is measured. If the refresh timer 13 does not generate a refresh request during this time, the refresh execution flag is set to the valid mode "1" (step S2).
5, S26), a refresh request is accepted. Then, the interval timer 19 is turned off (step S27).

If the next refresh request from the refresh timer 13 occurs before the end of the measurement of the fixed time by the interval timer 19, the refresh execution flag corresponding to the memory area in the memory table 17 is set to the invalid mode " Since it is "0", the refresh operation can be omitted and the next operation can be performed (steps S28 and S29). At the same time, the refresh execution flag is set to the valid mode "1" so that the next refresh request can perform the normal refresh operation (step S32) (steps S30 and S31). If the memory access is neither a zero clear access nor a refresh request, normal read and write accesses are performed (step S33).

Such an operation will be described with reference to the time charts of FIGS.

In the following, an example will be described in which the memory area of frames 0 and 1 is periodically refreshed, and zero clear processing is performed on frame 0 at a certain timing.

As shown in FIG. 15, after the zero clear processing is completed, the refresh execution flag is set to the invalid mode “0”,
The interval timer 19 starts counting. In this example, since the next refresh request for the frame 0 occurs before the count ends, that is, before the fixed time t elapses, the refresh is omitted (None) and the process proceeds to the next process. At the same time, the refresh execution flag is set to the valid mode “1”.

In the case of FIG. 16 as well, after the zero clear processing is completed,
The refresh execution flag is set to the invalid mode “0”, and the interval timer 19 starts counting. Since the next refresh request for frame 0 does not occur even after the end of the count, that is, after the elapse of the predetermined time t, the refresh execution flag is set to the valid mode "1", and the next refresh request performs a normal refresh operation.

[Seventh Embodiment of the Invention] As shown in FIG. 17, a computer system according to a seventh embodiment of the present invention comprises a main memory 11, a memory controller 1
2 (refresh management means), refresh timer 1
3, refresh address counter 14, address generation circuit 15, zero clear detection circuit 16, memory table 1
7 (refresh management means), interval timer 19
Since the configuration is similar to that of the sixth embodiment, detailed description of each part common to the sixth embodiment will be omitted.

In this embodiment, a register 20 (period setting means) is provided in the memory device 1. This register 20 can be accessed from the main bus 2,
You can write freely. The register 20 can set a period during which the refresh omission after the zero clear processing is performed is effective.

Next, the operation will be described.

The operation of this embodiment is described with reference to FIGS.
However, the period t can be varied by accessing the register 20. As a result, the refresh operation can be performed at an accurate time, and data reliability can be ensured.

[0100]

According to the first aspect of the present invention, there is provided a memory device in which a memory area is formed of a DRAM, and the memory area is periodically refreshed to maintain data storage. A refresh management means is provided for a part for which a zero-clear processing request is received from outside, by performing a zero-clear processing based on the zero-clear processing request, replacing the refresh operation based on the first refresh request after the zero-clear processing request. Of the DRAM memory area,
With respect to the part for which the zero-clear processing request is made, the zero-clear processing based on the zero-clear processing request replaces the refresh operation based on the first refresh request after the zero-clear processing request, thereby eliminating unnecessary refresh operations and reducing power consumption during the refresh operation. And the speed of the computer can be improved.

According to a second aspect of the present invention, in the first aspect of the present invention, the refresh management means includes a first zero-clear execution means for performing a zero-clear processing on the memory area based on a zero-clear processing request from outside the system. First memory address storage means for storing a memory address of a portion of the memory area subjected to the zero-clear processing, and a first refresh operation performed after the zero-clear processing on the memory area storing the memory address And a refresh omitting means for omitting the, performing zero clear processing based on a zero clear processing request from outside the system, and changing the memory address of the portion of the memory area where the zero clear processing has been performed. Memory area to be stored and indicated by this stored memory address In contrast, by omitting the refresh operation performed after the first zero clear processing, it is possible to omit wasteful refresh operation.

According to a third aspect of the present invention, in the first aspect of the present invention, the refresh management means holds a zero clear processing request from outside the system to the memory area, and holds the zero clear processing request. Second memory address storage means for storing the memory address of the memory area stored in the memory area, and at the time of the first refresh operation performed after the suspension, the memory area storing the memory address is cleared to zero in place of the refresh operation. And a second zero-clear execution means for performing the processing. Therefore, a zero-clear processing request from outside the system to the memory area is suspended, and a part of the memory area in which the zero-clear request is suspended is held. The memory address is stored, and at the time of the first refresh operation performed after the suspension, Memory area 憶 memory address is displayed to, by performing a zero clear processing instead of the refresh operation, it is possible to omit wasteful refresh operation.

The invention according to claim 4 is the invention according to claims 1, 2,
3. In the invention according to any one of the first to third aspects, the memory area is divided into a plurality of DRAM modules, and refresh management means performs a refresh operation and zero-clear processing performed in place of the refresh operation for each DRAM module. Therefore, control such as refreshing can be performed for each DRAM module, and control can be performed for each control signal given to each DRAM module. The control circuit can be simplified.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the refresh operation is performed by a CAS-before-RAS refresh cycle by the refresh management means. Such control can be performed in a CAS-before-RAS refresh cycle, and a refresh address can be made unnecessary. Therefore, memory access control is facilitated and a DRAM control circuit can be simplified.

The invention according to claim 6 is the invention according to claims 1, 2,
In the invention described in any one of 3, 4, and 5, the refresh management means may perform a zero clear request by using a control signal indicating an address space, which is prepared separately from a memory address on a bus communicating with the DRAM. Since it has a zero clear request determination means for determining the zero clear request, it determines the zero clear request by a control signal indicating an address space prepared separately from the memory address on the bus, so that the bus is monitored. As compared with the case of determining a zero-clear request of a certain size, the circuit for detecting the zero-clear request can be simplified.

The invention according to claim 7 is the invention according to claims 1, 2,
In the invention described in any one of 3, 4, 5, and 6, the refresh management means may include a selection means for selectively performing a zero clear process in place of the refresh operation based on a signal from outside the system. Since the refresh method is a feature, a normal refresh operation can be performed by a signal from outside the system, or a substitute can be performed by zero-clear processing, or a refresh method can be selected. Therefore, a refresh method according to a situation can be obtained.

The invention according to claim 8 is the invention according to claims 1, 2,
In the invention according to any one of 3, 4, 5, 6, and 7,
The refresh management means includes a timer for counting the elapsed time after the zero-clear processing, and the count is such that the refresh operation is omitted only when a refresh request signal is generated within a certain period from the zero-clear request. Therefore, the refresh operation is omitted only when the refresh request signal is generated within a certain period from the zero clear request, so that the refresh operation can be performed in an accurate time and data reliability can be ensured.

According to a ninth aspect of the present invention, in the invention of the eighth aspect, the refresh management means includes a period setting means for adjusting a size of a certain period counted from the zero clear request. Therefore, the refresh operation can be omitted only when the refresh request signal is generated within a certain period from the zero clear request, and in this case, the certain period can be made variable, so that accurate time can be obtained. Refresh operation can be performed, and data reliability can be ensured.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computer system according to first, second, and fourth embodiments of the present invention.

FIG. 2 is a diagram showing a configuration of a memory table according to the first and fourth embodiments of the present invention.

FIG. 3 is a memory map diagram of a main memory showing first, second, and fourth embodiments of the present invention.

FIG. 4 is a timing chart illustrating the operation of the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the first embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a memory table according to the second embodiment of the present invention.

FIG. 7 is a flowchart illustrating the operation of the second embodiment of the present invention.

FIG. 8 is a block diagram of an electronic computer system according to a third embodiment of the present invention.

FIG. 9 is a memory map diagram of a main memory according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a memory table according to a third embodiment of the present invention.

FIG. 11 is a timing chart for explaining the operation of the third embodiment of the present invention.

FIG. 12 is a block diagram of an electronic computer system according to a fifth embodiment of the present invention.

FIG. 13 is a block diagram of an electronic computer system showing a sixth embodiment of the present invention.

FIG. 14 is a flowchart illustrating the operation of the sixth embodiment of the present invention.

FIG. 15 is a timing chart for explaining the operation of the sixth embodiment of the present invention.

FIG. 16 is a timing chart for explaining the operation of the sixth embodiment of the present invention.

FIG. 17 is a block diagram of a computer system according to a seventh embodiment of the present invention.

[Explanation of symbols]

12 refresh management means, first and second zero clear processing, refresh omitting means, zero clear holding means,
Second zero clear executing means 16 Zero clear request determining means 17 Refresh managing means, first and second memory address storing means 18 Selecting means 19 Timer 20 Period setting means

Claims (9)

[Claims] 1. A memory device in which a memory area is composed of a DRAM and which periodically refreshes the memory area to maintain data storage, wherein a portion of the memory area for which a zero clear processing request is issued from outside the system. In contrast, a memory device comprising refresh management means for performing a zero-clear process based on the zero-clear process request and replacing the refresh operation based on the first refresh request after the zero-clear process request. 2. A refresh management unit comprising: a first zero-clear execution unit that performs a zero-clear process on a memory area based on a zero-clear process request from outside the system; and a memory address of a portion of the memory area on which the zero-clear process has been performed. A first memory address storing means for storing the memory address, and a refresh omitting means for omitting a refresh operation performed first after the zero clear processing for the memory area storing the memory address. Item 2. The memory device according to item 1. 3. The refresh management means includes: a zero clear suspending means for suspending a zero clear processing request to the memory area from outside the system; and a second memory address storing a memory address of the memory area in which the zero clear processing request is suspended. Storage means, at the time of the first refresh operation performed after the suspension, for the memory area where the memory address is stored,
2. The memory device according to claim 1, further comprising a second zero-clear execution unit that performs a zero-clear process instead of the refresh operation. 4. The memory area is divided into a plurality of DRAM modules, and the refresh management means performs a refresh operation and a zero clear process in place of the refresh operation.
4. The memory device according to claim 1, wherein the operation is performed for each RAM module. 5. The memory device according to claim 4, wherein the refresh operation is performed by a CAS before RAS refresh cycle by the refresh management means. 6. The refresh managing means includes a zero clear request determining means for determining a zero clear request using a control signal indicating an address space, which is provided separately from a memory address on a bus communicating with the DRAM. 3. The method according to claim 1, wherein
The memory device according to any one of 3, 4, and 5. 7. The refresh management unit according to claim 1, further comprising a selection unit that selectively performs a zero-clear process in place of a refresh operation based on a signal from outside the system. The memory device according to any one of 4, 5, and 6. 8. The refresh management means includes a timer for counting the elapsed time after the zero clear processing, and the refresh operation is omitted only when a refresh request signal is generated within a certain period from the zero clear request by this count. The memory device according to any one of claims 1, 2, 3, 4, 5, 6, and 7, wherein 9. The memory device according to claim 8, wherein the refresh management means includes a period setting means for adjusting a size of a certain period counted from the zero clear request.