JP2000207883A - Synchronous dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronous DRAM(dynamic random access memory) that is harder to generate a needless cycle than in a method in which pre-charge operation is performed using an auto-pre-charge and that can shorten the memory cycle time more than in a method performing pre-charge operation using a pre-charge command. SOLUTION: An exclusive external control signal line DSF1 for performing pre-charge operation is added to this device, a signal is guided to a pre-charge control circuit 106 for controlling pre-charge operation through a controller 105. A bank latch 107 stores tank information at the time of input of a column address read (write)-command, and the information is sent to the pre-charge control circuit. When an external control signal DSF1 is inputted, the controller 105 makes the pre-charge control circuit 106 function, and start of pre-charge operation is required. Thereby, pre-charge can be started at the final of a burst cycle in which judgment for existence of pre-charge is easy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a synchronous DR.
The present invention relates to an AM (Dynamic Random Access Memory), and more particularly to a synchronous DRAM effective for use in burst transfer.

[0002]

2. Description of the Related Art A synchronous DRAM is a main memory of a personal computer at present and is characterized by operating in synchronization with a system clock. In the synchronous DRAM, since the address is specified in the form of a command, it takes a little time to start reading, but thereafter, one data can be read out per clock by the internal pipeline (Nikkei Personal Computer New Dictionary) ).

FIG. 8 shows a general synchronous D of this kind.
FIG. 1 is a block diagram showing an example of a RAM, which is disclosed in Japanese Patent Application Laid-Open No. 8-115593.
The same content is also described in the official gazette.

[0004] In this synchronous DRAM, in a burst mode, a column address counter 806 is provided for one word line selected by a row decoder 801A.
Thus, complementary data lines of addresses successively designated are selected, and data of the designated burst number can be continuously read or written.

FIG. 9 is a block diagram showing a configuration example of the column address counter 806 in FIG. In FIG. 9, a counter unit (COUNTER UNIT) 900 has a counter of the number of bits corresponding to the bit configuration of the input initial address, and is a unit for counting the burst length.

A column address generator (COLUMN ADD)
RESS GENERATOR) 901 selects a column system based on the output of the counter unit 900, and a burst end monitor 90
When 2 monitors the output signal of the counter unit 900 and detects a burst end, the counter control circuit 903 controls the operation of the counter unit 900.

A burst end monitor 902 (BURST EN
D MONITOR) is a precharge operation section (not shown) for burst end when auto precharge is selected.
Notify to Controller (CONTROL LOGIC & TIMING GE
The NERATOR 904 notifies the burst end monitor 902 of the presence / absence of the auto precharge and sends a command to the counter control circuit 903 (COUNTER CONTROL LOGIC).

Next, the operation of the column address counter 806 will be described.

In FIG. 9, a burst end monitor 902
Is set to the burst length set in the mode register (built-in to the controller 810) in advance, and the initial column address is set to the counter unit (COUNTER).
UNIT) 900 and column address generator (COLUMN ADDRE)
After being set to (SSGENERATOR) 901, the counting operation of the counter unit 900 is started in synchronization with the internal clock signal ICLK.

The output of this count is input to a column address generator 901 and outputs a column address.
Then, the burst end is detected by monitoring the counter value of the counter unit 900 with the burst end monitor 902. If the burst end is detected, the counter end is notified to the counter control circuit 903, and the counting of the counter unit 900 is stopped.

When the auto precharge is selected, the burst end monitor 902 sends a burst end to the precharge operation section to start the precharge operation.

Further, when the burst length is a full page, no burst end occurs, so a burst stop in full page command is issued to the controller 904.
, The count of the counter unit 900 can be similarly stopped.

By the way, one of the read commands of the synchronous DRAM includes a column address, read with, and
There is an auto precharge command. This command
As one mode of the read operation, when burst read is set in the mode register, when a read command is input, auto precharge is selected according to the value of an address signal on a predetermined address input terminal.

FIG. 10 shows the timing when auto precharge is selected by the column address read with auto precharge command and the burst length in the burst mode is set to 4.

In FIG. 10, a column address read command for starting a burst read operation for bank (BANK) 0 is input, and at the same time, a high level is input to address input terminal A10, so that auto precharge is selected. After the completion of the four burst mode cycles, the precharge operation is automatically started. Since this precharge operation does not require command input, a column address read command can be input to the next bank 1 immediately after the end of the burst mode cycle of bank 0, and continuous read data can be output. Become.

[0016]

As described above, the auto precharge does not require the input of a precharge command and is effective in shortening the memory cycle time. However, in the above-mentioned conventional synchronous DRAM, the auto precharge is not performed. The setting for charging needs to be performed by the first column address read / write command in the burst cycle.

Therefore, it is difficult to predict whether or not the precharge is necessary for the next cycle of the currently executed burst cycle. Therefore, a precharge command not using the auto precharge is input or the precharge command is not input. There is a problem that a necessary auto precharge may make a memory cycle longer than necessary.

FIG. 11 shows that when the burst length of the burst mode is set to 4, an interrupt cycle having a higher priority than the cycle of bank 0 is performed for bank 1 during the burst read cycle for bank 0. The timing chart in the case is shown.

In FIG. 11, after inputting a row address strobe / bank active command (ACT) to bank 0, a column address read command Read is input after a time during which a command can be input. In this figure,
At the time of inputting the column address read command Read, the address input terminal A10 is set to the low level so that the auto precharge is not executed. Therefore, it is necessary to input the precharge command PRE after the end of the burst cycle. However, it shows a state in which the cycle of the bank 0 is delayed because it collides with the column address read command Read of the interrupt cycle for the bank 1.

The cycle as shown in FIG. 11 is often seen particularly in access to an image memory used in a display system or the like, and many cycles for changing a row address, such as a cycle for bank 0, occur. An interrupt cycle having a high priority for 1 frequently occurs as a read operation for displaying on a display.

In addition, since many irregular cycles occur in the access cycle to the image memory, auto precharge, which requires an input at the beginning of the cycle, is not effective in reducing the cycle time.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a synchronous DRAM in a system for controlling a synchronous DRAM in which a memory cycle time is shortened to improve a memory access efficiency.

[0023]

According to the first aspect of the present invention, a synchronous DRAM is provided with a dedicated external control signal line for performing a precharge operation, and independent of a command. Precharge can be forcibly executed by input of an external control signal.

Further, the synchronous DRA according to the second invention is provided.
M adds an external control signal line, and when an external control signal is input via the signal line, interrupts a burst cycle or starts a precharge operation according to a count value of a predetermined counter. Features.

Further, a preferred embodiment of the present invention is:
A precharge control circuit that requests the precharge operation unit to start a precharge operation, a bank latch that stores the bank information when a column address read (write) command is input, and an external control signal line dedicated to the precharge. And a controller for transmitting bank information stored in the bank latch to the precharge control circuit in response to an input external control signal, and executing a precharge to the bank.

Further, a preferred embodiment of the present invention is a counter unit in which an initial address in a burst mode is set, and which performs a counting operation for generating an address for a burst operation in synchronization with a clock, and the counter unit. A counter control circuit for controlling the unit, a precharge control circuit for requesting a precharge operation unit to start a precharge operation, a bank latch for storing the bank information when a column address read (write) command is input, A 1-bit counter for counting signals, and a function of resetting the counter, notifying the external control signal to the counter control circuit or the precharge control circuit according to the count value, and causing each circuit to function; When a precharge instruction is given, There is characterized by providing a controller for sending the bank information stored to the pre-charge control circuit.

According to the present invention, one signal line for performing a precharge operation is added to a synchronous DRAM, and a mechanism for connecting the circuit to a circuit for controlling the precharge operation is provided. At the same time, the precharge operation can be started, and the memory cycle time can be reduced.

In particular, the auto precharge does not require the input of a precharge command and is effective for shortening the memory cycle time. However, the setting for performing the auto precharge is performed by the first column address read / write command in the burst cycle. It is difficult to predict whether or not precharge is necessary for the next cycle of the currently executing burst cycle. In addition, there is a problem that a memory cycle is made unnecessarily long by performing unnecessary auto precharge or the like.

According to the present invention, a mechanism for adding one signal line for performing the precharge operation to the synchronous DRAM and connecting the signal line to a circuit for controlling the precharge operation is employed. Since the precharge operation can be started at the end of the burst cycle in which the judgment is easy, and the precharge operation can be started simultaneously with the input of another command, the memory cycle time can be reduced.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

First, a synchronous DRAM will be described, and then a column address counter which is a feature of the present invention will be described in detail.

FIG. 8 shows a general synchronous DRAM.
A schematic block diagram of one example is shown. This synchronous DRAM includes a memory array (MEMORY ARRAY) 800A constituting a memory bank (MEMORY BANK) 0 and a memory array 800B constituting a memory bank 1. Each of the memory arrays 800A and 800B includes dynamic memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column are connected to word lines (not shown) for each column. The data input / output terminals of the memory cells arranged on the same row are connected to complementary data lines (not shown) for each row.

The sense amplifier (SENSE AMPLIFIER) in the sense amplifier / column selection circuit 802A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in the sense amplifier / column selection circuit 802A is a switch circuit for selecting a complementary data line individually and conducting to a complementary common data line (I / O BUS). The column switch circuit is a column decoder (COLUMN DECO
The selection operation is performed according to the result of decoding the column address signal by the DER) 803A.

Similarly to the above, a row decoder 801B, a sense amplifier / column selection circuit 802B, and a column decoder 803B are provided on the memory array 800B side. The above memory bank 80
The complementary common data lines (I / O BUS) of 0A and 800B are connected to the output terminal of the input buffer (INPUT BUFFER) 808 and the output buffer (OUTP
UT BUFFER) 809 is connected to the input terminal. Input buffer 8
The input terminal 08 and the output terminal of the output buffer 809 are connected to 8-bit data input / output terminals I / O0 to I / O7.

A column address buffer (COLUMN ADDRESS BUFF) for holding a row address signal and a column address signal supplied from the address input terminals A0 to A11.
ER) 805 and row address buffer (ROW ADDRESS BUFFER) 80
4 and a refresh counter (REFRESH COUNTE) for refreshing dynamic memory cells.
R) 807.

The refresh counter 807 is connected to a row address buffer 804 for taking in a refresh address signal output therefrom as a row address signal.
A, 801B. The output of the column address buffer 805 is the column address counter (COLUMN ADDRESS COUNTER)
It is supplied to 806 and output to column decoders 803A and 803B.

[0037] CONTROL LOGIC & TIMING GE
NERATOR) 810 includes a clock signal CLK, a clock enable signal CKE, a chip select signal / CS, a column address strobe signal / CAS, a row address strobe signal / RAS, a write enable signal / WE, a data input / output mask control signal DQM, and the like. An external control signal, control data from the address input terminals A0 to A11, and a reference voltage Vref are supplied. Then, based on the level change and timing of these signals, an internal timing signal for controlling the operation mode of the synchronous DRAM and the operation of each of the above circuit blocks is formed, and a control logic and a mode register for that are provided. .

Next, the operation of the synchronous DRAM will be described.

The row address signal and the column address signal supplied from the address input terminals A0 to A11 are taken into the column address buffer 805 and the row address buffer 804 in an address multiplex format. The supplied address signals are held in respective buffers 805 and 804.

In the refresh operation mode, the row address buffer 804 takes in a refresh address signal output from the refresh counter 807 as a row address signal. The output of the column address buffer 805 is supplied as preset data of a column address counter 806, and the column address counter 806 outputs the column address signal as the preset data or the column address signal thereof according to an operation mode specified by a command described later. The value obtained by sequentially incrementing the column address signal is
Output to column decoders 803A and 803B.

One word line is driven to a selected level according to the result of decoding of a row address signal by row decoders 801A and 801B. Complementary data lines (not shown) of the memory arrays 800A and 800B are connected to the sense amplifier / column selection circuit 802.
A, 802B
The sense amplifier in A, 802B detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell, and the column switch circuit causes complementary data in accordance with the decoding result of the column address signal by the column decoders 803A, 803B. The lines are individually selected and conducted to the complementary common data line (I / O BUS) to read and write data.

The row address signal is defined by the levels of the address input terminals A0 to A11 in a row address strobe / bank active command cycle described later, which is synchronized with the rising edge of the internal clock signal ICLK. The input from the address input terminal A11 is regarded as a bank selection signal in the row address strobe / bank active command cycle.

That is, when the input of the address input terminal A11 is at low level, the memory array 800A (bank 0) is selected, and when it is at high level, the memory array 800B (bank 1) is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the non-selected memory bank are unselected, the input buffer 808 and the output buffer 808 of the selected memory bank only. This can be performed by processing such as connection to the 809.

On the other hand, the column address signal is the level of the address input terminals A0 to A8 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the internal clock signal ICLK. Defined by The column address defined in this way is used as a start address for burst access.

The clock signal CLK has a synchronous DR
The master clock of AM is used, and other external input signals are made significant in synchronization with the rising edge of the internal clock signal ICLK. Chip select signal / CS
Indicates the start of a command input cycle by its low level. When the chip select signal / CS is at a high level (chip is not selected) and other inputs have no meaning.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal CLK. When the clock enable signal CKE is at a high level, the rising edge of the next clock signal CLK is valid, and when it is at a low level. Invalidated. Further, although not shown, in the read mode, an external control signal for controlling output enable for the output buffer 809 is also supplied to the controller 810. When the signal is at a high level, for example, the output buffer 809 is set to a high output impedance state. .

An input to the address input terminal A10 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and a high level thereof indicates that a precharge target is both memory banks. The low level is applied to the address input terminal A1
Indicates that one of the memory banks indicated by 1 is to be precharged.

Next, main operation modes of the synchronous DRAM specified by the command will be described.

(1) Mode register set command (M
OD) Command for setting the mode register.
The command is designated by CS, / RAS, / CAS, / WE = low level, and data to be set (register set data) is given via address input terminals A0 to A11. Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. The burst lengths that can be set are 1, 2, 4, 8, and full pages, the CAS latency that can be set is 1, 2, 3, and the write modes that can be set are burst write and single write. Is done.

In the read operation specified by a column address read command to be described later, the above CAS latency is caused by the fall of / CAS from the output buffer 809.
Indicate how many cycles of the internal clock signal ICLK are to be consumed before the output operation. Until the read data is determined, an internal operation time for data read is required, but this is set in accordance with the operating frequency of the internal clock signal ICLK.

In other words, when using the internal clock signal ICLK having a high frequency, the CAS latency is set to a relatively large value, and when using the internal clock signal ICLK having a low frequency, the CAS latency is set relatively. To a small value. Although not particularly limited, in an image processing operation to be described later, the CAS latency can be set to a large value in order to secure a word line switching time if necessary.

(2) Row address strobe / bank active command (ACT) This is a command for validating a row address strobe and selecting a memory bank by the address input terminal A11. / CS, / RAS = low level, / CAS,
/ WE = high level. At this time, the address supplied to the address input terminals A0 to A10 is captured as a row address signal, and the signal supplied to the address input terminal A11 is captured as a memory bank selection signal.

The fetch operation is performed in synchronization with the rising edge of the internal clock signal ICLK as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column Address Read Command (Read) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe. / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, the column address supplied to the address input terminals A0 to A8 is taken in as a column address signal. The column address signal thus captured is
It is supplied to the column address counter 806 as a burst start address.

In the burst read operation designated thereby, the memory bank and its word line are selected in the row address strobe / bank active command cycle before that, and the memory cell of the selected word line is , Are sequentially selected in accordance with an address signal output from column address counter 806 in synchronization with internal clock signal ICLK, and are continuously read. The number of data read continuously is the number specified by the burst length. Also, output buffer 80
The start of data reading from 9 is performed after waiting for the number of cycles of the internal clock signal ICLK defined by the CAS latency.

(4) Column Address Write Command (Write) As a mode of the write operation, when a burst write is set in the mode register, the command is a command necessary to start the burst write operation. As a mode, when single write is set in the mode register, the command is a command necessary to start the single write operation.

Further, the command gives an instruction of a column address strobe in single write and burst write. The command is / CS, / CAS, /
Instructed by WE = low level and / RAS = high level, the addresses supplied to the address input terminals A0 to A8 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 806 as a burst start address in burst write.

The procedure of the designated burst write operation is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Column address read with
Auto Precharge Command (RP) When burst read is set in the mode register as a mode of the read operation, the address input terminal A10 is used to determine whether to select the auto precharge when a column address read command is input. used. If the address input terminal A10 is at the high level at the time of inputting the column address read command, auto precharge is selected, and if the CAS latency is set to 2, one cycle before the last output burst data is output. ,
Precharge is automatically started, and when the CAS latency is set to 3, the precharge is automatically started two clocks before the last output burst data.

(6) Column address write with
Auto Precharge Command (WP) When burst write is set in the mode register as a mode of the write operation, when a column address / write command is input, the address input terminal A10 is used to determine whether to select auto precharge. used. If the address input terminal A10 goes high when a column address / write command is input, auto precharge is selected, and precharge starts automatically one clock after the last data is input.

(7) Precharge command (PRE) This is a command to start a precharge operation for the memory bank selected by the address input terminals A10 and A11. / CS, / RAS, / WE = low level, / C
AS is indicated by a high level.

(8) Auto-refresh command This command is required to start auto-refresh, and includes / CS, / RAS, / C
AS = low level, / WE, CKE = high level.

(9) Burst stop in full page command (BST) This command is necessary to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. . This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(10) No operation command (N
OP) This is a command for instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, /
Indicated by the high level of WE.

Here, the features of the synchronous DRAM will be described. In a synchronous DRAM,
When a burst operation is being performed in one memory bank and another memory bank is specified in the middle of the burst operation and the row address strobe bank active command ACT is supplied, the memory bank in the above-described one memory bank during execution is supplied. The operation of the row address system in the another memory bank is enabled without affecting the operation.

For example, a synchronous DRAM has means for internally holding data, addresses, and control signals supplied from the outside. The held contents, particularly addresses and control signals, are not particularly limited. It is kept every time. Alternatively, data of one word line in the memory block selected by the row address strobe / bank active command cycle may be latched in advance by a latch circuit (not shown) for a read operation before the column operation. Has become.

Therefore, data input / output terminals I / O0 to I / O0
Unless data collision occurs in the I / O 7, during execution of a command whose processing has not been completed, a precharge command PRE for a memory bank different from the memory bank to be processed by the command being executed, row address strobe bank active It is possible to issue the command ACT to start the internal operation in advance.

The synchronous DRAM has an internal clock signal ICL formed based on an external clock signal CLK.
Data, address or / RAS, / CAS in synchronization with K
And the like can be defined as a memory capable of inputting and outputting various control signals. A synchronous DRAM can operate a large-capacity memory similar to a DRAM at a high speed comparable to that of an SRAM (static RAM), and can store some data for one selected word line. By designating whether or not to access by a burst length, the built-in column address counter 806 sequentially switches the selection state of the column system, so that a plurality of data can be continuously read or written.

Next, a column address counter proposed by the present inventor, which is suitable as the column address counter 806 used in the synchronous DRAM of FIG. 8, will be described.

FIG. 5 is a block diagram of the address counter. In FIG. 5, the counter unit 500 has a counter of the number of bits corresponding to the bit configuration of the input initial address, and is a unit for counting the burst length. A column address generator 501 for selecting a column system based on the output of the counter unit 500 is provided, and the purpose of monitoring the output signal of the counter unit to detect a burst end and auto precharge are selected. In such a case, a burst end monitor 502 for notifying the precharge operation section of the burst end and a counter control circuit 503 for controlling the operation of the counter unit 500 based on the burst end detection result are provided.

In addition to the controller 504 connected to both, to notify the burst end monitor 502 of the presence / absence of auto-precharge and to send a command to the counter control circuit 503, a special purpose for stopping the burst is provided. (CON) to input the signal line (DSF1)
TROL LOGIC & TIMING GENERATOR) 505.

Next, the operation of the column address counter will be described.

In FIG. 5, a burst end monitor 502
After the burst length set in the mode register is set in advance, the initial column address is set in the counter unit 500 and the column address generator 501, and then the counting operation of the counter unit 500 starts in synchronization with the internal clock signal ICLK. Is done. The output of this count is input to the column address generator 501, and outputs a column address.

By monitoring the counter value of the counter unit 500 with the burst end monitor 502, the burst end is detected. If the burst end is detected, the counter end is notified to the counter control circuit 503, and the counting of the counter unit 500 is stopped. When the auto precharge is selected, the burst end is sent to the precharge operation section to start the precharge operation.

When the burst length is a full page, since a burst end does not occur, a burst stop-in full page command BST is issued to the controller 504.
, The counting of the counter unit 500 can be similarly stopped.

A feature of the present invention is that a dedicated signal line (DSF1) for stopping a burst is provided by the controller 50.
The burst cycle is aborted by an active input to 5.

In a system for controlling a plurality of synchronous DRAMs using a chip select signal,
Actively input the SF1 signal to the controller 505,
FIG. 6 shows the timing when the burst cycle is interrupted.

Referring to FIG. 6, chip select signal / CS
0 and DSF associated with chip select signal / CS0
1. The command (CS0) includes a plurality of synchronous DRAs.
M is one of the control signals, and is a chip select signal / CS
1 and DSF associated with chip select signal / CS1
1 (CS0) and command (CS0) are the other control signals.

Read of the command (CS0) is the above-described column address read command. At the same time, the burst cycle is interrupted by activating the DSF1 signal, and the column address read command of the command (CS1) is output at the next clock. You can enter Read.

Next, FIG. 7 shows the timing when a precharge command PRE is input. In FIG. 7, the column address read command Re is used when the burst mode is used.
input the high level of ad and A10 at the same time,
Although the read with auto precharge command RP is set, the autoprecharge cannot be executed because the burst count was stopped by the DSF1 signal input.
Instead, the precharge command PRE is input.

However, it can be seen that the input of the column address read command Read to CS1 is delayed due to the input of the precharge command PRE to CS0.

In FIG. 7, the delay of the memory cycle due to the input of the precharge command is clear. The overhead of the precharge command PRE increases as the access switching to the synchronous DRAM connected to another chip select signal increases. To increase.

As described above, according to the present invention, even when the column address read with auto precharge RP is input in the burst mode, if the burst count is stopped by the DSF1 signal input, the auto precharge cannot be executed. Instead, a precharge command PRE must be entered. This is the precharge command
Since it is necessary to avoid collision between the input of the PRE and the input of another command, there is a problem that the memory cycle time becomes longer.

The present invention has been made to solve such a problem, and FIG. 1 shows the configuration of the column address counter of the first embodiment.

In FIG. 1, the counter unit 100 is
It has a counter for the number of bits corresponding to the bit configuration of the input initial address, and is a unit for counting the burst length. The column address generator 101 performs column selection based on the output of the counter unit 100, the burst end monitor 102 monitors the output signal of the counter unit 100 to detect a burst end, and the counter control circuit 103 The operation of the counter unit 100 is controlled based on the end detection result. The controller 104 sends a command to the counter control circuit 103.

The precharge control circuit (PRECHARGE C)
ONTROL LOGIC) 106 is a precharge operation unit (not shown)
Precharge start signal including bank information (PRECHARGE)
And sends a precharge end signal (PRECHARGE TERMINATION) to the row address buffer 804. And
Connected to the burst end monitor 102 to input a burst end detection result that notifies the start of auto precharge, and inputs a row address strobe / bank active command ACT, a column address read command Read or a column address write command Write For connection to the controller 104.

Further, a column address read command
Bank latch circuit (BANK LA) for storing bank information when a Read or Column Address Write command is input
TCH) 107 and a controller (CONTR) for inputting a dedicated signal line (DSF1) for performing a precharge operation.
OL LOGIC & TIMING GENERATOR) 105, each of which is connected to the precharge control circuit 106.

Next, the operation of the column address counter (806 in FIG. 8) shown in FIG. 1 will be described.

In FIG. 1, the burst end monitor 102
, A burst length preset in the mode register is set, and an initial column address is set in the counter unit 100 and the column address generator 101. Thereafter, the counting operation of the counter unit 100 is started in synchronization with the internal clock signal ICLK.

The output of the counter unit 100 is input to a column address generator 101 and outputs a column address. Then, by monitoring the count value of the counter unit 100 with the burst end monitor 102, the burst end is detected. If the burst end is detected, the counter end is notified to the counter control circuit 103, and the counting of the counter unit 100 is stopped.

When the burst length is a full page,
Since burst end does not occur, burst stop
By inputting the in-full page command BST to the controller 104, the counting of the counter unit 100 can be similarly stopped.

When the controller 104 recognizes the column address read with auto precharge command RP or the column address write with auto precharge command WP, the burst end monitor
When the burst end monitor 102 detects a burst end, it notifies the precharge control circuit 106,
The precharge control circuit 106 requests the precharge operation unit to start a precharge operation.

The bank latch circuit 107 includes a controller 104
Then, a column address read command Read or a column address read command Write and A11 are input, and the bank information at the time of inputting these commands is stored. The bank information is transmitted to the precharge control circuit 106, and when the DSF1 signal input to the controller 105 becomes active, a precharge request for the corresponding bank is transmitted to the precharge operation unit based on the bank information. . The precharge operation by the DSF1 signal has a higher priority than the auto precharge operation, and the auto precharge operation is canceled before or at the same time as the auto precharge operation.

FIG. 2 shows a timing chart when the dedicated line (DSF1) for starting the precharge operation is activated when the burst length in the burst mode is set to 4. FIG. 2 shows the timing when an interrupt cycle having a higher priority than the cycle of the bank 0 is performed on the bank 1 during the burst read cycle for the bank 0 as in FIG.

In FIG. 11, after the row address strobe / bank active command ACT for the bank 0 is input, the column address read command Read is input after a time during which the command can be input. In this case, A10 is set to the low level and the auto-precharge is not executed, so that the precharge command PRE needs to be input after the end of the burst cycle.

Therefore, in the present invention, by activating DSF1, bank information (bank information simultaneously input with DSF1) stored in the bank latch circuit 107 of FIG. 1 is used at the time of next DSF1 input. Precharge). As a result, as shown in FIG. 2, when DSF1 becomes active (high level), precharging of bank 0 is performed, and simultaneous input of a column address read command Read to bank 1 becomes possible. The cycle time of 0 can be shortened.

Next, a description will be given of a second embodiment of the column address counter according to the present invention.

FIG. 3 is a block diagram showing the configuration of the column address counter according to the second embodiment of the present invention.

In FIG. 3, the counter unit 300 is
It has a counter for the number of bits corresponding to the bit configuration of the input initial address, and is a unit for counting the burst length. The column address generator 301 selects a column system based on the output of the counter unit 300, the burst end monitor 302 monitors the output signal of the counter unit 300 to detect a burst end, and the counter control circuit 303 outputs the burst end detection result. The operation of the counter unit 300 is controlled based on The controller 304 sends a command to the counter control circuit 303.

Further, in addition to the controller 304 connected to the counter control circuit 303, the controller 30 which inputs a dedicated signal line (DSF1) for the purpose of stopping the burst cycle and for performing the precharge operation.
5 and a DSF1 counter (DSF1 COUNTER) 30 which is a 1-bit counter for counting a burst stop request and a precharge operation request output from the controller 305.
8 is provided.

The count value of the DSF1 counter 308 is reset by a signal from the controller 304,
The counter output of the F1 counter 308 is notified to the counter control circuit 303 when the counter value is “0”, and is notified to the precharge control circuit 306 when the counter value is “1”.

The precharge control circuit 306 is a control circuit for sending a precharge start signal including bank information to the precharge operation section. The precharge control circuit 306 outputs a burst end detection result for notifying the start of auto precharge. Connected to monitor 302, precharge command P
Connected to controller 304 to input RE.

The bank latch circuit 307 is for storing bank information at the time of inputting a column address / read command Read or a column address / write command Write, and is connected to the precharge control circuit 306.

Next, the operation of the second embodiment will be described.

In FIG. 3, the burst length set in the mode register in advance is set in the burst end monitor 302, the initial column address is set in the counter unit 300 and the column address generator 301, and then the internal clock signal ICLK is set. The counting operation of the counter unit 300 is started in synchronization. The output of this count is input to the column address generator 301, and outputs a column address.

Then, the counter value of the counter unit 300 is monitored by the burst end monitor 302 to detect the burst end. If the burst end is detected, the counter end is notified to the counter control circuit 303 and the counting of the counter unit 300 is stopped. If the burst length is full page, the burst end does not occur, so the burst stop in full page command is issued to the controller 30.
By inputting to 4, the counting of the counter unit 300 is similarly stopped.

Further, DSF1 which is a feature of the second embodiment is used.
The initial value of the counter 308 is “0”, and when the count value is “0”, the input of the DSF1 signal to the controller 305 is regarded as a burst stop request, and the DSF1 counter 308 is counted up to increase the count value to “ After setting it to 1 ", the counter control circuit 303 is notified of a request to stop counting. By this request, the counter control circuit 303
The counting of the counter unit 300 is stopped, and the burst cycle is stopped.

If the controller 305 receives the DSF1 signal when the count value of the DSF1 counter 308 is "1", the input of the DSF1 signal is regarded as a precharge operation request, and the DSF1 counter 308 is counted up by counting up. After setting the value to “0”, a precharge operation request is sent to the precharge control circuit 306, and the precharge control circuit 306 sends a precharge operation request PRECHARGE including bank information to the precharge operation unit.

This bank information is stored in the bank latch circuit 307.
From the controller 304, a column address read command Read or a column address write command Writ
A11 is input and stored together with e. And the aforementioned DS
It is input to the precharge control circuit 306 together with the precharge operation request sent from the F1 counter 308, and the precharge control circuit 306 sends a precharge request PRECHARGE to the corresponding bank to the precharge operation unit based on the bank information.

When the column address read command Read or the column address write command Write is input, the count value of the DSF1 counter 308 becomes an initial value by a signal transmitted from the controller 304. Also,
The controller 304 performs column address read / write
After recognizing the with auto precharge command RP, when there is no active input of the DSF1, it notifies the burst end monitor 302, and if it is burst end, notifies the precharge control circuit 306, and the precharge control circuit 306 A request to start a precharge operation is issued to the precharge operation unit.

Next, the operation of this embodiment will be described with reference to a timing chart.

FIG. 4 shows a system in which a plurality of synchronous DRAMs are controlled by using a chip select signal, the DSF1 signal is input to the controller 305 only for two clocks, and the first active input (the first clock). 4) is a timing chart when the burst cycle is interrupted and a precharge operation is performed at the next active input (second clock).

Referring to FIG. 4, chip select signal / CS
0 and DSF associated with chip select signal / CS0
1 (CS0), command (CS0), and A10 (CS0) are control signals for one of a plurality of synchronous DRAMs, and include a chip select signal and a DS related to chip select signal / CS1.
F1 (CS1), command (CS1), and A10 (CS1) are the other control signals.

A burst cycle in which auto-precharge is selected is started by simultaneously inputting a column address read command read and a high level of A10 to CS0, but DSF1 (CS
Since 0) is at the high level, the burst cycle is interrupted, and at the same time, the counting of the counter unit 300 is stopped, so that the auto precharge is not executed.

Then, the precharge operation is started when DSF1 is at the high level also in the next clock. This precharge operation is based on the precharge command
Since the input of PRE is unnecessary, after the burst cycle of CS0 is completed, the input of the column address read command Read to CS1 can be input in the next clock, thereby reducing the cycle time.

Further, the column address for CS1
The burst cycle started by inputting the read command Read is interrupted by the next clock because DSF1 (CS1) is at the high level, and the burst cycle is started in the next cycle.
The precharge operation has been started when F1 (CS1) is at the high level. At this time, a row address strobe / bank active command ACT for starting a burst operation can be simultaneously input to CS0.

[0117]

The first effect of the present invention is that the synchronous D
In a RAM, a useless cycle is less likely to occur as compared with a method of performing a precharge operation using auto precharge, and a memory cycle is compared with a method of performing a precharge operation using a precharge command. It can save time.

The reason is that one signal line for performing the precharge operation is added to the synchronous DRAM, and a mechanism for connecting to a circuit for controlling the precharge operation is employed. This is because the precharge operation can be started at the end of the burst cycle in which it is easy to judge, and the precharge operation can be started simultaneously with the input of another command.

The second effect is that a synchronous DRAM which interrupts a burst cycle using a dedicated signal line is used.
In this case, it is possible to obtain the same effect as the auto precharge which cannot be used when the burst cycle is interrupted, and to shorten the memory cycle time.

The reason is that the signal line for interrupting the burst cycle and the signal line for performing the precharge operation are shared, and one signal line is added to the synchronous DRAM to interrupt the burst cycle. No need for command input after the burst cycle is interrupted, and the precharge operation can be started at the same time as another command input by adopting a mechanism for connecting to the circuit for controlling the precharge operation and the circuit for controlling the precharge operation. That's why.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a column address counter used in a synchronous DRAM of the present invention.

FIG. 2 is a timing chart of the embodiment shown in FIG.

FIG. 3 is a block diagram of a second embodiment of a column address counter used in the synchronous DRAM of the present invention.

FIG. 4 is a timing chart of the embodiment shown in FIG. 3;

FIG. 5 is a block diagram of an embodiment of a column address counter in the proposed invention.

FIG. 6 is a timing chart for explaining features of the embodiment shown in FIG. 5;

FIG. 7 is a timing chart for specifying a problem in the embodiment shown in FIG. 5;

FIG. 8 is a block diagram of a general synchronous DRAM.

FIG. 9 is a block diagram of a conventional column address counter in a synchronous DRAM.

10 is a timing chart of a burst cycle when auto precharge is selected in the column address counter shown in FIG. 9;

11 is a timing chart of a burst cycle when auto precharge is not selected in the column address counter shown in FIG. 9;

[Explanation of symbols]

 100, 300, 500, 900 Counter unit 101, 301, 501, 901 Column address generator 102, 302, 502, 902 Burst end monitor 103, 303, 503, 903 Counter control circuit 104, 304, 504, 904 Controller 105, 305 , 505 Controller 106, 306 Precharge control circuit 107, 307 Bank latch 308 DSF1 counter 800A, 800B Memory array 801A, 801B Row decoder 802A, 802B Sense amplifier / column selection circuit 803A, 803B Column decoder 804 Row address buffer 805 Column address buffer 806 Column address counter 807 Refresh counter 808 Input buffer 809 Output buffer 810 Controller

Claims (5)

[Claims] An external control signal line dedicated for performing a precharge operation is added, and a precharge can be forcibly executed by inputting an external control signal from the external control signal line regardless of a command. A synchronous DRAM characterized by the above. 2. A precharge control circuit for requesting a precharge operation unit to start a precharge operation, a bank latch for storing the bank information when a column address read (write) command is input, and an external control dedicated to the precharge In response to an external control signal input via a signal line, the bank information stored in the bank latch is transmitted to the precharge control circuit,
2. The synchronous DRAM according to claim 1, further comprising a controller for executing a precharge to said bank. 3. An external control signal line is added, and when an external control signal is input via the signal line, a burst cycle is interrupted or a precharge operation is started according to a count value of a predetermined counter. A synchronous DRAM characterized by the above-mentioned. 4. A counter unit for setting an initial address in a burst mode and performing a count operation for generating an address for a burst operation in synchronization with a clock; a counter control circuit for controlling the counter unit; A precharge control circuit for requesting a precharge operation unit to start a precharge operation; a bank latch for storing the bank information when a column address read (write) command is input; a 1-bit counter for counting the external control signal; Having a function of resetting the counter, notifying the counter control circuit or the precharge control circuit of the external control signal based on a count value to make the respective circuits function, Stores the bank information stored by Synchronous DRAM according to claim 3, characterized in that a controller for sending to the di-control circuit. 5. A synchronous DRAM according to claim 1, wherein a plurality of synchronous DRAMs according to claim 1 are connected by a bus and individually selected by a chip select signal.