JPH08212126A - Dram controller - Google Patents

Abstract

PURPOSE: To shorten time for performing access to a DRAM. CONSTITUTION: This device is provided with a multiplexer 23 for supplying address signals to designate write and read addresses to a DRAM 40 during a term excepting for a refresh cycle, timing generator 24 for generating a prescribed control signal in a sequence suitable for write and read, and read/write buffer 25 for storing the plural pairs of the address signals supplied from the multiplexer 23 to the DRAM 40 for write and data to be wirtten in the addresses of the DRAM 40 designated by these address signals together. Further, a buffer managing circuit 26 is provided for detecting the storage of the address signal supplied to the DRAM 40 for reading in a buffer 25 and changing the generation sequence of the prescribed control signal in order to output the data stored in the buffer 25 as the read result together with this address signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
The present invention relates to a DRAM controller that controls the operation of (DRAM).

[0002]

2. Description of the Related Art In computer systems, DR is generally used.
AM is used as the main memory. This DRAM has, for example, a structure as shown in FIG. When writing 1-word data to this DRAM, this data is externally stored in the read / write data register 10, and the input / output circuit 1 is driven by the fall of the write enable signal WE bar.
1 to the memory array 12. The data write address signal is externally supplied to the multiplexer 13. The multiplexer 13 separates this address signal into a row address signal RA and a column address signal CA, and supplies them to a row address register 14 and a column address register 15, respectively. The row address register 14 supplies the row address signal RA to the row decoder 16 with the fall of the row address strobe signal RAS bar, and the column address register 15 has the column address signal CA with the fall of the column address strobe signal CAS bar. The column decoder 17
Supply to. The row decoder 16 selects a row of the memory array 12 according to the row address signal RA, and the column decoder 17 selects a column of the memory array 12 according to the column address signal CA. The data is stored in one word worth of memory cells located in the row and column of the memory array thus selected.

By the way, since the above-mentioned DRAM requires periodic refreshing, it is used by the DRAM controller for determining the access timing between the CPU and the DRAM. When this CPU issues a data read or write request, the DRAM notifies the CPU that it is in a busy state in order to perform an access process according to the request, and in the meantime, transfers the control signals and data described above in an appropriate sequence. Operation, clear the busy state when reading or writing of data is completed.

[0004]

Although the CPU can perform extremely high-speed data processing internally, the DR
When it becomes necessary to access the AM frequently, its effective processing speed is lowered depending on the performance of the DRAM.

An object of the present invention is to provide a DRAM controller capable of shortening DRAM access time.

[0006]

According to the present invention, an addressing unit for supplying an address signal designating a write and read address to a DRAM during a period excluding a refresh cycle and a predetermined sequence in a sequence suitable for write and read. A plurality of sets of a control signal generating section for generating the control signal of the above, an address signal supplied from the address designating section to the DRAM for writing, and data written at the address of the DRAM designated by the address signal. Detects that the buffer memory to store and the address signal supplied from the addressing unit to the DRAM for reading are already stored in the buffer memory, and reads the data stored in the buffer memory together with this address signal. A control circuit that modifies the sequence of generation of a given control signal for output as a result. DRAM controller with bets is provided.

[0007]

In this DRAM controller, when the address designating section supplies the address signal designating the write address to the DRAM, the address signal together with the data written at the address of the DRAM designated by the address signal. Stored in buffer memory. When the control circuit detects that the address signal supplied to the DRAM for reading is already stored in the buffer memory, the generation sequence of the predetermined control signal is changed and stored in the buffer memory together with this address signal. The read data can be output as a read result. This makes DR
Since the data can be obtained from the buffer memory without actually accessing the AM, the effective DRAM access time can be shortened.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A DRAM controller according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows the structure of this DRAM controller. The DRAM controller 20 is connected between the CPU 30 and the DRAM 40 in the computer system, and accesses the DRAM 40 under the control of the CPU 30. CPU 30 generates a read / write request, an address signal designating a write and read address, write data, etc. for controlling DRAM 20. D
The RAM 40 has the same structure as the conventional one shown in FIG.
Data is written and read at an address designated by an address signal from DRAM controller 20. DRAM controller 20 and CPU 3
0 operates in synchronization with the clock signal CLK supplied from the outside.

The DRAM controller 20 is an arbiter 2
1, refresh counter 22, multiplexer 23,
Timing generator 24, read / write buffer 2
6, and a buffer management circuit 26. CPU30
Are connected to the arbiter 21 via a data bus for transferring data and a control line for transferring a read / write request. The arbiter 21 arbitrates the data transfer based on the read / write request with respect to the refresh cycle of the DRAM 40 and supplies the read / write request to the refresh counter 22, the timing generator 24 and the buffer management circuit 26. The refresh counter 22 generates a refresh address signal during the period when the read / write request is not supplied from the arbiter 21, and supplies it to the multiplexer 23. The timing generator 24 responds to the read / write request supplied from the arbiter 21, and in a predetermined sequence for writing and reading, a row address strobe signal RAS bar, a column address strobe signal CAS bar, a write enable signal WE bar,
It generates a control signal such as a ready signal READY bar. These control signals are generated in synchronization with the clock signal CLK. The row address strobe signal RAS bar, the column address strobe signal CAS bar, and the write enable signal WE bar are supplied to the DRAM 40 as in the conventional case. The ready signal READY bar is a signal which falls when the access to the DRAM 40 is completed, and the CPU 3
0 is supplied. The read / write buffer 25 is the CPU 30
It stores the address signal supplied for writing and reading from and the write data supplied from CPU 30 through arbiter 21, and also stores the read data supplied from DRAM 40. The write data is supplied from read / write buffer 25 to DRAM 40. The read data is supplied from the read / write buffer 25 to the CPU 30 via the arbiter 21. The address signal is supplied from the read / write buffer 25 to the maniplexer 23. Multiplexer 23 selectively supplies one of a refresh address signal from refresh counter 22 and an address signal from read / write buffer 25 to DRAM 40.

In the DRAM controller 20, the read / write buffer 25 not only has a memory area for temporarily storing the data read from the DRAM 40, but also has a D area.
It has a plurality of memory areas for storing together an address signal designating a write address of RAM 40 and data written at an address of DRAM designated by the address signal. Buffer management circuit 26 manages address signals and data stored in read / write buffer 25 during writing and reading.

Next, the operation of the DRAM controller 20 will be described with reference to FIGS.

Here, the head address is specified by the address signal A1 and the blocks of the data D1-D4 are DRA'd.
Consider the case of writing to M40. When CPU 30 generates a write request and an address signal A1 and data D1-D4 in synchronization with clock signal CLK, address signal A1 is read / write buffer 25 and multiplexer 23.
Data D1-D4 are supplied to the DRAM 40 via the arbiter 21 and read / write buffer 25.
It is supplied to M40. On the other hand, the timing generator 2
4 is a row address strobe signal RAS bar, a column address strobe signal CAS bar, under the control of the arbiter 21.
And the write enable signal WE bar is lowered as shown in FIG. 2 and the ready signal READY bar is raised. The CPU 30 confirms that access to the DRAM 40 has started by the rise of the ready signal READY bar. The DRAM 40 operates as described in the conventional example shown in FIG. That is, the data D1 is latched by the data register 10 and supplied to the memory array 12 via the input / output circuit 11. On the other hand, the address signal is latched as row address signal RA1 and column address signal CA1 in row address register 14 and column address register 15, and responds to the fall of row address strobe signal RAS bar and column address strobe signal CAS bar, respectively. Decoder 16 and column decoder 1
7 is supplied. Row decoder 16 and column decoder 17
Are the address signal RA1 and the column address signal C, respectively.
The row and column of the memory array corresponding to A1 are selected, and the data D1 is stored in the memory cells for one word located in the selected row and column (address). The buffer management circuit 26 increments the address signal A1 by 1 every time the column address strobe signal CAS bar falls to update the column address signals as CA2, CA3, and CA4, and at the same time, the data D2, D3, and D.
4 is output from the read / write buffer 25. As a result, the data D1 to D4 are stored in order from the head address designated by the address signal.

As shown in FIG. 3, address signal A1 and data D1-D4 are stored in read / write buffer 25 under the control of buffer management circuit 26. The read / write buffer 25 stores such a combination of write address signal and data each time the DRAM 40 is accessed for writing. (When the read / write buffer 25 overflows, it is deleted in the oldest order.) The buffer management circuit 26 uses the data D1- as shown in FIG.
When the write of D4 is written in the read / write buffer 25, when there is a read request, the ready signal READ
The timing generator 24 is controlled to lower the Y bar. An address signal designating a read address is sent to the CPU 3 along with the fall of the ready signal READY bar.
When supplied from 0, the buffer management circuit 26 searches the read / write buffer 25 for this address signal, and accesses the DRAM 40 when it detects that this address signal is already stored in the read / write buffer 25. The sequence necessary for the
Timing generator 24 to make DY bar fall
Control. Further, the buffer management circuit 26 outputs the data stored in the read / write buffer 25 together with the above-mentioned address signal to the CPU 30 side as a read result.

DRAM controller 2 of the above-described embodiment
At 0, when the multiplexer 23 supplies the address signal designating the write address to the DRAM 40, this address signal is the DR designated by this address signal.
The data written to the address of AM 40 is stored in read / write buffer 25 together. The buffer management circuit 2 means that the address signal supplied to the DRAM 40 for reading is already stored in the read / write buffer 25.
When detected by 6, the generation sequence of the predetermined control signal is changed, and the data stored in read / write buffer 25 together with this address signal can be output as the read result. As a result, data can be obtained from the read / write buffer 25 without actually accessing the DRAM 40, so that the effective access time of the DRAM 40 can be shortened.

The present invention is not limited to the above-described embodiments, but can be variously modified without departing from the scope of the invention.

[0017]

According to the present invention, the access time of DRAM can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a DRAM controller according to an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the DRAM controller shown in FIG.

FIG. 3 is a time chart for explaining an operation of storing a write address signal and write data in the read / write buffer shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a conventional DRAM.

[Explanation of symbols]

20 ... DRAM controller, 21 ... Arbiter, 22 ...
Refresh counter, 23 ... Multiplexer, 24 ...
Timing generator, 25 ... Read / write buffer,
26 ... Buffer management circuit, 30 ... CPU, 40 ... DRA
M.

Claims (1)

[Claims] 1. An address signal for designating a write and read address is DRA during a period excluding a refresh cycle.
An address designating section supplied to M, a control signal generating section for generating a predetermined control signal in a sequence suitable for writing and reading, an address signal supplied to the DRAM for writing from the address designating section, and this address A buffer memory for storing a plurality of sets together with data written in the address of the DRAM designated by a signal; and an address signal supplied from the address designating unit to the DRAM for reading is already stored in the buffer memory. Control means for detecting that the data is stored and changing the generation sequence of the predetermined control signal so as to output the data stored in the buffer memory together with the address signal as a read result. DRAM controller.