JP2003044354A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller capable of transferring data at high speed by minimizing access frequencies to a memory. SOLUTION: A register with the same size as data bus width of the memory is provided, required pieces of data are successively selected from the register after storing the data (with the size of the data bus width of the memory) read from the memory in a single access in the register and outputted to a processor such as a CPU that issues a read request. Thus, only the absolute minimum accesses to the memory are required and the data is transferred at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device capable of accessing a memory at high speed.

[0002]

2. Description of the Related Art In a conventional memory control device, CP
The address output from the processing device such as U is directly connected to the memory for memory access. However, in this method, when reading a plurality of data, the arrival time of the address signal output by the CPU to the memory, the access time to the memory, the arrival time of the data to the CPU, etc.
Since it is added every time each data is read, there is a problem that the access speed is lowered. To solve this problem, there is a memory control device (disclosed in Japanese Patent Laid-Open No. 9-34827) that realizes high-speed memory access with a single memory bus.

As a conventional example, this memory control device will be briefly described. FIG. 13 is a block diagram showing the configuration of a conventional memory control device. In FIG. 13, 131 is a memory control device, 132 is a memory, and 133 is a CPU that accesses the memory. The memory control device 131 has an address counter unit 134 and a data holding unit 135. The address counter unit 134 accesses the memory 132 with the address received from the CPU 133, and updates the address in units of the data bus width of the CPU 133. The data holding unit 135 temporarily holds the data read from the memory 132 in units of the data bus width of the CPU 133.

When the CPU 133 reads data,
First, the address on the memory 132 of the data to start reading is loaded into the address counter unit 134. The address counter unit 134 uses this address to store in the memory 132.
To store the read data (for the data bus width of the CPU 133) in the data holding unit 135. CPU
While the 133 reads the data from the data holding unit 135, the address counter unit 134 updates the held address to the next address (address of the CPU 133 bus width ahead), accesses the memory 132, and reads. The stored data is stored in the data holding unit 135. Therefore, in the process of reading data for consecutive addresses from the same memory 132, by causing the data of the next address to be read while the CPU 133 is reading the data, the CPU 133 can continuously perform without waiting time required for memory access. Then you can read the data.

Here, the address is arbitrary information for specifying the address of the memory. The information includes absolute address information, relative address information, and a clock that increments or decrements the address starting from an arbitrary address.

Similarly, when writing data, data can be continuously written without waiting time required for memory access.

[0007]

However, in the conventional technique, for example, the data bus width of the CPU 133 is M bits and the data bus width of the memory 132 is N bits. When M <N, one memory is used. Even though N-bit data can be read by access, only M-bit data can be read, so the number of memory accesses is N
/ M times. Specifically, M = 8 bits,
When N = 64 bits, when reading 64-bit data, 64/8 = 8 memory accesses are required. As described above, by prefetching the data by using the data holding unit 135, although the data read time can be shortened, there is a problem that the power consumption is high because the number of accesses to the memory is large.

The present invention solves the above-mentioned conventional problems, and provides a memory control device capable of high-speed data transfer and highly efficient data transfer with a minimum number of memory accesses. To aim.

[0009]

In order to solve the above problems, the memory control device of the present invention has the following configuration.
According to a first aspect of the present invention, an input unit for inputting a read access request to a memory and an address, and m bits (m
Has an arbitrary positive integer) data bus, outputs a data interface section, an address processing section that generates and stores a memory address and a read data selection address based on the address, and an address of the memory. A memory address output unit that outputs the memory address to an input unit, and an n-bit (n is any positive integer satisfying m <n) data bus connected to the data interface unit of the memory, and the memory address A memory data interface unit for inputting the data read from the memory specified by 1., a read data storage register for dividing the n-bit data input by the memory data interface unit into m-bit units, and storing the read data. The read data selection add from the data stored in the data storage register A read data selector for transmitting m-bit data selected by a memory to the data interface unit, the memory address generated based on the address, and the memory unit already stored in the address processing unit. When the memory address is the same, the read data selector is generated based on the address from the data already stored in the read data storage register without performing read access to the memory. The memory control device is characterized in that m-bit data selected by the read data selection address is transmitted to the data interface unit.

According to a second aspect of the present invention, the input unit further inputs a write access request for the memory, and the memory data interface unit writes write data to the memory designated by the memory address.
When the memory address generated based on the address related to the write access request and the memory address related to the data already stored in the read data storage register are the same, the read data storage register The memory control device according to claim 1, wherein the write data is written.

According to a third aspect of the present invention, when the write data is written to the read data selection address of the read data storage register, the read data selector is configured to store the data stored in the read data storage register. 3. The memory control device according to claim 2, wherein the m-bit data selected by the read data selection address is transmitted to the data interface unit, and the data interface unit outputs the m-bit data. Is.

According to a fourth aspect of the invention, an input section for inputting a write access request and an address for the memory,
a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for inputting data; an address processing unit for generating and storing a memory address and a write data selection address based on the address; A memory address output unit that outputs the memory address to an address input unit of the memory; a write data storage register having an n-bit (n is an arbitrary positive integer satisfying m <n) register; and a write data storage register A write data selector for storing m-bit data input by the data interface unit in an m-bit register designated by the write data selection address, and an n-bit data bus connected to the data interface unit of the memory And input n-bit data from the write data storage register , A memory data interface unit that writes n-bit data to the memory specified by the memory address at one time, and the memory address generated based on the address is changed from a current value to a new value. When there is a change, the memory data interface unit inputs data from the write data storage register, writes data to the memory specified by the memory address of the value before the change, and then the write data selector, The memory control device is characterized in that the m-bit data input by the data interface unit is stored in the register designated by the write data selection address of the write data storage register.

According to a fifth aspect of the present invention, an input section for inputting a write access request and an address for the memory,
a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for inputting data; an address processing unit for generating and storing a memory address and a write data selection address based on the address; A memory address output unit that outputs the memory address to an address input unit of the memory; a write data storage register having an n-bit (n is an arbitrary positive integer satisfying m <n) register; and a write data storage register A write data selector for storing m-bit data input by the data interface unit in an m-bit register designated by the write data selection address, and an n-bit data bus connected to the data interface unit of the memory And input n-bit data from the write data storage register A memory data interface unit for writing n-bit data to the memory specified by the memory address at one time, and the write data selection address is a final address of the write data storage register, The write data selector is
After storing the m-bit data input by the data interface unit in the register at the final address of the write data storage register, the memory data interface unit inputs the data from the write data storage register and uses the memory address. A memory control device is characterized in that data is written in the specified memory.

According to a sixth aspect of the present invention, there is provided an input section for inputting a write access request and an address for the memory,
a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for inputting data; an address processing unit for generating and storing a memory address and a write data selection address based on the address; A memory address output unit that outputs the memory address to an address input unit of the memory; a write data storage register having an n-bit (n is an arbitrary positive integer satisfying m <n) register; and a write data storage register A write data selector for storing m-bit data input by the data interface unit in an m-bit register designated by the write data selection address, and an n-bit data bus connected to the data interface unit of the memory And input n-bit data from the write data storage register A memory data interface unit for writing n-bit data to the memory specified by the memory address at one time, and the write data selector writes the m-bit data input by the data interface unit to the write unit. The memory data interface unit has a counter that counts each time the data is stored in the data storage register. When the counter reaches a predetermined number of memory write data, the memory data interface unit inputs data from the write data storage register. A memory control device is characterized in that data is written in the memory specified by the memory address.

The invention according to claim 7 is the memory control device according to claim 6, wherein the number of data to be written in the memory can be set from the outside.

According to an eighth aspect of the present invention, there is provided an input section for inputting a write access request and an address for the memory,
a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for inputting data; an address processing unit for generating and storing a memory address and a write data selection address based on the address; A memory address output unit that outputs the memory address to an address input unit of the memory; a write data storage register having an n-bit (n is an arbitrary positive integer satisfying m <n) register; and a write data storage register A write data selector for storing m-bit data input by the data interface unit in an m-bit register designated by the write data selection address, and an n-bit data bus connected to the data interface unit of the memory And input n-bit data from the write data storage register A memory data interface unit for writing n-bit data to the memory specified by the memory address at one time, and the write data selector is activated after the data interface unit inputs m-bit data. If the data interface unit does not input new m-bit data before the timer measures a certain time, the memory data interface unit inputs data from the write data storage register. Write data to the memory specified by the memory address,
It is a memory control device characterized by the above.

The invention according to claim 9 is characterized in that the fixed time can be set from the outside.
The memory control device described in 1.

According to a tenth aspect of the present invention, there is provided an input unit for inputting a write access request for the memory, information of an access source and an address, and an m-bit (m is an arbitrary positive integer) data bus, A data interface section for inputting the address, an address processing section for generating and storing a memory address and a write data selection address based on the address, and a memory address output section for outputting the memory address to the address input section of the memory. , N-bit (n is an arbitrary positive integer satisfying m <n) register, and the write-data storage register, the m-bit register specified by the write-data selection address A write data selector for storing m-bit data input by the interface unit, and the memo Has a n-bit data bus connected to the data interface unit, inputs n-bit data from the write data storage register, and writes the n-bit data to the memory specified by the memory address at one time. A memory data interface unit, and the m-bit data input by the data interface unit to the register specified by the write data selection address of the write data storage register in response to the write access request from the access source. If an access request from another access source occurs during storage, the memory data interface unit inputs data from the write data storage register and stores the data in the memory specified by the memory address. Writing, a memory control device characterized by A. The “access request” may be either a read access request or a write access request.

According to an eleventh aspect of the present invention, the write data selector determines whether or not data is stored in the write data storage register based on the write data selection address in response to the write access request. When the memory data interface unit has a write storage register for storing the m-bit register unit of the register, the memory data interface unit inputs data from the write data storage register and writes data to the memory specified by the memory address. 7. The data of the write data storage register is written in the memory only for the write data selection address in which the data is stored, based on the write storage register. Item 8 or Claim 1
The memory control device according to claim 1.

According to a twelfth aspect of the present invention, there is further provided a control unit for making a decision to grant the access right to the memory according to a priority order of a predetermined access source, and the priority order is from outside. The memory control device according to claim 10, wherein the memory control device is settable.

The present invention has an effect that a high-speed data transfer to a memory can be realized, and further, a memory control device with a low power consumption can be realized in which the number of accesses to the memory is minimized.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments specifically showing the best mode for carrying out the present invention will be described below with reference to the drawings.

<< Embodiment 1 >> A memory control apparatus according to Embodiment 1 will be described with reference to FIGS. First Embodiment FIG. 1 is a block diagram showing the configuration of a memory control device according to a first embodiment of the present invention. In FIG. 1, 1 is a memory control device, 2 is a memory, and 3 is a first processing device. Memory controller 1
In the figure, 4 is an input unit, 5 is an address processing unit, 6 is a memory address output unit, 9 is a memory data interface unit, 10 is a read data storage register, 11 is a read data selector, and 12 is a data interface unit.
In the memory 2, 7 is an address input unit and 8 is a data interface unit.

The first processing device 3 is a control processing device such as a CPU that accesses the memory 2. The input unit 4 is the first
The read access request from the processing device 3 and the address to be read-accessed are input, and the address is output to the address processing unit 5. The address processing unit 5 generates a memory address and a read data selection address based on the address from the input unit 4, and outputs the memory address to the memory address output unit 6
The read data selection address is output to the read data selector 11. The memory address output unit 6 outputs the memory address from the address processing unit 5 to the address input unit 7. The memory 2 reads data from or writes data to the memory address input by the address input unit 7. The data interface unit 8 transfers data with the memory control device 1.

The memory data interface unit 9 inputs the read data from the data interface unit 8 of the memory 2 via the data bus (bus width is, for example, 64 bits). The read data storage register 10 is the memory 2
It is a register that can store the 64-bit data read from the device by dividing it into 8-bit data units. The size of the read data storage register 10 is the same as the bus width (64 bits) of the data bus connecting the memory data interface unit 9 and the data interface 8. The read data selector 11 selects 8 from the read data storage register 10 according to the read data selection address.
The bit data is output to the data interface unit 12. The data interface unit 12 outputs the data from the read data selector 11 to the first processing device 3 via the data bus (bus width is, for example, 8 bits).

FIG. 2 shows the data stored in the memory 2 in an array from the head address. The data array name is DT, and the array elements are divided into 1-byte units from the start address, and the order is DT0, DT1 ,.
(Same below). Further, the corresponding addresses on the memory 2 are shown in binary notation, and for example, the address of DT0 is "000_000". Here, the upper 3 bits indicate a memory address, and carry is carried for each width (64 bits) of the data bus of the memory 2. That is, D
The address of T8 is "001_000", and the address of DT16 is "010_000". The lower 3 bits indicate a read data selection address, and carry is carried in units of 1 byte. In other words, the address of DT9 is "001
_001 ”, the address of DT10 is“ 001_01 ”
It becomes 0 ".

A case where the first processing device 3 reads continuous 16-byte data from DT8 to DT23 of the memory 2 will be described. First, the first processing device 3
"00" as the address together with the read access request
1_000 ”is output to the input unit 4. The input unit 4 outputs the address“ 001_000 ”to the address processing unit 5.
At this time, since the upper 3 bits correspond to the memory address, the memory address is “001”. Here, it is assumed that the memory address processed by the address processing unit 5 last time is not "001". Then, the address processing unit 5 outputs “001” as the memory address to the memory 2 via the memory address output unit 6. Memory 2 has 8 addresses corresponding to the address.
The byte data (DT8 to DT15) is output from the data interface unit 8 to the memory interface unit 9.
The read data input by the memory data interface unit 9 are read data storage register 10 in order from DT8.
Nos. 0 to 7 are stored.

Next, the address processing unit 5 determines "001_0".
The lower 3 bits "000" of 00 "is output to the read data selector 11 as a read data selection address. The read data selector 11 is stored in the register (number 0) corresponding to" 000 "of the read data storage register 10. The data (DT8) stored therein is acquired and output to the first processing device 3 via the data interface unit 12. Next, the address processing unit 5 increments "000" by "001" as the read data selection address. To the read selector 11. Read data selector 1
1 is the data (DT) stored in the register (No. 1) corresponding to “001” of the read data storage register 10.
9) is acquired and output to the first processing device 3. After this,
In the same manner, the data (DT15) stored in the 7th register of the read data storage register 10 is output to the first processing device 3.

When the read data selection address is "111", it is incremented to "000", and the memory address is also incremented (carried) to 010. Therefore, the address processing unit 5 sets “010” as the memory address to the memory address output unit 6
To the memory 2 via. The memory 2 stores 8-byte data (DT16 to DT23) corresponding to the address.
Is output from the data interface unit 8 to the memory interface unit 9. The read data input by the memory data interface unit 9 is stored in the 0th to 7th registers of the read data storage register 10 in order from the DT 16. Next, the address processing unit 5 determines "010_00".
The lower 3 bits "000" of 0 "is output to the read data selector 11 as a read data selection address. The read data selector 11 reads the read data storage register 1
The data (DT16) stored in the register (0) corresponding to "000" of 0 is acquired and output to the first processing device 3 via the data interface unit 12. By the same procedure, the data (DT23) stored in the 7th register of the read data storage register 10 is output to the first processing device 3.

Next, the first processing unit 3 again sets DT2
The case of reading 1 will be described. First, the first processing device 3 outputs “010_101” as the address together with the read access request to the address processing unit 5 via the input unit 4. At this time, the memory address is "01
It becomes 0 ". Since this is the same as the memory address processed by the address processing unit 5 last time, the read request D
T21 is stored in the read data storage register 10. Therefore, the address processing unit 5 does not output the memory address to the memory address output unit 6 and outputs “0”.
The lower 3 bits "101" of 10_101 "is output to the read data selector 11 as a read data selection address. The read data selector 11 is a register (No. 5) corresponding to" 101 "of the read data storage register 10.
The data (DT21) stored in is acquired and output to the first processing device 3 via the data interface unit 12.

As described above, in the memory control device of the first embodiment, when reading data from the memory 2,
Data of the width of the data bus of the memory 2 (8 bytes) is read by one memory access and stored in the read data storage register 10. Therefore, for example, when reading 16 bytes of data, the memory 2 need only be accessed twice. Therefore, highly efficient memory access is possible with a small number of accesses to the memory 2.

Further, the address processing unit 5 automatically updates (increments) the read selection address, and based on the address, the read data selector 11 sequentially acquires data from the corresponding register of the read data storage register 10. Then, since the data is output to the first processing device 3,
High-speed reading of continuous data is possible.

Further, if there is a read request for the same memory address as the previously processed memory address,
Since the data is read from the read data storage register 10 without accessing the memory 2, the data can be read at high speed.

<< Second Embodiment >> A memory control device according to a second embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the memory control device according to the second embodiment of the present invention. The configuration of the memory control device of the second embodiment differs from the memory control device of the first embodiment (FIG. 1) in that a second processing device 31 is added. Otherwise they are the same. The same parts are designated by the same reference numerals and the description thereof will be omitted.
The second processing device 31 accesses the memory 2 similarly to the first processing device 3. The second processing device 31 outputs a write access request and its address to the input unit 4, writes data to the memory 2, and reads the data storage register 10.
Write data to.

First, the first processing unit 3 is
A read access request for data up to 7 is issued and the first embodiment is executed.
It is assumed that the data is read from the memory 2 by the procedure described in 1. After that, the second processing device 31 updates the DT6 in order to update the DT6 with the address "00".
0_110 "is output to the input unit 4. The input unit 4 outputs the address" 000_110 "to the address processing unit 5. At this time, the memory address becomes" 000 ", which is the first processing unit 3 first. However, the second processing device 31 writes new data (DT6) to the address “000 — 110” of the memory 2 and at the same time sets DT6 of the read data storage register 10 to the same. The 6th register to be stored is also updated with new data (DT6).

Since the contents of the read data storage register 10 have been updated, the memory control device 1 causes the first processing device 3 to again store the data stored in the 6th register of the read data storage register 10 ( Read out DT6).

As described above, in the memory control device of the second embodiment, the memory address is checked at the time of write access to the memory 2, and if this is the same as the memory address at the time of the previous read access, , Memory 2
Write data to the read data storage register 10
The same data is written to the corresponding register of. As a result, the data stored in the read data storage register 10 is always kept the latest.

When the second processing device 31 updates the register value of the read data storage register 10 after the first processing device 3 makes a read access to the memory 2, the first processing device 3 Read data storage register 1
By reloading the updated register data of 0,
The latest data can be read and the integrity of the data can be maintained.

In this embodiment, the write access processing to the memory 2 of the second processing device 31 is described with a simple structure, but during actual operation, the structure of the embodiment described later is adopted.

<< Third Embodiment >> A memory control device according to a third embodiment will be described with reference to FIGS. FIG. 4 is a block diagram showing the configuration of the memory control device according to the third embodiment of the present invention. In FIG. 4, 41 is a memory control device, 2 is a memory, and 3 is a first processing device. In the memory control device 41, 4 is an input unit, 5 is an address processing unit, 6 is a memory address output unit, 12 is a data interface unit, 42
Is a write data selector, 43 is a write data storage register, 44 is a write storage register, and 9 is a memory data interface unit. In the memory 2, 7 is an address input unit and 8 is a data interface unit.

The first processing device 3 is a control processing device such as a CPU that accesses the memory 2. The input unit 4 is the first
The write access request signal and the address for write access from the processing device 3 are input, and the address is output to the address processing unit 5. The address processing unit 5 generates a memory address and a write data selection address based on the address from the input unit 4, outputs the memory address to the memory address output unit 6, and outputs the write data selection address to the write data selector 42. . Memory address output unit 6
Outputs the memory address from the address processing unit 5 to the address input unit 7. The data interface unit 12 is
Write data output by the first processing device 3 (for example, 8
(Bit unit) is input and output to the write data selector 42.

The write data selector 42 stores the data output from the data interface section 12 in the corresponding register of the write data storage register 43 selected by the write data selection address. The write data storage register 43 stores the data to be output to the memory 2 in 8
It is a register that can be divided and stored in bit data units. The size of the write data storage register 43 is
It is the same as the bus width (for example, 64 bits) of the data bus connecting the memory data interface unit 9 and the data interface 8. Memory data interface unit 9
Outputs the write data to the memory 2 via the data bus. The address input unit 7 inputs the memory address from the memory address output unit 6. The memory 2 reads data from this address or writes data from this address. The data interface unit 8 transfers data with the memory control device 41. The write storage register 44 includes the write data storage register 43, numbers 0 to
It stores in which register No. 7 the data is stored.

The first processing unit 3 sends D to the memory 2.
The operation of writing 8-byte data of T8 to DT14 and DT16 will be described. First, the first processing device 3
Outputs to the input unit 4 the address "001_000" for writing the data of DT8 together with the write access request,
The write data (DT8) is transferred to the data interface unit 12
To the write data selector 42 via. The input unit 4 sends the address “001 — 000” to the address processing unit 5
Output to. The address processing unit 5 is "001_000".
The lower 3 bits “000” of the above are output to the write data selector 42 as the write data selection address. The write data selection address “000” corresponds to the 0th register of the write data storage register 43, and the write data selector 42 stores DT8 in this register.

Next, the first processing unit 3 outputs the DT 9 to the write data selector 42 via the data interface section 12. The address processing unit 5 increments the previous write data selection address “000” by “0”.
01 "is output as a new write data selection address to the write data selector 42. The write data selector 42 stores DT9 in the first register of the write data storage register 43 corresponding to" 001 ". Then, the data of DT10 to DT14 are stored in the second to sixth registers of the write data storage register 43.

Next, the first processor 3 receives the address "0".
10_000 "is output to the input unit 4, and the DT 16 is output to the write data selector 4 via the data interface unit 12.
Output to 2. The input unit 4 receives the address “010_00
0 "is output to the address processing unit 5. At this time, the memory address becomes" 010 ", which is different from the previously processed memory address" 001 ". Therefore, the address processing unit 5 causes the memory address" 001 "before the change. Is output to the memory 2 via the memory address output unit 6. Then, the write data (DT8 to DT14) stored in the register of the write data storage register 43 is output to the destination of the memory 2 via the memory data interface unit 9. Then, the DT 16 is stored in the 0th register of the write data storage register 43 by the same procedure as described above.

Further, when the write data stored in the register of the write data storage register 43 is written in the memory 2, by using the write storage register 44,
Of the write data storage register 43
Only the write data stored based on the write data selection address can be written in the memory 2. Figure 5
Under these circumstances, the internal states of the write storage register 44 and the write data storage register 43 are shown. In FIG. 5, the write data storage register 4
DT8 to DT14 of the 0th to 6th registers of 3 indicate the data stored by this write access. In the area corresponding to the 0th to 6th registers of the write storage register 44, a flag "1" indicating that writing has been completed is set. Since it is not written in the 7th register, "
The contents of the write storage register 44 are reset when the contents of the write data storage register 43 are output to the memory 2.

FIG. 6 is a flowchart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 when the memory address at the time of the write access request changes.

In step S61, it is determined whether or not a write access request is being made. If a write access request is being made, the process proceeds to step S62, and if a write access request is not being made, this processing ends. Step S62
Then, it is determined whether the memory address has changed.
If the memory address has changed, the process proceeds to step S63, and if it has not changed, the process proceeds to step S65. In step S63, the address processing unit 5 outputs the memory address before change to the memory 2 via the memory address output unit 6. In step S64, the write data stored in the write data storage register 43 is output to the memory 2 via the memory data interface unit 9.
In step S65, the data held in the write data selector 42 is stored in the corresponding register of the write data storage register 43 based on the write data selection address, and the process returns to step S61.

As described above, in the memory control device of the third embodiment, the write data output from the first processing device 3 is not directly transferred to the memory 2 but is stored in the register of the write data storage register 43 and the address is stored. Since the data stored in the register of the write data storage register 43 is written to the memory 2 according to the change of the memory address generated by the processing unit 5, the data can be written at high speed.
It is possible to minimize write access to.

Further, by using the write storage register 44, the first processing device 3 can write only the data for which the write access is requested into the memory 2. Therefore, unnecessary data is not accidentally overwritten.

<< Fourth Embodiment >> A memory control device according to a fourth embodiment will be described. The configuration of the memory control device according to the fourth embodiment is as follows.
This is the same as the memory control device (FIG. 4) of the third embodiment.

The first processing unit 3 makes D
An operation of writing 8-byte data of T9 to DT16 will be described. First, the first processing device 3 writes the address for writing the data of the DT 9 together with the write access request.
001_001 ”is output to the input unit 4, and write data (DT9) is output to the write data selector 42 via the data interface unit 12. The input unit 4 outputs the address“ 001_001 ”to the address processing unit 5.
The address processing unit 5 outputs the lower 3 bits “001” of “001 — 001” to the write data selector 42 as a write data selection address. The write data selection address “001” is 1 in the write data storage register 43.
Number register, and the write data selector 42 is
DT9 is stored in this register. Thereafter, the data of DT10 to DT15 are stored in the second to seventh registers of the write data storage register 43 in the same procedure.

Write data storage register 43 to DT15
When it is stored in the No. 7 register, the No. 7 register is the final register, and therefore the address processing unit 5 outputs the memory address “001” to the memory 2 via the memory address output unit 6. Then, the write data storage register 4
Write data stored in the register 3 (DT9 to DT1
5) is written to the area of the memory address output to the end of the memory 2 via the memory data interface unit 9. After that, the DT 16 is stored in the 0th register of the write data storage register 43 by the same procedure as described above.

As in the third embodiment, when the write data stored in the register of the write data storage register 43 is written in the memory 2, the write storage register 44 is used to output the data from the first processing unit 3. Only the write data stored in the write data storage register 43 based on the write data selection address can be written in the memory 2.

FIG. 7 shows an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 when the write data is stored in the last (7th) register of the write data storage register 43. It is a flowchart shown.

In step S71, it is determined whether or not a write access request is being made. If a write access request is being made, the process proceeds to step S72, and if a write access request is not being made, this processing ends. Step S72
Then, the data held in the write data selector 42 is stored in the corresponding register of the write data storage register 43 based on the write data selection address.
In step S73, it is determined whether the register of the write data storage register 43 storing the data is the final register. If it is the final register, the process proceeds to step S74, and if not, the process proceeds to step S71. In step S74, the address processing unit 5 outputs the memory address to the memory 2 via the memory address output unit 6. In step S75, the write data storage register 4
The write data stored in 3 is output to the memory 2 via the memory data interface unit 9, and the process returns to step S71.

As described above, in the memory control device according to the fourth embodiment, the write data output from the first processing device 3 is not directly transferred to the memory 2 but is stored in the register of the write data storage register 43 to be written. By storing the data in the final register of the data storage register 43, the data stored in the register of the write data storage register 43 is written in the memory 2, so that the data can be written at high speed and the write access to the memory 2 is minimized. It is possible.

<Fifth Embodiment> A memory control device according to a fifth embodiment will be described with reference to FIGS. FIG. 8 is a block diagram showing the configuration of the memory control device according to the fifth embodiment of the present invention. The same components as those in Embodiments 1 to 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 8, 81 is a memory control device, 82 is a write data selector, 83 is a counter, and 84 is an external setting unit. The write data selector 82 has a counter 83 in addition to the functions described in the fourth embodiment. The counter 83 is a counter that increments each time write data is stored in the register of the write data storage register 43 from the write data selector 82. The external setting unit 84 uses the counter 8
This is an input device that can externally set the "memory write data count" for comparison with the value of 3. The unit of data written to memory is bytes.

An operation of writing 3 bytes of data (DT17 to DT19) in a continuous area of the memory 2 will be described as an example. First, the external setting unit 84 is used to set the number of memory write data to 3 (bytes). First, the first
Processing device 3 of DT17 with the write access request.
The address "010_001" for writing the data is output to the input unit 4, and the write data (DT17) is output to the write data selector 82 via the data interface unit 12. The input unit 4 outputs the address “010 — 001” to the address processing unit 5. The address processing unit 5
The lower 3 bits “001” of 010 — 001 ”are output as the write data selection address to the write data selector 82. Since the write data selection address“ 001 ”corresponds to the first register of the write data storage register 43, the write data selector 82 is D in this register
Store T17.

At this time, 1 is set in the counter 83. Hereinafter, in the same procedure, the data of DT18 and DT19 are stored in the second and third registers of the write data storage register 43, and the counter 83 is incremented each time the data is stored. Then, the value of the counter 83 becomes 3, which coincides with the number of memory write data. Therefore, the address processing unit 5 outputs the memory address “010” to the memory 2 via the memory address output unit 6. Then, the write data (DT1 stored in the register of the write data storage register 43
7 to DT19) is written in the area of the memory address output earlier in the memory 2 via the memory data interface unit 9. The counter 83 is cleared to 0 at this point.

Here, similarly to the third embodiment, when the write data stored in the register of the write data storage register 43 is written to the memory 2, the write storage register 44 is used to output the data from the first processing unit 3. Then, only the write data stored in the write data storage register 43 based on the write data selection address can be written in the memory 2.

FIG. 9 is a flow chart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 when the value of the counter 83 becomes equal to or larger than the number of memory write data.

In step S91, it is determined whether or not a write access request is being made. If a write access request is being made, the process moves to step S92, and if a write access request is not being made, this processing ends. Step S92
Then, the data held in the write data selector 82 is stored in the corresponding register of the write data storage register 43 based on the write data selection address.
In step S93, the counter 83 is incremented. In step S94, the value of the counter 83 is compared with the number of memory write data. If the value of the counter 83 is equal to or more than the number of memory write data, step S9
If it is smaller than the number of memory write data, the process proceeds to step S91. In step S95,
The address processing unit 5 outputs the memory address to the memory 2 via the memory address output unit 6. Step S96
Then, the write data stored in the write data storage register 43 is output to the memory 2 via the memory data interface unit 9. In step S97, the counter 83
Is cleared to 0 and the process returns to step S91.

As described above, in the memory control device of the fifth embodiment, the number of data stored in the register of the write data storage register 43 is counted, and the number reaches the predetermined "memory write data number". In this case, since the data stored in the register of the write data storage register 43 is written in the memory 2, the data can be written in the memory 2 without writing to the final register. Also,
Since this "memory write data count" can be set externally, the size range of the write data storage register 43 (1
~ 8 bytes) can be adjusted arbitrarily.

<< Sixth Embodiment >> A memory control device according to a sixth embodiment will be described with reference to FIGS. Figure 10
It is a block diagram which shows the structure of the memory control apparatus in Example 6 of this invention. The same components as those in Embodiments 1 to 5 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 8, 101 is a memory control device, 102 is a write data selector, 103 is a timer, and 104 is an external setting unit. The write data selector 102 has a timer 103 in addition to the functions described in the fourth embodiment. Timer 10
3 starts when the write data is stored in the write data storage register 43, and measures the time until the next storage. The external setting unit 104 is an input device that can externally set a “memory writing interval” for comparison with the measured value of the timer 103. The unit of memory write interval is millisecond.

An operation of writing 3 bytes of data (DT17 to DT19) in a continuous area of the memory 2 will be described as an example. First, the memory writing interval is set to 100 (milliseconds) using the external setting unit 104. First, the first
Processing device 3 of DT17 with the write access request.
The address "010_001" to write the data of is written to the input unit 4, and the write data (DT17) is written to the write data selector 102 via the data interface unit 12.
Output to. The input unit 4 has the address “010_001”
Is output to the address processing unit 5. Address processing unit 5
Is the write data selector 1 using the lower 3 bits "010" of "010_001" as the write data selection address.
Output to 02. Write data selection address "001"
Corresponds to the first register of the write data storage register 43, so the write data selector 102 stores DT17 in this register.

At this time, the timer 103 is activated. After this, even if 100 milliseconds or more elapses, if the DT 18 is not input to the write data selector 102 and the data is not stored in the register of the write data storage register 43,
The address processing unit 5 outputs the memory address “010” to the memory 2 via the memory address output unit 6. Then, the write data (DT17) stored in the register of the write data storage register 43 is written to the area of the memory address output ahead of the memory 2 via the memory data interface unit 9.

Here, similarly to the third embodiment, when the write data stored in the register of the write data storage register 43 is written to the memory 2, the write storage register 44 is used to output the data from the first processing unit 3. Then, only the write data stored in the write data storage register 43 based on the write data selection address can be written in the memory 2.

FIG. 11 is a flow chart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 when the time measured by the timer 103 exceeds the memory write time interval. .

In step S101, it is determined whether or not a write access request is being made. If a write access request is being made, the process proceeds to step S102, and if a write access request is not being made, this processing ends. Step S
In 102, the measurement time of the timer 103 is compared with the memory writing interval.
If it is shorter than the memory writing interval, step S106.
Move to. In step S103, the timer 103 ends. In step S104, the address processing unit 5
The memory address is output to the memory 2 via the memory address output unit 6. In step S105, the write data stored in the write data storage register 43 is output to the memory 2 via the memory data interface unit 9, and the process returns to step S101. In step S106, the write data selector 102 is set to the write data storage register 4
It is determined whether or not there is data to be stored in 3. If there is data, the process proceeds to step S103, and if there is no data, the process proceeds to step S101. In step S107, the data held in the write data selector 102 is stored in the corresponding register of the write data storage register 43 based on the write data selection address. In step S108, the timer 103 is activated, and the process returns to step S101.

As described above, in the memory control device of the sixth embodiment, the timer 103 manages the time interval in which the write data is stored in the register of the write data storage register 43, so that the first processing device 3 executes the memory operation. Even when the write operation to the memory 2 is interrupted for some reason while accessing the memory 2, it is possible to prevent the data in the memory 2 from being updated for a long time.

<< Embodiment 7 >> A memory control apparatus according to Embodiment 7 will be described with reference to FIG. FIG. 12 is a block diagram showing the configuration of the memory control device according to the seventh embodiment of the present invention. The same components as those in Embodiments 1 to 6 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 12, 121 is a memory control device, 122 is a second processing device, 123 is a control unit, and 124 is an external setting unit.

The second processing device 122 accesses the memory 2 similarly to the first processing device 3. Second processing device 1
Reference numeral 22 outputs a write access request or read access request and its address to the input unit 4, outputs write data to the data interface unit 12, or inputs read data from the data interface unit 12. Control unit 1
When a memory access conflict occurs between a plurality of processing devices, 23 determines access right grant based on the priority of the access source. The external setting unit 124 is an input device that can externally set the “priority order” of access to the memory 2 for each processing device of each access source. The set value is a positive integer, and the processing device given a smaller value has a higher priority. In addition to the access request and address, the input unit 4 also inputs access source information.

An operation in which the first processing device 3 writes 8-byte data (DT24 to DT31) in a continuous area of the memory 2 will be described as an example. First, the external setting unit 124
"2" is set to the first processing device 3 and "1" is set to the second processing device 122 as the priority order by using.
(The priority is the second processing device 122> the first processing device 3) First, the first processing device 3 inputs the write access request, the access source information, and the address "011_000" into which the data of the DT 24 is written. 4, and the write data (DT24) is output to the write data selector 42 via the data interface unit 12. The input unit 4 outputs the address “011 — 000” to the address processing unit 5. The address processing unit 5 determines the lower 3 of “011_000”.
The bit “000” is output to the write data selector 42 as the write data selection address. The write data selection address “000” is the write data storage register 43.
Since the 0th register corresponds to, the write data selector 42 stores the DT 24 in this register. Less than,
By the same procedure, the data of DT25 to DT27 are stored in the first to third registers of the write data storage register 43.

At this point, the second processing unit 122 outputs the access request, address and access source information to the input unit 4. The input unit 4 outputs the access source information to the control unit 123. The control unit 123 determines that the second processing device 122 has a higher access priority from the priorities set earlier. Then, the address processing unit 5 outputs the memory address “011” to the memory 2 via the memory address output unit 6 before giving the access right to the second processing device 122. Then, the write data storage register 43
Data stored in the register of (DT24 to DT2
7) is written in the area of the memory address output to the end of the memory 2 via the memory data interface unit 9. After writing to the memory 2, the control unit 123 gives the second processing device 122 an access right to the memory 2.

Here, as in the third embodiment, when the write data stored in the register of the write data storage register 43 is written to the memory 2, the write storage register 44 is used to output the data from the first processing unit 3. However, only the write data stored in the write data storage register 43 based on the write data selection address can be written in the memory 2.

As described above, in the memory control device according to the seventh embodiment, the second processing device 122 makes an access request while the first processing device 3 is accessing the memory 2. In this case, the control unit 123 writes the write data stored in the register of the write data storage register 43 to the memory 2 and then the second processing unit 122.
By giving the access right to, even if the access to the memory 2 by a plurality of processing devices competes with each other, the control can be efficiently performed, and the memory 2 can store the latest data.

[0078]

As described above, according to the memory control device of the present invention, the data read register having the same size as the width of the data bus of the memory is provided, and when the data is read from the memory, the memory is read once. Data of the width of the data bus of the memory is read by access, and the data is stored in the data read register. By sequentially selecting the data from the data read register and outputting the data to the processor of the read request source, highly efficient memory read access with a small number of accesses to the memory is possible.

According to the memory control device of the present invention,
A data write register having the same size as the width of the data bus of the memory is provided, and write data output by a processing device such as a CPU is temporarily stored in the data write register. After that, the data write register is written to the memory with one access under certain conditions. Therefore,
Highly efficient memory write access is possible with a small number of accesses to the memory.

Further, according to the memory control device of the present invention,
The control unit that controls access to the memory enables efficient memory access even when there are conflicting access requests to the memory, and keeps the memory contents up to date.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory control device according to a first embodiment of the present invention.

FIG. 2 is a memory map of data stored in a memory 2.

FIG. 3 is a block diagram showing a configuration of a memory control device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a memory control device according to a third embodiment of the present invention.

FIG. 5 shows the internal state of the write storage register 44 and the write data storage register 43 in the third embodiment of the present invention.
It is a figure showing the internal state of.

FIG. 6 is a flowchart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 in Embodiment 3 of the present invention.

FIG. 7 is a flowchart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 in Embodiment 4 of the present invention.

FIG. 8 is a block diagram showing a configuration of a memory control device according to a fifth embodiment of the present invention.

FIG. 9 is a flowchart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 in the fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a memory control device according to a sixth embodiment of the present invention.

FIG. 11 is a flowchart showing an operation algorithm until the data stored in the write data storage register 43 is written in the memory 2 in Embodiment 6 of the present invention.

FIG. 12 is a block diagram showing a configuration of a memory control device according to a seventh embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a memory control device according to a conventional technique.

[Explanation of symbols]

1, 41, 81, 101, 121 memory control device 2,132 memory 3 First processing equipment 4 Input section 5 Address processing unit 6 Memory address output section 7 Address input section 8, 12 Data interface section 9 Memory data interface section 10 Read data storage register 11 Read data selector 31,122 Second processing device 42, 82, 102 write data selector 43 Write data storage register 44 write storage register 83 counter 84, 104, 124 External setting section 103 timer 123 control unit 133 CPU 134 Address counter section 135 data storage

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toru Aoki             1 Juden Matsushita, 1-8 Koshinmachi, Takamatsu City, Kagawa Prefecture             Child Industry Co., Ltd. (72) Inventor Okazaki Makoto             1 Juden Matsushita, 1-8 Koshinmachi, Takamatsu City, Kagawa Prefecture             Child Industry Co., Ltd. (72) Inventor Nobuaki Noguchi             1 Juden Matsushita, 1-8 Koshinmachi, Takamatsu City, Kagawa Prefecture             Child Industry Co., Ltd. F-term (reference) 5B060 CB01 DA02 MB08

Claims (12)

[Claims] 1. An input unit for inputting a read access request to a memory and an address, a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for outputting data, and based on the address. An address processing unit that generates and stores a memory address and a read data selection address, a memory address output unit that outputs the memory address to an address input unit of the memory, and an n connected to the data interface unit of the memory. A memory data interface unit that has a data bus of bits (n is an arbitrary positive integer satisfying m <n) and that inputs data read from the memory specified by the memory address; Read data class that stores n-bit data by dividing it into m-bit units Register and were selected from data stored in the read data storage register by the read data selection address m
A read data selector for transmitting bit data to the data interface unit, wherein the memory address generated based on the address is the same as the memory address already stored in the address processing unit. In this case, the read data selector does not perform read access to the memory, and the read data selector generates the read data selection address based on the address from the data already stored in the read data storage register. The memory control device, wherein m-bit data selected by is transmitted to the data interface unit. 2. The input unit further inputs a write access request to the memory, the memory data interface unit writes write data to the memory specified by the memory address, and the address related to the write access request. The write data is written to the read data storage register when the memory address generated based on the same is the same as the memory address related to the data already stored in the read data storage register. The memory control device according to claim 1, wherein: 3. When the write data is written to the read data selection address of the read data storage register, the read data selector selects the read data selection address from the data stored in the read data storage register. The memory control device according to claim 2, wherein the selected m-bit data is transmitted to the data interface unit, and the data interface unit outputs the m-bit data. 4. An input unit for inputting a write access request to a memory and an address, a data interface unit for inputting data having an m-bit (m is an arbitrary positive integer) data bus, and an address unit based on the address. An address processing unit that generates and stores a memory address and a write data selection address, a memory address output unit that outputs the memory address to an address input unit of the memory, and n bits (n satisfies m <n A write data storage register having a positive integer) register and an m-bit register designated by the write data selection address of the write data storage register to store the m-bit data input by the data interface unit. N connected to the write data selector and the data interface unit of the memory A memory data interface unit that has a bit data bus, inputs n-bit data from the write data storage register, and writes the n-bit data to the memory specified by the memory address at one time. When the memory address generated based on the address changes from a current value to a new value, the memory data interface unit inputs data from the write data storage register and stores the value before the change. Data is written in the memory specified by a memory address, and then the write data selector registers the m-bit data input by the data interface unit by the register specified by the write data selection address of the write data storage register. A memory control device, characterized in that 5. An input unit for inputting a write access request to a memory and an address, a data interface unit for inputting data having an m-bit (m is an arbitrary positive integer) data bus, and an address unit based on the address. An address processing unit that generates and stores a memory address and a write data selection address, a memory address output unit that outputs the memory address to an address input unit of the memory, and n bits (n satisfies m <n A write data storage register having a positive integer) register and an m-bit register designated by the write data selection address of the write data storage register to store the m-bit data input by the data interface unit. N connected to the write data selector and the data interface unit of the memory A memory data interface unit that has a bit data bus, inputs n-bit data from the write data storage register, and writes the n-bit data to the memory specified by the memory address at one time. If the write data selection address is the final address of the write data storage register, the write data selector transfers the m-bit data input by the data interface unit to the final address register of the write data storage register. After storing, the memory data interface unit inputs data from the write data storage register and writes the data in the memory specified by the memory address. 6. An input unit for inputting a write access request to a memory and an address, a data interface unit for inputting data having an m-bit (m is an arbitrary positive integer) data bus, and an address unit based on the address. An address processing unit that generates and stores a memory address and a write data selection address, a memory address output unit that outputs the memory address to an address input unit of the memory, and n bits (n satisfies m <n A write data storage register having a positive integer) register and an m-bit register designated by the write data selection address of the write data storage register to store the m-bit data input by the data interface unit. N connected to the write data selector and the data interface unit of the memory A memory data interface unit that has a bit data bus, inputs n-bit data from the write data storage register, and writes the n-bit data to the memory specified by the memory address at one time. The write data selector has a counter that counts each time the m-bit data input by the data interface unit is stored in the write data storage register, and the counter reaches a predetermined number of memory write data. In this case, the memory data interface unit inputs data from the write data storage register and writes the data in the memory specified by the memory address. 7. The memory control device according to claim 6, wherein the number of data to be written in the memory can be set from the outside. 8. An input unit for inputting a write access request to a memory and an address, a data interface unit for inputting data having an m-bit (m is an arbitrary positive integer) data bus, and an address unit based on the address. An address processing unit that generates and stores a memory address and a write data selection address, a memory address output unit that outputs the memory address to an address input unit of the memory, and n bits (n satisfies m <n A write data storage register having a positive integer) register and an m-bit register designated by the write data selection address of the write data storage register to store the m-bit data input by the data interface unit. N connected to the write data selector and the data interface unit of the memory A memory data interface unit that has a bit data bus, inputs n-bit data from the write data storage register, and writes the n-bit data to the memory specified by the memory address at one time. The write data selector has a timer that is activated after the data interface unit inputs m-bit data, and the data interface unit outputs new m-bit data by the time the timer measures a certain time. When not inputting, the memory data interface unit inputs data from the write data storage register and writes the data in the memory specified by the memory address. 9. The memory control device according to claim 8, wherein the fixed time can be set from outside. 10. An input unit for inputting a write access request to a memory, information of an access source, and an address, and a data interface unit having an m-bit (m is an arbitrary positive integer) data bus for inputting data. An address processing unit that generates and stores a memory address and a write data selection address based on the address, a memory address output unit that outputs the memory address to an address input unit of the memory, and n bits (n is m A write data storage register having a register of <any positive integer satisfying n, and an m-bit register input by the data interface unit to an m-bit register designated by the write data selection address of the write data storage register. Write data selector for storing the data of the memory and the data interface of the memory. A memory having an n-bit data bus connected to the source section, inputting n-bit data from the write data storage register, and writing the n-bit data to the memory specified by the memory address at one time A data interface unit, and stores m-bit data input by the data interface unit in the register specified by the write data selection address of the write data storage register in response to the write access request from an access source. If an access request from another access source occurs during the operation, the memory data interface unit inputs data from the write data storage register and writes the data to the memory specified by the memory address. A memory control device characterized by the above. 11. The write data selector determines whether or not data is stored in the write data storage register based on the write data selection address in response to the write access request, in the m-bit register of the write data storage register. A write storage register for storing in units, the memory data interface unit inputs the data from the write data storage register and writes the data in the memory specified by the memory address, 5. Based on the above, the data of the write data storage register is written in the memory only for the write data selection address in which the data is stored.
The memory control device according to claim 6, 8, or 10. 12. The system further comprises a control unit that determines whether to grant the access right to the memory according to a predetermined priority order of access sources, and the priority order can be set from the outside. The memory control device according to claim 10.