JP2011090697A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance throughput of an external memory bus to a case when a continuous read with data size smaller than data bus width of the external memory, etc. is heavily used. <P>SOLUTION: A semiconductor device includes: a memory control part 10 which can control the external memory 61 having a plurality of banks by synchronizing it with a clock; buses connected to the memory control part; and a circuit module which is provided corresponding to the buses and can instruct memory access. When burst read is requested in access data size smaller than the number of bits in the buses from the circuit module, the memory control part 10 continuously issues the read request to the external memory 61 by the number of times smaller than the number of bursts in the requested burst read. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a memory control unit capable of controlling an external memory with clock synchronization, and relates to a technique effectively applied to, for example, a microcontroller including an interface controller of a DDR (double data rate) memory.

  Synchronous memories that are operated in synchronization with a clock such as SDRAM (Synchronous Dynamic Random Access Memory) are widely used for graphic frame buffers, CPU main memories, and the like. For example, an SDRAM has a plurality of memory banks, and each memory bank has an address decoder, a memory array, a sense amplifier array, etc., and can be controlled independently, and the plurality of memory banks are operated in a pipeline manner. Thus, high-speed access operation is enabled. In particular, the DDR type synchronous memory performs data input / output with the outside in synchronization with both rising and falling edges of the clock, and is further increased in speed compared with the SDR (single data rate) synchronous memory. Patent Document 1 describes a multi-bank SDRAM. Patent Document 2 describes a system controller equipped with a graphic port and an SDRAM controller. The synchronous memory is connected to such a system controller and controlled for access.

Japanese Patent Laid-Open No. 10-189889 Japanese Unexamined Patent Publication No. 2000-132503 (FIG. 6)

  The inventor has studied a DDR memory controller that incorporates a CPU (central processing unit) and a graphic module for accessing an externally connected DDR memory and controls access to the DDR memory. For example, in the case of a DDR memory having a 32-bit data input / output terminal, the data that can be read in one clock cycle is 64 bits, which is twice the bus width, but the access subject is a word or longword access data size. When access is requested, most of the data read from the DDR memory in one clock cycle becomes data outside the access request and is invalidated. When the access addresses are continuous, it is highly possible that the invalid data includes data related to the subsequent access request. For example, when the access data size of a burst access request from a CPU or the like is smaller than the access data size by one clock cycle, if memory access of one clock cycle is repeated for the specified number of burst accesses, even if the read is repeated More data is invalidated. Thus, it has been clarified that when the access data size required for the memory controller is smaller than the unit access data size of the external memory, the bus throughput deteriorates.

  In some cases, the cache memory of the CPU can be effective in reducing the bus throughput or data throughput of the external memory. In such a CPU cache memory, the cache miss penalty processing for performing entry or cache line replacement due to a cache miss is relatively heavy, so it is important to target repeatedly used programs and data as cache targets. Become. Considering this, CPU cache memory is used for data that is rarely used repeatedly, such as drawing data and image data for the frame buffer, or for subroutine programs and control data that are not frequently used. It would be a good idea not to be eligible for cash.

  An object of the present invention is to provide a semiconductor device capable of improving the bus throughput or data throughput of an external memory bus in the case where continuous read or the like with a data size smaller than the data bus width of the external memory is frequently used. There is.

  Another object of the present invention is to provide a semiconductor device capable of improving bus throughput or data throughput in response to data or program access requests that are not frequently repeatedly accessed and difficult to be cached by a CPU cache memory. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor device according to the present invention includes a memory control unit capable of controlling an external memory having a plurality of independently controllable banks in synchronization with a clock, and a plurality of buses connected to the memory control unit. And a circuit module provided corresponding to each of the plurality of buses and capable of instructing memory access. The memory control unit has a bank cache as a storage area corresponding to each bank of the external memory. The bank cache can store a part of data of the bank using the address of the corresponding bank as an associative key. As a result, when continuous reading is performed with a data size smaller than the data bus width of the external memory, the data read from the external memory is stored in the bank cache and stored without being invalidated. Therefore, the bus throughput or data throughput of the external memory bus can be improved. Since the bank caches corresponding to the banks of the external memory are provided, it is possible to support the holding of data from each bank even for continuous data reading by operating a plurality of banks in a pipeline manner.

  In a specific form of the present invention, a CPU is provided as one circuit module, and a cache memory is provided between the CPU and one bus, and the memory control unit is configured to store the cache memory in the cache memory. The bona fide bank cache is validated for access requests to the target area. As a result, for data and programs that are not frequently accessed repeatedly and are difficult to be cached by the CPU cache memory, such that the cache memory is subject to a large burden due to cache miss penalties. The bus throughput or the data throughput can be improved. Further, there is no need for complicated control for maintaining coherency as in the case where both the CPU cache and the bank cache are cached.

  In still another specific form of the invention, the external memory is a memory that is DDR-operated with respect to the clock. In the DDR operation, twice as many read data can be obtained per unit clock cycle as in the SDR operation. By using a bank cache for the read data, the read data throughput to the external memory can be further improved. Can do. At this time, the bank cache has a data storage unit corresponding to a data size accessible to one bank of the external memory in one cycle of the clock. It is possible to contribute to simplification of the cache control while guaranteeing the read data latch function by the DDR operation. For this bank cache configuration, the bank cache is invalidated in response to a read access instruction in which the total access data size by burst access by a single read access instruction to the external memory exceeds the data size of the data storage unit. This can contribute to further simplification of cache control. The number of parallel data bits on the bus is preferably equal to the data size obtained by DDR operation of the external memory in one cycle of the clock. The size of the data storage unit of each bank cache matches the size of the bus, which is convenient for access control.

  [2] A semiconductor device according to another aspect of the present invention includes a memory control unit capable of controlling an external memory having a plurality of banks in synchronization with a clock, and a plurality of connected to the memory control unit, as in the above-described invention. And a circuit module provided corresponding to each of the plurality of buses and capable of instructing memory access. And it has CPU as one circuit module and has the cache memory arrange | positioned between said CPU and one bus | bath. At this time, the memory control unit has a bank cache corresponding to each bank of the external memory, and the bank cache can store a part of data of the bank by using the address of the corresponding bank as an associative key. . When the bank cache is enabled for an access request to the cache non-target area of the cache memory and the bank cache is enabled for the external memory read access request from the circuit module, the read access is transferred to the bank cache. On the other hand, in the case of an associative miss, a read command for reading the data related to the associative miss from the external memory is issued, and the read data is stored in the corresponding bank cache and as data for the read access request source. Output. As a result, when continuous reading is performed with a data size smaller than the data bus width of the external memory, the data once read from the external memory can be stored in the bank cache and used without waste. The bus throughput or data throughput can be improved. Since the bank caches corresponding to the banks of the external memory are provided, it is possible to support the holding of data from each bank even for continuous data reading by operating a plurality of banks in a pipeline manner. For data and programs that are difficult to be cached by the CPU cache memory, if the cache memory is not frequently repeatedly accessed and is subject to a large burden due to cache miss penalties, the bus throughput or Data throughput can be improved.

  In a specific form of the invention, when the memory control unit validates the bank cache in response to a write access request for the external memory from the circuit module, the write access causes an associative hit to the bank cache. In this case, the cache data related to the associative hit is invalidated, and a write command for the write data related to the associative hit is issued to the external memory. This eliminates the need for complicated control to maintain coherency between the bank cache and the external memory. The memory control unit is connected to a plurality of buses and controls access to the external memory in response to access requests from a plurality of circuit modules, and all access requests from any bus are subject to caching. However, if this is taken into consideration and the coherency between the bank cache and the external memory is maintained, complicated control is required.

  When the write access is an associative miss for the bank cache, a data write command related to the associative miss may be issued to the external memory.

  In a more specific embodiment of the present invention, a graphic module for three-dimensional drawing is connected as a circuit module to another one bus, and a graphic module for two-dimensional drawing as a circuit module is connected to another one bus. A display controller is connected as a circuit module to the other one bus.

  In another specific form of the present invention, a bus for enabling the bank cache and a bus for disabling the bank cache are mixed for an access request. For example, in the case of access by the graphic module, it is efficient to continuously read data arranged at consecutive addresses on the same raster with the maximum number of bursts, and the data size exceeds the size of the bank cache of the access data size of 1 clock cycle. Therefore, such buses should not be cached, and the data size for saving and restoring to the stack area is consistent with the data processing unit such as the CPU, such as 16 bits or 32 bits. This is because the bus used for data transfer should be cached.

  In another specific form of the present invention, when a bus ID is assigned to each bus, the memory control unit is configured to enable the bus ID of the bus to be invalidated and the bus ID of the bus to be invalidated for an access request. It is preferable to have a circuit that defines The bus ID is included in the access request and is used for routing of the access request and a response thereto. The circuit that defines the bus ID may be fixedly configured with hard-wired logic, or may be configured to be programmable with a control register. If the cache validity / invalidity can be determined for each bus for transmitting an access request to the memory control circuit, it contributes to the improvement of the bank cache hit rate.

  In another specific form of the present invention, when an access request is received from a circuit module, the memory control unit may determine whether the bank cache is valid or invalid according to an access data size associated therewith. If the cache valid / invalid can be determined according to the access data size accompanying the access request to the memory control circuit, it contributes to the improvement of the bank cache hit rate. The memory control unit includes a circuit that defines an access data size for determining whether the bank cache is valid or invalid. Such a circuit that defines the access data size may be fixedly configured by hard-wired logic, or may be configured to be programmable by a control register.

  [3] A semiconductor device according to still another aspect of the present invention includes a memory control unit capable of controlling an external memory having a plurality of banks in synchronization with a clock, a bus connected to the memory control unit, and the bus And a circuit module capable of instructing memory access, wherein the memory control unit has a bank cache corresponding to each bank of the external memory, and the bank cache A part of the data of the bank can be stored using the address as an associative key. The bus is a split transaction type bus. In a split transaction type bus, an access response circuit receives a request packet from an access request circuit and returns a response packet in response to the request to the access request circuit, and includes a request packet and a response packet. A series of processes (transactions) can be identified from other transactions by a transaction ID unique to the access request circuit. When the memory control unit returns a plurality of read data in response to a plurality of continuous read access instructions from the circuit module to the external memory to the bus, the memory control unit corresponds to a read access instruction order from the circuit module. Reordering that changes the output order of read data to the read access request source is possible. This is possible because a transaction can be identified as another transaction by its unique transaction ID.

  If it is necessary to return responses in the order of access requests, in short, if the above reordering is not performed, the response data of the access request hit in the bank cache is more than the response data of the access request to which the bank cache is associatively missed. Although it can be acquired quickly, it is necessary to wait until the latter response is received in order to return the former response to the access request source, and as a result, the data throughput of the system is deteriorated. In the above-mentioned means, the read access request from the bank cache in which the associative hit is made precedes the read data from the external memory related to the associative miss of the bank cache with respect to the read access instruction order from the circuit module. It can be output as original data. No extra waiting is required to receive a response to the access request.

  [4] A semiconductor device according to still another aspect of the present invention includes a memory control unit capable of controlling an external memory having a plurality of banks in synchronization with a clock, a bus connected to the memory control unit, and the bus A circuit module provided correspondingly and capable of instructing memory access, wherein the memory control unit is configured to request the burst read when an access data size smaller than the number of bits of the bus is requested from the circuit module. The read request can be continuously issued to the external memory with a smaller number of burst reads. In other words, in response to an access request from the circuit module in which the burst number is specified with an access data size smaller than the number of bits of the bus, all data received in one read request to the external memory is validated. Issue read requests multiple times in succession. In short, the bus control unit merges read requests issued to the external memory in response to access requests from the circuit modules. For example, when the number of bits of the bus is readable from the external memory in one clock cycle and the number of data bits is equal, the access data size of the burst read request from the circuit module is 1 / n of the number of bits of the bus At this time, the bus control unit merges the read request of the n circuit with respect to the external memory into one read request. As a result, the number of read requests issued by the bus control unit to the external memory is reduced to 1 / n, and the bus control unit validates all bits of the read data from the external memory every time, and the circuit module receives the requested access. Returns a response for each data size. As a result, the bus throughput of the external memory can be improved, the rate of access contention between circuit modules for the external memory is reduced, and the data throughput of the system is improved.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to improve the bus throughput or data throughput of the external memory bus as compared to the case where continuous read with a data size smaller than the data bus width of the external memory is frequently used.

  The bus throughput or the data throughput can be improved in response to data or program access requests that are not frequently repeatedly accessed and are not easily cached by the CPU cache memory.

It is a block diagram which illustrates the image processor concerning an example of the present invention. It is a schematic block diagram of a DDR-SDRAM. It is a block diagram of a DDR-SDRAM controller. It is explanatory drawing which shows the data structure of the cache entry of a bank cache. It is a control processing flow at the time of a bank cache hit and miss by the DDR controller. It is a timing chart which shows the typical access timing of DDR-SDRAM. 10 is a timing chart when a read access with a 16-bit access data size is requested three times for a continuous address from the super highway bus. 8 is a timing chart when the same access request as in FIG. 7 is operated without using a bank cache. 5 is a timing chart showing an operation in which a DDR-SDRAM controller reorders bank cache hit data and returns it to an access request source in response to a burst read and single read access request from a super highway bus. FIG. 10 is a timing chart showing an operation of a comparative example in which a single read according to S1 of FIG. It is a flowchart which shows the read access flow from a graphic module to DDR-SDRAM. It is a flowchart which shows the read access operation | movement from a graphic module to DDR-SDRAM. 10 is a timing chart showing an operation when a read access request is not merged when a read access request with a 32-bit access data size and a burst length of 8 is made from the graphic module. This is a timing church when a refresh cycle for the DDR-SDRAM occurs midway with respect to FIG. 6 is a timing chart when issuing a read command by merging access requests. It is a flowchart which shows operation | movement when there exists a read access request | requirement to DDR-SDRAM from two graphic modules. It is a flowchart which shows the operation timing when not merging access requests when there are a plurality of modules requesting memory access. It is a flowchart which shows the operation | movement timing in the case of merging an access request when there are two or more modules which request a memory access. It is a flowchart which shows the operation | movement timing when not merging an access request when the operating frequency of a graphic module is higher than the operating frequency of DDR-SDRAM. It is a flowchart which illustrates the operation | movement timing in the case of merging an access request, when the operation frequency of a graphic module is higher than the operation frequency of DDR-SDRAM.

<Image processor>
FIG. 1 illustrates an image processor according to an example of the present invention. The image processor 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a complementary MOS (CMOS) integrated circuit manufacturing technique, and is used for car navigation, for example. It has necessary image processing and sound processing functions, and a DDR-SDRAM (double data rate synchronous dynamic random access memory) interface and the like.

  The image processor 1 has a processor core 2 and a clock generation circuit (CPG) 3. A super highway bus (SHB) 4 connected to the processor core 2 has a bus bridge circuit (BBRG) 5, a direct memory access controller (DMAC). ) 6, 3D engine (3DGFC) 7 that performs 3D image processing such as 3D image rendering processing, RAM 8, interrupt controller (INTCF) 9, and DDR-SDRAM controller (NCEMI) 10 as a memory control unit are connected. . The processor core 2 includes a central processing unit (CPU) 11 that executes a fetched instruction, a floating point arithmetic unit (FPU) 12, and a cache memory unit / memory management unit (CACH / MMU) 13. The cache memory unit 13 (CACH) has an associative memory structure that holds data and programs held in the memory and input / output registers in the cache target address area so that they can be replaced according to their access frequency. A clock generation circuit (CPG) 3 supplies a clock CLKi for synchronous operation to each part of the image processor 1. The cache memory unit 13 (CACH) is also simply referred to as CPU cache memory 13 (CACH).

  The DDR-SDRAM 61 connected to the DDR-SDRAM controller (NCEMI) 10 is used as a main memory or a frame buffer of the CPU 11. A first peripheral bus (PBF) 21, a second peripheral bus (PBS) 22 and an external bus (EXB) 23 are connected to the bus bridge circuit 5. The 3D engine 7 is connected to a DDR-SDRAM controller (NCEMI) 10 via a 3D bus (3DB) 24. A graphic bus (GFB) 20 is further connected to the DDR-SDRAM controller (NCEMI) 10. The DDR-SDRAM controller (NCEMI) 10 is externally coupled to a DDR memory bus (MRB) 25.

  The super highway bus 4 is a multi-master bus or a split transaction type bus. Each circuit module connected to the super highway bus 4 has a master port and a slave port independently, and a read / write transfer request from its own circuit module is issued as a request packet from the master port, and from other circuit modules. As a result of the arbitration in the bus arbitration circuit, the transfer request is notified to the slave port as a request packet, and the bus transaction is executed. The bus arbitration circuit is arranged in the middle of the super highway bus 4 although not particularly shown. With this multi-master bus control system, the super highway bus 4 can transfer all combinations between circuit modules connected thereto. For example, transfer between the CPU 11 and the DMAC 6, the bus bridge circuit 5 and the NCEMI 10, and the bus bridge circuit 5 and the CPU 11 can be performed.

  The 3DGFC 7 connected to the 3D bus 24 receives an image processing command such as a 3D drawing command from the CPU 11 via the super highway bus 4 and performs 3D drawing processing. Drawing is performed on the frame buffer area of the DDR-SDRAM 61 (not shown) via the NCEMI 10.

  The graphic bus 20 includes a 2D engine (2DGFC) 30 for performing two-dimensional image processing, a display control circuit (DU) 31, a serial interface circuit (IEEE1394) 32, a color space conversion unit (YUV) 33, an AT attachment packet interface circuit ( An ATAPI) 34, a video signal input circuit (VIN) 35, and a universal serial bus function controller (USB) 36 are connected. The display control circuit 31 sequentially reads the image data drawn in the frame buffer area, and performs control to output to the raster scan type display in synchronization with the display timing. The video signal input circuit 35 inputs a digital video signal. The ATAPI 34 performs interface control with a disk drive device such as a hard disk drive, a DVD or a CD-ROM drive.

  The graphic bus 20 is a split transaction type bus like the super highway bus 4, but one of the source and destination of the bus is always the DDR-SDRAM controller 10. That is, the bus bridge circuit 5, 2 DGFC 30, DU 31, serial interface circuit 32, YUV 33, ATAPI 34, VIN 35, and USB 36 perform only transfer with the DDR-SDRAM 61 via the DDR-SDRAM interface 10. These image system circuit modules 30 need to temporarily store data in the DDR-SDRAM 61 after performing image processing in their circuit blocks, or transfer the data in the DDR-SDRAM 61 to the DU 31. The transfer is always performed via the DDR-SDRAM controller 10.

  The INTC 37, 2DGFC 30, DU 31, and serial interface circuit 32 are connected to the first peripheral bus 21.

  The second peripheral bus 22 includes an asynchronous serial communication interface circuit (SCIF) 40, a pulse width change timer (PWM) 41, an IEC60958 audio controller (SPDIF) 42, a source rate converter (SRC) 43, and a GPS (Global Positioning System). A search / tracking engine (GPS) 44 and the clock generation circuit 3 are connected.

  The first peripheral bus 21 and the second peripheral bus 22 are single master 32-bit buses, and the bus bridge circuit 5 is a bus master.

  The CPU 11 is a 32-bit CPU, for example, and the data processing unit is 32 bits. Since the CPU 11 has a superscalar structure that issues a plurality of instructions in one cycle, it has an instruction processing execution capability that is approximately twice the operating frequency. That is, the CPU 11 has a so-called 2-way superscalar structure. In response to this, the super highway bus 4 is a 64-bit bus. Therefore, the CPU 11 can execute two instructions in parallel to prepare two sets of 32-bit data, and transfer the prepared two sets of 64-bit data to the super highway bus 4 in one bus cycle. Further, the CPU 11 can read 64-bit data from the super highway bus 4 in one bus cycle, and can perform arithmetic processing on the read lower 32 bits and upper 32 bits separately in parallel.

  FIG. 2 shows a schematic block of the DDR-SDRAM 61. The DDR-SDRAM 61 has four memory banks BNK0 to BNK3, although not particularly limited. Each of the memory banks BNK0 to BNK3 includes a memory array (ARY) 62, a row address decoder (RDEC) 63, a sense amplifier array (SAA) 64, a column input / output circuit (CIO) 65, and a column address decoder (CDEC) 66. Each memory array 62 includes a large number of dynamic memory cells arranged in a matrix, the selection terminals of the memory cells are connected to word lines for each column, and the data input / output terminals of the memory cells are folded back through a sense amplifier. The other complementary bit line is coupled.

  The row address decoder 63 is supplied with an internal row address from a row address buffer / refresh counter (RABF / RCUNT) 67. The column address decoder 66 is supplied with an internal column address from a column address buffer / burst counter (CABF / BCUNT) 68. The internal row address and internal column address are supplied to the selectively activated memory bank. The column input / output circuit 65 is selectively connected to a data input / output buffer (DIOB) 71 via a data control logic (DCLGC) 70 so that read data can be output and write data can be input in units of memory banks. The data input / output buffer 71 is connected to 32-bit data input / output terminals DQ0 to DQ31.

  The DDR-SDRAM 61 has, for example, 15-bit address input terminals A0 to A14. The row address signal and bank selection signal supplied to the address input terminals A0 to A14 in the form of an address multiplex are supplied to the row address buffer, the column address signal is supplied to the column address buffer 7, and the mode register setting information is supplied to the timing controller. The four memory banks BNK0 to BNK3 are enabled (bank active) according to the logic value of the 2-bit bank selection signal. The operations of the memory banks BNK0 to BNK3 can be controlled independently.

  Operation control of the DDR-SDRAM 61 is performed by a timing controller (TCNT) 72. The timing controller 72 includes clock signals CLK and / CLK, clock enable signal CKE, chip select signal / CS, column address strobe signal / CAS, row address strobe signal / RAS, write enable signal / WE, and data strobe signal DQS. The mode register setting information is input together with the external control signal. The operation of the DDR-SDRAM 61 is determined by a command defined by a combination of the states of these input signals, and the timing controller 72 has control logic for forming an internal timing signal corresponding to the operation instructed by the command.

  The clock signals CLK and / CLK are used as a master clock of the DDR-SDRAM 61, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK. The chip select signal / CS instructs the start of the command input cycle by its low level. Each signal of / RAS, / CAS, / WE is a signal for defining a command cycle. The data strobe signal DQS as an input signal is supplied from the outside as a write strobe signal at the time of a write operation, and defines the timing for determining write data. The data strobe signal DQS as the output signal is changed in synchronization with the external output of the read data and is used as a read strobe signal. The output timing of the read data and the change of the output signal DQS are synchronized with the clock signal CK using a DLL (delay locked loop) circuit (not shown). The DLL circuit is not particularly limited, but generates an internal clock signal in which the signal propagation delay time characteristic of the internal circuit with respect to the clock CLK is compensated by a replica circuit technique and a phase synchronization technique. In synchronization with the internal clock signal, read data is output and the output signal DQS is changed in clock. As a result, the phases of the clock CLK and the output clock DQS are matched with high accuracy.

  The access commands include a row address strobe / bank active command (RASBA command), a column address / read command (CAR command), a column address / write command (CAW command), and the like.

  The RASBA command is a command for validating selection of a memory bank and an instruction of a row address of the selected memory bank, whereby a word line in the specified memory bank is selected and the memory connected to the word line is selected. Each cell is conducted to a corresponding complementary data line.

  The CAR command is a command for giving a column address for a read operation, whereby a column address signal is taken into the column address buffer and a column system selection operation is performed. In the burst operation, the column address incremented by the burst counter is used in the subsequent column system selection operation. In the column selection operation, a 64-bit unit bit line selection operation is performed in the memory bank previously activated by the RASBA command, and the data of the selected bit line is synchronized with the rise and fall of the output signal DQS. Then, it is continuously output to the outside in units of 32 bits. The number of times of continuous reading is the number designated by the burst number (burst length). In the case of the DDR-SDRAM 61, the number of bursts is a multiple of 2 of an integer. Further, data reading from the data output circuit is started after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

  The CAW command is a command for giving a write address for a write operation, and the column address signal fetched thereby is used as the write start address of the activated memory bank. The address includes the rising edge of the input signal DQS and the address. Write data supplied in units of 32 bits in synchronization with the falling edge is written in units of 64 bits. There is no CAS latency setting in the write operation, and writing of the write data is started in synchronization with the data strobe signal DQS with a delay of one cycle of the clock signal CLK from the CAW command cycle.

  In the DDR-SDRAM 61, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle of the burst operation and a row address strobe / bank active command is supplied, The operation of the row address system in the other memory bank is made possible without affecting the operation in the other memory bank. That is, a row address system operation specified by a bank active command or the like and a column address system operation specified by a column address / write command or the like can be performed in parallel between different memory banks. Therefore, as long as data does not collide at the data input / output terminals DQ0 to DQ31, during execution of a command that has not been processed, precharging or RASBA for a memory bank different from the memory bank to be processed by the command being executed is performed. It is possible to issue internal commands in advance by issuing commands or the like. The DDR-SDRAM 61 can input / output data synchronized with both rising and falling edges of the data strobe signal DQS synchronized with the clock signal CLK, and can input / output addresses and control signals in synchronization with the clock signal CLK. A large-capacity memory similar to a DRAM can be operated at a high speed comparable to that of an SRAM, and the number of data to be accessed for one selected word line is specified by a burst length. Thus, it is possible to sequentially read or write a plurality of data by sequentially switching the column system selection state by the built-in column address counter 10.

<< DDR-SDRAM controller >>
FIG. 3 shows a block diagram of the DDR-SDRAM controller 10. The DDR-SDRAM controller 10 includes a super highway bus interface (SHBIF) 80, a 3D bus interface (3DBIF) 81, a graphic bus interface (GFBIF) 82, a bus arbiter (BARBT) 83, and a DDR controller (DDRCNT) 84.

  The SHB interface 80 is connected to the SHB 4, the 3DB interface 81 is connected to the 3DB 24, and the GFB interface 82 is connected to the GFB 20. The GFB 20 is configured as a 128-bit to 32-bit inter-module dedicated bus. The interfaces 80 to 83 have a master port and a slave port, and execute a bus transaction of a split transaction bus. The bus arbiter 83 arbitrates data transfer or packet transfer between the circuit module and the DDR controller (DDRCNT) 84 via the interfaces 80 to 82.

  The DDR controller 84 controls the clock synchronization command issuance and the data input / output operation for the DDR-SDRAM 61 so as to satisfy the access request arbitrated by the bus arbiter. The basic control is general DDR-SDRAM access control for the burst read operation and write operation of the DDR-SDRAM 61 described with reference to FIG. 2, and the control logic thereof is provided in the DDR access control unit (ASCNT) 85. . A characteristic configuration for the DDR controller 84 is that it has bank caches CACHB0 to CACHB3 as storage areas respectively corresponding to the four memory banks BNK0 to BNK3 of the DDR-SDRAM 61. The bank caches CACHB0 to CACHB3 can store a part of data of the bank using the corresponding bank address as an associative key. The control logic for the bank caches CACHB0 to CACHB3 is provided in the cache control unit (CHCNT) 86. In addition, the DDR controller 84 includes a read data output control unit (DOCNT) 87 and a selector (DSEL) 88 for selecting data in the bank caches CACHB0 to CACHB3 and data from the DDR-SDRAM. Any one of the bank caches CACHB0 to CACHB3 or these are collectively referred to as a bank cache CACHB.

  Each of the bank caches CACHB0 to CACHB3 has an address part ADR, V and a data part DAT illustrated in FIG. 4 as storage areas. The data part DAT is a storage area having a data size accessible in one cycle of the clock DQS of the DDR-SDRAM. Specifically, it is 64 bits. The address portion ADR stores an address defining a range specified by one row address and two column addresses for the DDRE-SDRAM memory bank, that is, a row address and a column address excluding the least significant bit from the row address. . The address part V stores a valid bit indicating the validity of the bank cache. Each of the bank caches CACHB0 to CACHB3 can hold one cache entry. The bank caches CACHB0 to CACHB3 are composed of SRAM (Static Random Access Memory), registers and the like.

《Bank Cash》
A control mode for the bank cache by the cache control unit (CHCNT) 86 will be described. The access request that is arbitrated and supplied by the bus arbiter 83 includes a transaction ID in the access request base, a bus ID that identifies the bus to which the access request is transferred, an access command that indicates the type of access, an access address, a burst length, and a write access In the case of, write data is included.

  The cache control unit 86 enables the bank cache CACHB when the access address is a non-cache target area of the CPU cache memory 13 (CACH). When the access address is the CPU cache target area, the bank cache CACHB is not operated. As a result, the CPU cache memory 13 (CACH) is not frequently accessed repeatedly, and if the CPU cache memory 13 (CACH) is cached, a large burden is imposed by the cache miss penalty. The bus throughput or data throughput can be improved for difficult data and programs. Further, when both the CPU cache memory 13 (CACH) and the bank cache CACHB are to be cached, complicated control for maintaining coherency of stored information is not necessary.

  In addition, the cache control unit 86 limits the buses that can operate the bank cache CACHB in response to an access request. For example, the bank caches CACHB0 to CACHB3 are made operable only in response to an access request from SHB4. For example, in accessing by a graphic module such as DGFC7 or 2DGFC30, it is efficient to continuously read data arranged at consecutive addresses on the same raster with a large number of bursts, and a series of access data sizes thereby stored in the bank cache CACHB. Since it will exceed the capacity, it is better not to cache such a bus, and the data size for saving and restoring to the stack area is 16 bits or 32 bits. This is because the SHB4 bus, which is used for transferring these data, should be cached because it matches the unit.

  Further, the cache control unit 86 uses the bank caches CACHB0 to CACHB3 in response to a read access instruction in which the total access data size by burst access by one read access instruction to the DDR-SDRAM 61 exceeds the size of one bank cache CACHB. Do not operate. In short, the bank caches CACHB <b> 0 to CACHB <b> 3 are not operated unless an access by one read access command to the DDR-SDRAM 61 is the burst number 2. It is not necessary to perform complicated control for access in which the burst read data length from the same memory bank exceeds the storage capacity of the data part DAT of one bank cache CACHB.

  When the cache control unit 86 enables the bank caches CACHB0 to CACHB3, the cache control unit 86 refers to the bank caches CACHB0 to CACHB3 corresponding to the access address, and whether the address of the address unit ADR corresponds to the access address or the valid of the address unit V It is determined whether the bit is valid. When the address corresponds and the valid bit is valid, the cache hit is determined. Otherwise, it is a cache miss.

  In a read operation, if it is a cache hit, the memory control unit 85 suppresses the issuance of a memory read command to the DDR-SDRAM 61, reads the data in the data part DAT of the corresponding one bank cache CACHB, and selects it as a selector 88. To select. The read data output from the DDR controller 84 is returned to the bus access request source as a response packet via the SHBIF 80 connected to the access request source. If it is a cache hit, it is not necessary to perform memory access to the DDR-SDRAM. This contributes to improving the bus throughput of the MRB 25 and improves the data throughput of read access.

  In a read operation, in the case of a cache miss, the memory control unit 85 performs read access to the DDR-SDRAM 61 using the access address related to the miss, and performs bus access as a response packet via the SHBIF 80 that connects the read access data to the access request source. The read data is returned to the request source, the read data is stored in the data part of the bank cache CACHB corresponding to the memory bank, the address of the corresponding address part ADR is updated to the access address, and the valid bit of the corresponding address part V is set. Set to a value indicating validity.

  In the case of a cache hit in a write operation, the memory control unit 85 invalidates data in one bank cache CACHB related to the hit. That is, the valid bit of the address part V of the corresponding bank cache CACHB is changed to a value indicating invalidity. At the same time, a write command for write data related to the hit is issued to the DDR-SDRAM 61. In the case of a cache miss in the write operation, a write command of write data related to the miss is issued to the DDR-SDRAM 61. This eliminates the need for complicated control for maintaining coherency between the bank caches CACHB0 to CACHB3 and the DDR-SDRAM 61. The DDR controller 10 is connected to a plurality of buses and controls access to the DDR-SDRAM 61 in response to access requests from a plurality of circuit modules. All access requests from any bus are targeted for the bank caches CACHB0 to CACHB3. In this case, complicated control is required to maintain coherency between the bank caches CACHB0 to CACHB3 and the DDR-SDRAM 61.

  FIG. 5 illustrates a control processing flow when the DDR controller 10 hits and misses the bank caches CACHB0 to CACHB3. As described above, when there is an access request, it is determined whether or not it is a read access (S1). If it is a bank cache hit in the case of reading (T in S2), the data related to the hit is output (S3). If it is a cache miss (F in S2), a memory read is performed on the DDR-SDRAM (S4), and the bank cache related to the miss is updated (S5). In the case of a write (F in S1), if it is a bank cache hit (T in S7), the bank cache related to the hit is invalidated (S8), a memory write to the DDR-SDRAM is performed (S9), and a cache miss ( In the case of F) of S7, the process shifts to memory write to the DDR-SDRAM 61 (S9).

  FIG. 6 shows a typical access timing of the DDR-SDRAM 61. A burst length 2 read command is issued with an address specified for each clock cycle C1, C2, C3. After issuing the command, the read data is output in units of 32 bits every half cycle of the clock in clock cycles C5, C6 and C7 after waiting for the timing when the internal operation of the DDR-SDRAM is determined.

  FIG. 7 shows a timing chart when a read access having a 16-bit access data size is requested three times for a continuous address from SHB4. The continuous address of 16-bit unit data is the upper common address in 64-bit units. FIG. 7 shows such a common address as A0. For example, when the read access request for the access address A0 is supplied from the CPU 11 of the SHB 4 three times continuously in the clock cycles C1, C2, and C3, the DDR controller 10 determines the hit or miss of the bank cache, and the first access request Since there is a bank cache miss, a read access command of access address A0 is issued to DDR-SDRAM 61 at clock cycle C2. After issuing the command, the DDR-SDRAM 61 waits for the timing when the internal operation of the DDR-SDRAM 61 is determined, and the read data D0 and D01 are output from the DDR-SDRAM 61 in units of 32 bits every half cycle of the clock in synchronization with the clock cycle C6. Since the requests of C2 and C3 hit the bank caches CACHB0 to CACHB3 built in the DDR-SDRAM controller 10, the memory access command for the DDR-SDRAM 61 is not issued, and the read data used as the access response to the CPU 11 is the bank. It is 16-bit data of continuous addresses extracted from the data D00 and D01 held in the cache CACHB. In the figure, the response data returned in clock cycles C7, C8, and C9 indicate all data related to bank cache hits such as D00 and D01 for convenience. This improves the throughput of the MRB 25.

  FIG. 8 shows a timing chart when the same access request as in FIG. 7 is operated without using a bank cache. An access command corresponding to the access request issued in the clock cycles C1, C2, and C3 from the CPU is directly issued to the DDR-SDRAM 61 in the clock cycles C2, C3, and C4, and is sent to the CPU 11 in the cycles of the clock cycles C7, C8, and C9. Will be transferred. Compared to FIG. 7, the time for occupying the MRB 25 is longer and the bus throughput is lower.

  FIG. 9 shows the timing of the operation in which the DDR-SDRAM controller 10 reorders the bank cache hit data and returns it to the access request source in response to the burst read and single read access requests from the SHB 4. An access request issued from the CPU 11 in the clock cycle C0 is a read access with a burst number of 4 with the head address B0. Next, in cycles C2 and C3, the CPU 11 issues a single read access request with addresses S1 and S2. In response to the burst read access request, the DDR-SDRAM controller 10 does not target the bank cache because the entire access data size exceeds the storage capacity of the bank cache, and addresses B00 and B01 sequentially from the clock cycle C2. , B02, B03 are issued to the SDRAM 61 as a read command (burst number 2). The SDRAM 61 responding to this read command outputs the read data D00, D01, D03, D04, D05, D05, D06, D07 in units of 32 bits every half cycle of the clock sequentially from the clock cycle C6. Here, the single read for the address S1 hits the bank cache. Therefore, the DDR-SSDRAM controller 10 does not issue the access command of the DDR-SDRAM 61 for the single read, and acquires the data D10 and D11 related to the hit from the bank cache. Since this acquisition timing is earlier than the timing at which the read data D00, D01 from the SDRAM 61 can be returned to the CPU, the data D00, D01 related to the bank cache hit is first returned to the CPU 11 in the clock cycle C6. Since a single read for the address S2 is a bank cache miss, a read command (burst number 2) for the address S2 is issued to the SDRAM 61 in the clock cycle C6. The outputs of the data D20 and D21 from the SDRAM 61 in response to this read command are synchronized with the clock cycle C10. The DDR-SDRAM controller 10 sequentially returns the read data D00, D01, D02, D03, D04, D05, D06, D07, D20, D21 from the SDRAM 61 to the CPU 11 after the clock cycle C7.

  As described above, in FIG. 9, during the read latency cycle of the DDR-SDRAM 61, the read data D10 and D11 corresponding to the access request of the single read S1 that is a bank cache hit can be returned to the access request source CPU 11. The bus throughput for the CPU 11 access is improved, and the bus throughput of the DDR-SDRAM 61 is improved.

  In particular, in this case, since the super highway bus 4 is a split transaction type and supports reordering of read data, the SHB interface 80 sends response data D10 and D11 related to the access request of S1 in the cycle of C6. It is possible to transfer the response prior to the response to the access request related to B0.

  In a split transaction type bus, an access response circuit receives a request packet from an access request circuit and returns a response packet in response to the request to the access request circuit, and includes a request packet and a response packet. A series of processes (transactions) can be identified from other transactions by a transaction ID unique to the access request circuit. When the DDR-SDRAM controller 10 returns a plurality of read data in response to a plurality of continuous read access instructions from the circuit module to the external memory to the bus, the DDR-SDRAM controller 10 corresponds to the read access instruction order from the circuit module. Thus, reordering that changes the output order of read data to the read access request source is possible. This is possible because a transaction can be identified as another transaction by its unique transaction ID.

  If the responses must be returned in the order of access requests, if the reordering is not performed, the response data of the access request that hits the bank cache CACHB is earlier than the response data of the access request that misses the bank cache CACHB. Although it can be acquired, the former response must be returned to the access request source until the latter response is received, and as a result, the data throughput of the system is deteriorated. Read data from the bank cache CACHB related to the bank cache hit is preceded by read data from the DDR-SDRAM 61 related to the bank cache miss with respect to the instruction order of the read access from the circuit module. Can be output as data. No extra waiting is required to receive a response to the access request.

  FIG. 10 shows the operation timing when the single read related to S1 in FIG. 9 is also a bank cache miss. In this case, since the access requests from the CPU 11 are processed sequentially, the transfer of response read data to the CPU 11 is also sequential. There is no bank cache hit, so no reordering occurs.

《Merging access requests》
Next, a response by the DDR-SDRAM controller 10 to an access request from the graphic bus 20 which is not targeted for the bank cache, particularly merging of access requests will be described.

  FIG. 11 shows a read access flow from the circuit module (also simply referred to as a graphic module) of the graphic bus 20 to the DDR-SDRAM 61. When an address and a burst length are issued from the graphic module to the graphic bus 20, a memory read access is performed by the DDR-SDRAM 61 via the DDR memory bus 25, and the read data is returned as graphic data to the graphic bus 20.

  FIG. 12 shows an operation flow of read access from the graphic module to the DDR-SDRAM 61.

Read access from the graphic module to the DDR-SDRAM 61 is as follows:
(1) Read request cycle from the graphic module to the DDR-SDRAM controller 10;
(2) Start of a read cycle for issuing a read command from the DDR-SDRAM controller 10 to the DDR-SDRAM 61;
(3) DDR-SDRAM 61 outputs read data to DDR-SDRAM controller 10 to end the read cycle,
(4) The read response cycle in which the DDR-SDRAM controller 10 returns memory read data to the graphic module is performed in this order.

  FIGS. 13 to 15 show the operation timing when a read access request with an access data size of 32 bits and a burst length of 8 is sent from the graphic module to the DDR-SDRAM. FIGS. 13 and 14 show the case where read access requests are not merged, and FIG. 15 shows the case where read access requests are merged.

  In FIG. 13, a request command, an address, and a burst length are issued from the graphic module to the DDR-SDRAM controller 10 via the graphic bus 20 in the C1 cycle. The DDR-SDRAM controller 10 issues a read command in the cycle C2 to C9 to the DDR-SDRAM 61 via the DDR memory bus 25, and the DDR-SDRAM 61 is in 32-bit units every half clock cycle in the cycle C4 to C11. Output read data. At this time, the DDR-SDRAM controller 10 issues a read command to the DDR-SDRAM 61 as many times as the burst length (eight times) and receives data from the DDR-SDRAM 61 as many times as the burst length (eight times). That is, in order to read 32-bit data 8 times, a read command is issued 8 times. Correspondingly, in the DDR memory bus 25, 64-bit data with consecutive addresses is output in 32 cycles at a time, and is continuously output within one cycle, so that the addresses are continuous like the requested read access. When 32-bit data is read eight times, the same data is output in the C4 and C5 cycles, the C6 and C7 cycles, the C8 and C9 cycles, and the C10 and C11 cycles. However, in this case, since only 32 bits are valid in one read access, the first-half or second-half 32-bit data output in each cycle is invalidated. This is the same as outputting the same data that is output and invalidated in the previous cycle and validated again in the next cycle. In drawing, invalid data is distinguished from valid data by a thick line frame. The DDR-SDRAM controller 10 returns the data thus obtained to the graphic module via the graphic bus 20 in the C6 to C13 cycle. This response cycle is performed 8 times corresponding to the number of burst lengths, and 32-bit data is transferred each time.

  FIG. 14 shows a timing church when a refresh cycle for the DDR-SDRAM 61 occurs in the middle of FIG. Similarly to FIG. 13, after a request command, an address, and a burst length are issued from the graphic module in the C1 cycle, the DDR-SDRAM controller 10 sends the DDR-SDRAM 61 to the DDR-SDRAM 61 via the DDR memory bus 25 from the C2 cycle. A read command is issued as many times as the burst length (8 times), and data is received as many times as the burst length (8 times) from the cycle C4. Here, refresh occurs in the cycle C3 in the middle of issuing the read command eight times. Then, the remaining read command issuance cycles are delayed after the C10 cycle, for example. Further, since the DDR-SDRAM 61 outputs data after the refresh is completed, the data output corresponding to the read command issued after the refresh command is based on the cycle from C5 to C11 in the case where no refresh occurs as shown in FIG. Will be too late. Therefore, the data throughput of the graphic bus 20 is worse than in the case of FIG.

  FIG. 15 shows a timing chart when issuing a read command by merging access requests. A request command, an address, and a burst length are issued from the graphic module to the DDR-SDRAM controller 10 through the graphic bus 20 as in the case of FIG. The DDR-SDRAM controller 10 issues a read command to the DDR-SDRAM 61 via the DDR memory bus 25, whereby data is output from the DDR-SDRAM 61. At this time, the DDR-SDRAM controller 10 issues read commands in four batches in order to effectively use the invalid data generated in FIGS. 13 and 14. In other words, an access request for reading 8 times of 32-bit data with consecutive addresses from the graphic module is converted into a request for reading 4 times of 64-bit data, and a read command is issued to the DDR-SDRAM 61. As a result, the period during which the DDR memory bus 25 is not used for the read access is increased as compared with FIG. 13, and the period can be used for the next access, precharge, refresh, or the like. Further, since the use cycle of the DDR memory bus 25 with respect to one request is small, the probability that a refresh occurs during the memory read access as in the case of FIG. 14 is reduced. For these reasons, the data throughput of the DDR memory bus 25 is greatly improved.

  Read data merged from the access requests and output from the DDR-SDRAM 61 is supplied to the RDOCNT 87. The data supplied to the RDOCNT 87 is cut out to the data size requested from the graphic module in accordance with an instruction from the ASCNT 85, supplied to the GFBIF 82 via the selector 88, and transferred to the access requesting graphic module via a response packet. .

  In the above description of access request merging, eight read accesses of 32-bit data are given as an example. However, the present invention is not limited to this example, and the number of data bits of an access request to the DDR-SDRAM controller 10 is greater than the width of the data bus 25. In the case where it is small, the data throughput of the DDR memory bus 25 is improved similarly. Naturally, the burst length may be another value.

  Next, the operation when there are a plurality of modules that request access to the DDR-SDRAM 61 will be described.

FIG. 16 shows an operation flow when there is a read access request from the two graphic modules A and B to the DDR-SDRAM 61. In FIG. 16, the read access from the two graphic modules A and B to the DDR-SDRAM 61 is as follows.
(1) Read request (A) cycle from the graphic module A to the DDR-SDRAM controller 10;
(2) Start of a read cycle (A) for issuing a read command corresponding to (1) from the DDR-SDRAM controller 10 to the DDR-SDRAM 61;
(3) The DDR-SDRAM 61 outputs the data corresponding to (2) to the DDR-SDRAM controller 10 and ends the read cycle (A).
(4) Read response (A) cycle in which the DDR-SDRAM controller 10 responds to memory read data to the graphic module A,
(5) Read request (B) cycle from the graphic module B to the DDR-SDRAM controller 10;
(6) Start of a read cycle (B) for issuing a read command corresponding to (5) from the DDR-SDRAM controller 10 to the DDR-SDRAM 61;
(7) The DDR-SDRAM 61 outputs data corresponding to (6) to the DDR-SDRAM controller 10 and ends the read cycle (B).
(8) The read response (B) cycle in which the DDR-SDRAM controller 10 responds the memory read data to the graphic module B is performed in this order. The cycles (1) and (4) use a different bus through the graphic bus (A) of the graphic module A, and the cycles (5) and (8) use a different bus through the graphic bus (B) of the graphic module B. Therefore, cycles (1) to (4) and cycle (5) can be performed in reverse order or simultaneously.

  In FIG. 16, the access request from the graphic module B is generated before the response to the access request from the graphic module A is completed. The bus throughput of the graphic bus (A) and the graphic bus (B) is determined by the bus throughput of the DDR memory bus 25.

  FIG. 17 illustrates the operation timing when access requests are not merged when there are a plurality of modules that request memory access.

  The graphic module A and the graphic module B issue a request command, an address, and a burst length in the cycle of C1 to the DDR-SDRAM controller 10 via the graphic bus (A) and the graphic bus (B), respectively. The access data size at this time is 32 bits. The DDR-SDRAM controller 10 arbitrates requests from a plurality of modules by the bus arbiter 83. Here, an access request is issued to the DDR-SDRAM 61 in the order of the graphic module A and the graphic module B. In FIG. 17, the DDR-SDRAM controller 10 issues a read command for each access request every number of burst lengths (8 times) and receives read data for the number of burst lengths (8 times). This is because it is necessary to issue a read command eight times in order to read 32-bit data eight times. When the accesses of the graphic module A and the graphic module B are combined, a total of 16 read commands are issued in the cycle from C2 to C17, and read data is received 16 times in the cycle from C4 to C19. Similar to the case of FIG. 13, the same data as the data output in the previous cycle and invalidated is read later and validated. The DDR-SDRAM controller 10 returns the data read 16 times in this way to the graphic module A via the graphic bus (A) and to the graphic module B via the graphic bus (B). The number of responses is equal to the number of burst lengths.

  FIG. 18 illustrates the operation timing when merging access requests when there are a plurality of modules requesting memory access.

  The graphic module A and the graphic module B issue a request command, an address, and a burst length in the cycle of C1 to the DDR-SDRAM 10 controller 10 via the graphic bus (A) and the graphic bus (B), respectively. The access data size at this time is 32 bits. In response to this, the DDR-SDRAM controller 10 arbitrates access requests from the graphic module A and the graphic module B, and issues an access request to the DDR-SDRAM 61 in the order of the graphic module A and the graphic module B. In the case of FIG. 18, the DDR-SDRAM controller 10 makes an access request of 8-bit read of 32 bits with consecutive addresses from the graphic modules A and B in order to effectively use the invalid data of FIG. In this way, the read command is collectively issued to the DDR-SDRAM 61 every four times. As a result, the access of the graphic module A and the graphic module B is combined and a read command is issued eight times in the cycle from C2 to C9. The DDR-SDRAM controller 10 receives 32 bits from the DDR-SDRAM 61 in cycles C4 to C11. Receive x2 read data 8 times. There is no invalid data in the data received from the DDR-SDRAM 61. Therefore, the data throughput of the DDR memory bus 25 is improved as compared with FIG. Thereafter, the DDR-SDRAM controller 10 returns read data to the graphic module A and the graphic module B via the graphic bus (A) and the graphic bus (B). This access response is performed the number of burst lengths (8 times). Since the graphic bus (A) and the graphic bus (B) are individualized corresponding to the graphic module A and the graphic module B, access responses to the graphic module A and the graphic module B can be performed in parallel. As a result, the data throughput of the entire system is improved.

  FIG. 19 illustrates the operation timing when the access request is not merged when the operation frequency of the graphic module is higher than the operation frequency of the DDR-SDRAM 61.

  Here, the operating frequency of the graphic module is set to twice the operating frequency of the DDR-SDRAM 61. The graphic module issues a request command, an address, and a burst length in the C1 cycle to the DDR-SDRAM controller 10 via the graphic bus. The access data size at this time is 32 bits. The DDR-SDRAM controller 10 issues a read command to the DDR-SDRAM 61 via the DDR memory bus 25 for the number of times of the burst length (8 times) in the cycle C′1 to C′8, and from C′3 to C ′. The data of 32 bits × 2 is received 8 times over 10 8 cycles. Next, the DDR-SDRAM 10 controller sequentially returns the received data to the graphic module via the graphic bus. However, the DDR-SDRAM 10 controller is limited by the slow data reception from the DDR-SDRAM 10 and cannot return read data in a continuous cycle. In this case, the data throughput of the graphic bus is greatly deteriorated.

  FIG. 20 illustrates an operation timing when merging access requests when the operating frequency of the graphic module is higher than the operating frequency of the DDR-SDRAM 61.

  Here, the operating frequency of the graphic module is set to twice the operating frequency of the DDR-SDRAM 61. The graphic module issues a request command, an address, and a burst length in the cycle of C1 to the DDR-SDRAM controller 10 via the graphic bus. The access data size at this time is 32 bits. The DDR-SDRAM controller 10 issues a read command to the DDR-SDRAM 61 via the DDR memory bus 25, but unlike the case of FIG. 18, an access request for 32-bit 8-times read is an access for 64-bit 4-times read. Merge to the request and issue a read command only four times in the cycle from C′1 to C′4. In response to this, the DDR-SDRAM 61 outputs all 32-bit unit data in four cycles C3 to C'6. The DDR-SDRAM controller 10 returns the read data to the graphic module via the graphic bus. However, the DDR-SDRAM controller 10 can continuously return the read data response without being limited by the reception timing of the read data from the DDR-SDRAM 61. The data throughput of the graphic bus is improved. Therefore, the data throughput of both the DDR memory bus 25 and the graphic bus is improved, and the data throughput of the entire system can be greatly improved.

  Although not specifically shown, when there are a plurality of modules that request access to the DDR-SDRAM 61 and the operating frequency of the module is higher than the operating frequency of the DDR-SDRAM, an access request from the module is issued in the same manner as described above. The data throughput of the bus and system can be improved by merging.

  Further, each bus such as the SHB 4 and the graphic bus 20 is given a bus ID for each bus, but the validity or invalidity of the bank cache may be set by the bus ID. Such a setting may be fixedly performed by the logic of the bank cache control unit 86, or may be performed programmable by a control register. This makes it easier to deal with the case where it is desirable to determine the bank cache target for each bus in order to improve the hit rate of the bank cache.

  The SHB 4 and the graphic bus employ a packet-type split transaction bus, and the access size is determined when an access request is made. A valid or invalid access size of the bank cache may be set depending on the access size. Such a setting may be fixedly performed by the logic of the bank cache control unit 86, or may be performed programmable by a control register. This makes it easier to deal with cases where it is desirable to improve the hit rate of the bank cache by determining the target of the bank cache by the access size.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the semiconductor device of the present invention is not limited to an image processor for car navigation, but various data such as an image processor for a printer or a portable terminal, a communication control processor, an engine control processor, a general-purpose microcomputer, etc. The present invention can be widely applied to semiconductor devices for processing. Various changes can be made to the bus bits, the bus data transfer protocol, the number of buses, and the types of built-in circuit modules. The memory having a plurality of banks is not limited to the DDR-SDRAM, and may be other clock synchronous memories such as SDR-SDRAM, DDR-SRAM, and SDR-SRAM.

DESCRIPTION OF SYMBOLS 1 Image processor 2 Processor core 3 Clock generation circuit 4 Super highway bus 5 Bus bridge circuit 7 3D engine 10 DDR-SDRAM controller 11 CPU
13 (CACH) CPU cache memory unit 20 Graphic bus 24 3D bus 25 DDR memory bus 30 2D engine 31 Display control circuit 61 DDR-SDRAM
BNK0 to BNK3 Memory bank 80 Super highway bus interface 81 3D bus interface 82 Graphic bus interface 83 Bus arbiter 84 DDR controller 85 DDR access control unit 86 Cache control unit CACHB0 to CACHB3 Bank cache

Claims (2)

A memory control unit capable of controlling an external memory having a plurality of banks in synchronization with a clock, a bus connected to the memory control unit, and a circuit provided corresponding to the bus and instructing memory access Module and
When a burst read is requested from the circuit module with an access data size smaller than the number of bits of the bus, the memory control unit continuously issues a read request to the external memory with a number of times less than the burst number of the requested burst read. Device that can be issued automatically. A memory control unit capable of controlling an external memory having a plurality of banks in synchronization with a clock, a bus connected to the memory control unit, and a circuit provided corresponding to the bus and instructing memory access Module and
In response to an access request from the circuit module in which the number of bursts is specified with an access data size smaller than the number of bits of the bus, the memory control unit receives all data received by a single read request to the external memory. A semiconductor device that can issue read requests multiple times in succession.

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