JPH03163638A - Burst transfer system - Google Patents

Abstract

PURPOSE:To execute the burst transfer at a higher speed than a conventional burst transfer by providing a buffer between a RAM constituted of two banks and a CPU, respectively, and executing a page mode access by interleave by both the banks. CONSTITUTION:A dynamic RAM is divided into two of a bank 20 and a bank 21, and addresses #0,#2,#4... #N-1, and addresses #1,#3,#5... #N are allocated to the bank 20 and the bank 21, respectively. Also, a controller 3A allows an address by a RAS to be used in common by both the banks, divides an address by a CAS into each bank, and forms a timing signal OE#0 and OE#1 for data buffers 40, 41. In such a state, the dynamic RAM executes a burst transfer by a page mode access. That is, by toggling the CAS allowing the RAS to fall against to the bank 20, 21, a random access can be executed on the same line address, a rise of the CAS becomes output enable of a high speed in a read cycle, and by a rise of the CAS, a data output is turned off.

Description

[Detailed Description of the Invention] A. INDUSTRIAL APPLICATION FIELD The present invention relates to a data burst transfer method in a computer.

B9 Summary of the invention The present invention combines dynamic RAM with external memory.
When data is transferred in burst mode using PUL'I, the dynamic RAM is divided into two banks and page mode access is performed using interleaf to enable high-speed data transfer.

C. BACKGROUND OF THE INVENTION Many conventional computer systems have a burst mode for high-speed data transfer between a CPU and peripheral devices. For example, a 32-bit CPU has a built-in cache memory to temporarily store programs and data in order to improve processing speed. Cache replacement is performed for a preset number of bytes in the memory. In order to perform this replacement operation at high speed, burst mode data transfer is performed instead of normal external memory access.

FIG. 3 shows a time chart of data transfer in burst mode. The burst request BSTRQ is asserted in the Tl cycle of the clock CLK, and the burst acknowledge BSTAK is asserted at the falling edge of the clock in the T2 cycle.
is asserted, and on the condition that READY is asserted at the rising edge of the next clock of the T2 cycle, data D31 is transferred from address A31-A2.
- Sub/sub/register DO and move on to the burst transfer TB cycle. In the TB cycle, the address A3 1-A2 is incremented at the rising edge of the clock, and data is sampled at the rising edge of the next clock. The TB cycle is performed for the set number of replacements, and the bus cycle ends.

When burst acknowledgment BSTAK is not asserted in response to burst request BSTRQ,
As shown in FIG. 4, normal external memory access is performed by asserting READY. In the same figure, berth 1
- Since the acknowledge BSTAK is not asserted, data transfer is started with the assertion of READY, and the address increment and data transfer are repeated every time READY is asserted for the set number of replacements.

D. Problems to be Solved by the Invention Conventional burst mode data transfer handles high-speed memory access, but this requires external memory that can perform high-speed read/write processing, and static RAM It can only be applied to high-speed, small-capacity and heavy-duty devices such as (SRAM).

Therefore, when using large-capacity low-speed memory such as dynamic RAM (DRAM) as external memory, even if dynamic RAM is used in high-speed access mode (page mode, static column mode), burst mode transfer is not possible. The access time is insufficient for operation, and only normal memory access is possible.

FIG. 5 shows a conventional configuration for realizing burst mode transfer when dynamic RAM is used as an external memory. For data transfer between the CPU I and the dynamic clock RAM 2, the controller 3 forms a field clock pulse with respect to the clock CLK as shown in FIG. 6, and forms a burst cycle 'rB with this long clock cycle. , to accommodate the slow access time of dynamic RAM 2, and
The burst cycle TB of pu+ is set to one clock width.

RAS (row address select) and C AS (column address select)
ct) is the switching timing of address data acquisition by the address multiplex method.

An object of the present invention is to provide a burst transfer method that allows high-speed data transfer using a large-capacity low-speed memory such as a dynamic RAM as an external memory.

E. Means for Solving the Problems In order to achieve the above object, the present invention provides a dynamic RA.
In a burst transfer method in which data is transferred between M and the CPU in burst mode, the dynamic RAM is divided into two banks, and a buffer 1 for temporarily storing data is provided between each bank and the CPU.
The controller alternately accesses each bank in page mode access using interleaf, starts accessing one bank while accessing the other bank, and also secures recharging time using CAS. Data collision caused by starting access to one bank while accessing another bank is avoided by temporarily storing data in a buffer.

F. Example FIG. 1 is a block diagram showing an embodiment of the present invention.

Dynamic RAM is bank 2. and bank 2. Addresses #0, #2, #4...#N-1 are in bank 2, and addresses #1, #3, #5...#N are in bank 2! assigned to. The controller 3A uses RAS addresses common to both banks, separates CAS addresses for each bank, and stores them in the data buffer 4. +4+ timing signals OE#0 and OE#1 are formed. Data buffer 4. +4+ is each bank 2. , 21 and CPU1, temporary storage of data is performed.

In such a configuration, the dynamic RAM performs burst transfer using page mode access.

That is, bank 2. +2+, random access is enabled on the same row address by toggling CAS after falling RAS, and the falling edge of CAS is used as a high-speed output enable in the read cycle.
The data output buffer is turned off by the rising edge of .

FIG. 2 shows a time chart of this embodiment, and shows the controllers 3A, ! :The procedure for starting burst transfer between CPUIs is the same as before, but bank 2 is used for addressing by RAS and CAS. +2+ alternately access pages. Bank 2. Data access to bank 21 by CAS #1 is started in the middle of data access by CAS #0 to bank 2. Access to bank 2l is started during access to bank 2l. At this time, the data is in buffer 4. , 4l to prevent data collisions during transfer with cpul. Bank 2. bank 2 when the access is completed. buffer 4. Close Bank 2.
Open buffer 4I of bank 2. Outputs data. The bank 2o uses this data output period to secure precharge time for the CAS. When bank 21 data output is finished, bank 2. page access. The bank 21 also uses this time as a CAS pre-charging time.

In this way, in this embodiment, the dynamic RAM is divided into two banks, and burst transfer is performed by alternate page mode access.

Conventionally, when using this page mode access for data burst transfer, the access time of dynamic RAM is slow, so TB cycles are required. However, in this embodiment, burst transfer is made possible with the period of the clock CLK. For example, when the CPU performs four replacements in burst mode, in the conventional system there is only one dynamic RAM bank, so the same bank is accessed four times in page mode access, but in this embodiment, the same bank is accessed four times. Because it is divided into two, bank 2. CA by accessing the page alternately and 2■
Secure S's bricharging time.

G. Effects of the Invention As described above, according to the present invention, dynamic R A
M has a two-bank structure, a buffer is provided between each bank and the CPU to avoid data collisions, and page mode access is performed using interleaf for both banks, which reduces cross-linking compared to conventional burst transfer. Fast burst transfer is possible. Furthermore, in the case of burst transfer, conventionally, N page mode accesses are performed for one bank for N same replacements, but in the present invention, page mode accesses are performed N/2 times, which is (=r
Address changes are halved due to CAS addressing, and CA
The access time can be shortened by eliminating the delay in the S pre-charging time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, the second flash is a time chart of the embodiment, FIG. 3 is a burst mode time chart, FIG. 4 is a normal external memory access time chart, and the fifth diagram is a time chart of the embodiment. The figure is a block diagram of a conventional DRAM external memory, and FIG. 6 is a burst transfer time chart using the conventional DRAM. ■...cpu, 2o, 21...bank, 3A...dynamisoku RAM controller, 4. ,41...buffer. @1 Figure 3 Time chart of the embodiment D31-[)0 ------------{)-00-0--1-Figure 3 Burst mode time chart D31-Do

Claims (1)

[Claims] (1) In a burst transfer method in which data is transferred between a dynamic RAM and a CPU in burst mode, the dynamic RAM is divided into two banks, and a buffer for temporarily storing data is provided between each bank and the CPU. A burst transfer method characterized in that a RAM controller alternately accesses each bank in page mode access using interleaf.