JPH10308081A - Information reproducing device and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute Viterbi decoding by detecting the offset of reproduced RF signals and cancelling the offset. SOLUTION: State data is supplied to the timing generating circuit 100 from the Viterbi decoder 13 which executes Viterbi decoding of six values and four states. Timing of rise or fall of the reproduced RF signals is detected from the transition of state data. The offset calculating unit 103 samples the levels of reproduced RF signals fed from the shift register 102 with the generated timing to generate offset signals by arithmetic processing. Offset signals OE converted by the D/A converter 104 to analog signals are fed back to the subtractor 101 to cancel the offset in reproduced RF signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus such as a magneto-optical disk device and a reproducing method.

[0002]

2. Description of the Related Art In an information reproducing apparatus such as a magneto-optical disk apparatus, a reproduced signal reproduced from a recording medium is generally binarized. As a binarization method, there is known a method of detecting a peak value and a bottom value of a reproduction RF signal, generating a slice level by calculating the peak value and the bottom value, and comparing the slice level with the reproduction RF signal. ing. In some cases, a dedicated area for defining a slice level is provided on a recording medium. Also recently,
Binarization using the Viterbi decoding method is being put to practical use.

[0003] As a digital modulation method, if a DC-free method such as that used in CD is used,
The DC component in the reproduced RF signal can be made zero on average. However, RLL (2,7), RLL
In the case of a digital modulation method used in a magneto-optical disk such as (1, 7), the reproduced RF signal has a DC component. Such a DC component is called an offset. If the offset of the reproduced RF signal is constant, it is easy to remove it.

[0004]

SUMMARY OF THE INVENTION As described above, DC
When a non-free digital modulation method is employed, the offset varies depending on the pattern of the reproduced signal. Further, optical birefringence occurs due to mechanical distortion generated during the manufacture of the substrate of the magneto-optical disk, and the offset of the reproduced RF signal fluctuates at a low frequency. The slice level deviates from the ideal position due to the fluctuation of the offset,
A binarization error occurs. When Viterbi decoding is employed, the dynamic range of the preceding A / D converter is narrowed, and the resolution of A / D conversion is reduced. Thereby, the accuracy of Viterbi decoding is reduced. Further, the amplitude reference value of Viterbi decoding is shifted, and the calculated value of the branch metric is incorrect, and as a result, decoding accuracy is reduced.

Accordingly, an object of the present invention is to provide an information reproducing apparatus and a reproducing method capable of improving the accuracy of Viterbi decoding by canceling the offset of a reproduced RF signal.

[0006]

According to a first aspect of the present invention, there is provided an information reproducing apparatus for decoding a reproduced signal reproduced on a recording medium by a Viterbi decoding method. State data generating means for generating state data for each clock representing the maximum likelihood state transition itself, decoded data output means for outputting decoded data based on the state data, and Means for generating an offset detection timing corresponding to a rising or falling edge; means for generating an offset signal by calculating a reproduction signal value at the detection timing; and feeding back the offset signal to the reproduction signal, And a signal path for canceling That is the information reproducing apparatus. Further, the present invention is an information reproducing method for canceling an offset in a reproduced signal as described above.

According to a fifth aspect of the present invention, there is provided an information reproducing apparatus for decoding a reproduced signal reproduced on a recording medium by a Viterbi decoding method, wherein an A / D converter provided in a preceding stage of the Viterbi decoder is provided. MS in reproduction signal of predetermined bit number
A means for generating an offset detection timing based on the timing at which the inversion of B occurs, a means for generating an offset signal by calculating a reproduction signal value at the detection timing, and feeding back the offset signal to the reproduction signal; An information reproducing apparatus comprising: a signal path for canceling an offset. Further, the present invention is an information reproducing method for canceling an offset in a reproduced signal as described above.

According to the present invention, the rising and falling timings of the reproduced RF signal can be detected based on the Viterbi decoding status data, and the offset in the reproduced RF signal can be detected. Further, the rising and falling timings of the reproduction RF signal can be detected from the timing when the MSB of the A / D conversion output is inverted,
An offset in the reproduced RF signal can be detected.
The offset is canceled by subtracting the detected offset from the reproduced RF signal.

According to the present invention, the offset can be detected from the reproduced RF signal, and a special area for offset detection is not required on the recording medium, and the data recording area on the recording medium can be prevented from being reduced. Further, a level detection circuit for detecting a peak level, a bottom level, and the like can be omitted. Further, the offset can be continuously canceled during the reproducing operation. By canceling the offset in this way, the accuracy of Viterbi decoding can be increased.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to facilitate understanding of the present invention, an example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. The outline of the 4-value 4-state Viterbi decoding method will be described in the order of the configuration and operation of the Viterbi decoder that realizes the 4-value 4-state Viterbi decoding method, and the Viterbi decoding method other than the 4-value 4-state Viterbi decoding method.

[Overview of Disc Recording / Reproducing Apparatus] An example of a recording / reproducing apparatus having a reproducing system for performing a Viterbi decoding method will be described below. FIG. 1 is a block diagram showing an overall configuration of an example of a magneto-optical disk device having a reproducing system that performs a Viterbi decoding method. At the time of recording, the controller 2 receives user data to be recorded according to a command from the host computer 1, performs encoding based on the user data as information words, and performs RLL (1,
7) Generate a code. This codeword is used as recording data in a laser power control unit (hereinafter referred to as LPC).
4 is supplied. In addition to such processing, the controller 2 performs operations such as decoding processing described later, control of each mode such as recording, reproduction, and erasing, and communication with the host computer 1.

The LPC 4 performs recording by controlling the laser power of the optical pickup 7 to form a pit row having a magnetic polarity on the magneto-optical disk 6 in accordance with the supplied recording data. At the time of this recording, the magnetic head 5 applies a bias magnetic field to the magneto-optical disk 6. Actually, mark edge recording as described later is performed according to a precode output generated as described later based on the recording data.

As will be described later, the recording position, that is, the pit formation position, is controlled by means (not shown) for positioning the magnetic head 5 and the optical pickup 7 and the like. For this reason, even during the recording operation, when the optical pickup 7 passes through the address section and the like, the same operation as the reproducing operation described later is performed.

A method of associating each pit formed as described above with each bit in a precode output generated as described later based on recording data will be described with reference to FIG. A recording method in which a pit is formed for, for example, "1" and no pit is formed for "0" in the precode output is called a mark position recording method.
On the other hand, a recording method in which the inversion of the polarity at the boundary of each bit in the precode output expressed by the edge of each pit corresponds to, for example, “1” is called a mark edge recording method. During playback, the boundaries of each bit in the playback signal are
It is recognized in accordance with a read clock DCK generated as described later.

Next, the configuration and operation of the reproducing system will be described. The optical pickup 7 irradiates the magneto-optical disk 6 with laser light, receives reflected light generated thereby,
Generate a playback signal. The reproduction signal is composed of a sum signal R ₊ , a difference signal R _−, and a focus error signal and a tracking error signal (not shown). The sum signal R ₊ is supplied to the changeover switch 10 after the gain is adjusted by the amplifier 8. Also, the difference signal R
_- the gain adjustment and the like are supplied to a switch 10 switching after being made by the amplifier 9. Further, the focus error signal is supplied to a means (not shown) for eliminating the focus error. On the other hand, the tracking error signal is
It is supplied to a servo system and the like (not shown) and used in those operations.

The changeover switch 10 is supplied with a changeover signal S as described later. Changeover switch 10, in accordance with the switching signal S, as follows, the sum signal R ₊ or difference signals R _- supplying to the filter unit 11. That is, in a sector format of the magneto-optical disk 6 described later, the sum signal R ₊ is supplied to the filter unit 11 during a period in which a reproduction signal reproduced from a portion formed by embossing is supplied to the changeover switch 10. I do.
Further, during a period in which a reproduction signal reproduced from a portion recorded magneto-optically is supplied to the changeover switch 10, the difference signal R ₋ is supplied to the filter unit 11.

The switching signal S is generated, for example, as follows. That is, first, a signal reproduced from a predetermined pattern defined in the sector format is detected from the reproduced signal. As such a predetermined pattern, for example, a sector mark SM described later is used. Then, the switching signal S is generated at a predetermined time point recognized by a method such as counting read clocks, which will be described later, based on the time point at which the detection is performed.

The filter section 11 includes a low-pass filter for performing noise cut and a waveform equalizer for performing waveform equalization. As will be described later, the waveform equalization characteristics used in the waveform equalization process at this time are adapted to the Viterbi decoding method performed by the Viterbi decoder 13. The A / D converter 12 supplied with the output of the filter unit 11 samples the reproduced signal value z [k] according to a read clock DCK supplied as described later. Viterbi decoder 1
3 generates decoded data by the Viterbi decoding method based on the reproduced signal value z [k]. Such decrypted data is
This is the maximum likelihood decoding sequence for the recording data recorded as described above. Therefore, if there is no decoding error,
The decrypted data matches the recorded data.

The decoded data is supplied to the controller 2. As described above, the recording data is a codeword generated from user data by encoding such as channel encoding. Therefore, if the decoding error rate is sufficiently low, the decoded data can be regarded as recording data as a codeword. The controller 2 reproduces user data and the like by performing decoding processing corresponding to the above-described encoding such as channel encoding on the decoded data.

The output of the filter unit 11 is also supplied to a PLL unit 14. The PLL unit 14 generates a read clock DCK based on the supplied signal. The read clock DCK is supplied to the controller 2, the A / D converter 1
2. It is supplied to the Viterbi decoder 13 and the like. The operations of the controller 2, the A / D converter 12, and the Viterbi decoder 13 are performed at timing according to the read clock DCK. Further, the read clock DCK is supplied to a timing generator (not shown). The timing generator
For example, it generates a signal for controlling operation timing of the apparatus such as switching between recording / reproduction operations.

In the above-described reproducing operation, in order to obtain more accurate reproduction data based on the reproduction signal reproduced from the magneto-optical disk 6, the operation of each component of the reproduction system is performed according to the quality of the reproduction signal. Optimization is performed.
Such an operation is called calibration. In the calibration, there is a possibility that the quality and the like of the reproduction signal may change due to the characteristics of the recording medium such as processing accuracy and the like, for example, fluctuations in the power of the recording laser beam, recording / reproduction conditions such as the ambient temperature, and the like. This is to optimize the parameters of the reproduction system in order to cope with the above.

The contents of the calibration include, for example, adjustment of the reading laser light power of the optical pickup 7, adjustment of the gains of the amplifiers 8 and 9, adjustment of the waveform equalization characteristics of the filter unit 11, and operation of the Viterbi decoder 13. For example, adjustment of an amplitude reference value to be used. Such calibration is performed by a configuration not shown in FIG. 1 immediately after the power is turned on or when the recording medium is replaced.

[Overview of Sector Format of Recording Medium]
The user data is recorded on the magneto-optical disk 6 using a sector as a recording / reproducing unit. An example of a sector format used in the magneto-optical disk 6 will be described with reference to FIG. As shown in FIG. 3A, one sector is divided into respective areas of a header, an ALPC, a gap, a VFO ₃ , a sync, a data field, and a buffer in the order of recording / reproduction. The numbers attached in FIG.
Indicates the number of bytes. Encoded data such as block encoding is recorded on the magneto-optical disk 6. For example, 8 bits are converted into 12 channel bits and recorded.

As an example of this sector format, a format having a user data amount of 1024 bytes and a format having a user data amount of 512 bytes are prepared. In the format in which the user data amount is 1024 bytes, the number of bytes in the data field is 670 bytes.
Bytes. In the format in which the amount of user data is 512 bytes, the number of bytes in the data field is one.
278 bytes. In these two sector formats, the preformatted header of 63 bytes and the 18 bytes of the ALPC and gap area are the same.

FIG. 3B shows a 63-byte header in an enlarged manner. The header is a sector mark SM (8 bytes), VF
O field VFO ₁ (26 bytes), address mark AM (1 byte), ID field ID ₁ (5 bytes), VFO field VFO ₂ (16 bytes), address mark AM (1 byte), ID field ID
₂ (5 bytes) and postamble PA (1 byte) are arranged in order.

FIG. 3C shows an enlarged 18 byte ALPC and gap area. 18 bytes are a gap field (5 bytes), a flag field (5 bytes),
It consists of a gap field (2 bytes) and ALPC (6 bytes).

Next, these fields will be described. The sector mark SM is a mark for identifying the start of a sector, and has a pattern formed by embossing that does not occur in the RLL (1, 7) code.
The VFO field is the VFO (V
ariable Frequency Oscillator), and is composed of VFO ₁ , VFO ₂ and VFO ₃ . V
FO ₁ and VFO ₂ are formed by embossing. The VFO ₃ is written magneto-optically when a recording operation is performed on the sector. VFO ₁ , V
FO ₂ and VFO ₃ are patterns (2T patterns) in which channel bits “0” and “1” appear alternately, respectively.
Having. Therefore, if the time corresponding to the time length of one channel bit is T, a reproduced signal whose level is inverted every 2T is obtained when the VFO field is reproduced.

The address mark AM is used to provide byte synchronization to the device for the subsequent ID field and has an embossed pattern that does not occur in the RLL (1,7) code. The ID field includes a sector address, that is, information of a track number and a sector number, and a CRC for error detection for the information.
Has bytes. The ID field consists of 5 bytes. The ID ₁ and ID _2, the same address information is recorded in duplicate. The postamble PA has a pattern (2T) in which channel bits “0” and “1” appear alternately.
Pattern). ID ₁ , ID ₂ and postamble PA are also formed by embossing. Thus, the header area is a preformatted area in which pits are formed by embossing.

FIG. 3C shows the ALPC and the gap area in an enlarged manner. No pit is formed in the gap. The first gap field (5 bytes) is the first field after the preformatted header, which ensures that the device will have time to process after reading the header. The second gap field (2 bytes) is for allowing a displacement of the position of VFO ₃ later.

In the ALPC and gap area, a 5-byte flag field is recorded. In the flag field, a continuous 2T pattern is recorded when sector data is recorded. ALPC (Auto Laser Power Cont
The (rol) field is provided for testing the laser power at the time of recording. Sync field (4 bytes)
Is provided for the device to obtain byte synchronization for the subsequent data field and has a predetermined bit pattern.

The data field is provided for recording user data. The above-mentioned 670-byte data field includes 512-byte user data and 14 bytes.
It consists of 4 bytes of parity for error detection and correction, 12 bytes of sector write flag, and 2 bytes (FF). In the case of a 1278-byte data field, the data field includes 1024-byte user data, 242-byte parity for error detection and correction, and a 12-byte sector write flag. The buffer field at the end of the sector is used as a tolerance for electrical or mechanical errors.

In the above example of the sector format, the header is an area in which pits are formed by embossing. The ALPC and gap areas are not used during reproduction. In addition, VFO
_{3. The} sync field and the data field are areas of magneto-optically recorded data.

[Summary of 4-value 4-state Viterbi decoding method] The Viterbi decoding method performed by the Viterbi decoder 13 will be described below. As described above, the user data is
It is converted into a codeword as recording data by various encoding methods. An appropriate encoding method is adopted according to the characteristics of the recording medium and the recording / reproducing method. In the magneto-optical disk drive, in the block coding, Ru
In many cases, an RLL (Run Length Limited) coding method for limiting the n Length, that is, the number of '0's between' 1 'and' 1 'is used. Conventionally, several RLL coding methods have been used. Generally, an m / n block code in which the number of '0's between' 1 'and' 1 'is at least d and at most k is RLL
(D, k; m, n) code.

For example, in a 2/3 block code,
A block coding method in which the number of '0's between 1' and '1' is at least one and at most seven is RLL (1,7; 2,3)
Sign. Generally, the RLL (1, 7; 2, 3) code is R
Since it is often referred to as an LL (1, 7) code, the RLL (1, 7; 2, 3) code will be simply referred to as an RLL (1, 7) code in the following description. .

A Viterbi decoding method can be used to decode a reproduction signal reproduced from data recorded by a combination of such an RLL encoding method and the above-described mark edge recording method.

Such an RLL encoding method can meet the conditions required for the encoding method from the two viewpoints of improving the recording density and ensuring the stability of the reproducing operation. First, as described above, the mark edge recording method associates '1' in the precode output generated as described later based on the recording data with the inversion of the polarity represented by the edge of each pit. '1'
As the number of '0's between' 1 'and' 1 'is increased, the number of bits recorded per pit can be increased. Therefore, the recording density can be increased.

On the other hand, the read clock DCK necessary for adjusting the operation timing of the reproduction system is generated by the PLL section 14 based on the reproduction signal as described above. For this reason, in the recorded data, a value between '1' and '1'
When the number of 0's is increased, the operation of the PLL unit becomes unstable during the reproducing operation, so that the entire reproducing operation becomes unstable.

Considering these two conditions, '1' and '
The number of '0's between 1's must be set within a reasonable range, not too high or too low. The RLL encoding method is effective for setting the number of '0' in the recording data.

By the way, as shown in FIG.
In the combination of the LL (1, 7) encoding method and the mark edge recording method, at least one '0' is inserted between '1' and '1' in precode output generated based on recording data. Since it is included, the minimum inversion width is 2. When such an encoding method in which the minimum inversion width is 2 is used, as a method for decoding recorded data from a reproduced signal affected by intersymbol interference and noise, as described below,
A quaternary 4-state Viterbi decoding method can be applied.

As described above, the waveform equalization processing is performed on the reproduced signal by the filter unit 11. Such a waveform equalization process performed as a preceding stage of the Viterbi decoding method includes:
A partial response method that actively uses intersymbol interference is used. The waveform equalization characteristics used at this time are:
From the partial response characteristics generally represented by (1 + D) ⁿ , the linear recording density and MTF of the recording / reproducing system
(Modulation TransferFunction). Waveform equalization processing using PR (1, 2, 1) for data recorded by a combination of the above-described RLL (1, 7) encoding method and mark edge recording method requires 4
This is the preceding stage of the 4-state Viterbi decoding method.

On the other hand, in the mark edge recording method,
Prior to actual recording on a magneto-optical disk medium, etc.,
Precoding based on the recording data encoded by the above-described RLL encoding or the like is performed. The recording data sequence at each time point k is a [k], and the precode output based on this is b
When [k] is set, precoding is performed as follows.

B [k] = mod 2 {a [k] + b [k−1]} (1) Such a precode output b [k] is actually recorded on a magneto-optical disk medium or the like. On the other hand, the waveform equalization characteristic PR (1,
The waveform equalization processing in (2, 1) will be described. However, in the following description, the waveform equalization characteristic is PR (B, 2A, B) without normalizing the signal amplitude. The value of the reproduced signal when noise is not considered is denoted as c [k]. In addition, the actual playback signal containing noise (ie,
The reproduced signal reproduced from the recording medium) is denoted by z [k].

PR (B, 2A, B) indicates that the contribution of the amplitude at time point k to the value of the reproduced signal at a certain time point k is 2A times the amplitude value. The contribution of the amplitude is B times the amplitude of the signal at each point in time. Accordingly, the maximum value of the value of the reproduction signal is a case where a pulse is detected at any of the time points k-1, k, and k + 1. In such a case, the maximum value of the reproduction signal is as follows.

B + 2A + B = 2A + 2B The minimum value of the reproduced signal is 0. However, in the actual handling, the DC component A +
The following is obtained by subtracting B.

C [k] = B × b [k−2] + 2A × b [k−1] + B × b [k] −AB (2) Therefore, the reproduced signal c [k when noise is not considered. ]
Takes any value among A + B, A, -A, and -AB. Generally, one of the methods for indicating the property of a reproduced signal
For example, a pattern obtained by superimposing a large number of reproduction signals in units of five time points is called an eye pattern. FIG. 5 shows an example of an eye pattern of an actual reproduction signal z [k] subjected to waveform equalization processing under PR (B, 2A, B) in a magneto-optical disk drive to which the present invention can be applied. . From FIG. 5, the reproduced signal z [k] at each time point
Has a variation due to noise, but is approximately A +
It can be confirmed that any one of B, A, -A, and -AB is obtained. As described later, A + B, A, -A, -AB
Is used as an identification point.

An outline of a Viterbi decoding method for decoding a reproduced signal having undergone the above-described waveform equalization processing is as follows. All possible states are identified based on the step encoding method and the recording method for the recording medium. With each state at a certain point as a starting point, all state transitions that can occur at the next point in time, and the recording data a [k] and the value c [k] of the reproduction signal at the time of each state transition are specified. A representation of all states and state transitions specified as a result of the step and the state and [recorded data value a [k] / reproduced signal value c [k]] at the time of each state transition. Is called a state transition diagram. As will be described later, a state transition diagram in the 4-value 4-state Viterbi decoding method is as shown in FIG. Then, to perform a decoding operation based on this state transition diagram,
The Viterbi decoder 13 is configured.

Further, as described above, based on the state transition diagram, the most likely state transition based on the reproduction signal z [k] reproduced from the recording medium at each time point k is selected. However, as described above, z [k] is waveform-equalized in a stage before being supplied to the Viterbi decoder 13. Each time such a maximum likelihood state transition is selected, the value of the recording data a [k] described in the state transition diagram is set as a decoded value in accordance with the selected state transition. Decoded data a '[k] as the maximum likelihood decoded value sequence for the data can be obtained. However, the configuration for obtaining the maximum likelihood decoded value sequence from the decoded data values at each time point k is based on the PMU 23 in the Viterbi decoder 13 described later.
It is. Therefore, as described above, the decoded data sequence a ′
[K] is a record data sequence a when there is no decoding error.
[K]. The above steps are described in detail below.

The above steps will be described. First, as a state used here, a state at a certain time point k is defined as follows using a precode output before the time point k. That is, n = b [k], m =
The state when b [k-1] and 1 = b [k-2] is defined as Snml. With such a definition, it is considered that there are 2 ³ = 8 states, but as described above, the states that can actually occur are limited based on the encoding method and the like. RLL
Recording data sequence a encoded as a (1,7) code
In [k], at least one '0' is included between '1' and '1', so that two or more '1's do not continue.
Based on such conditions imposed on the recording data string a [k], certain conditions are imposed on the precode output b [k], and the resulting states are restricted.

Such a limitation will be specifically described. As described above, in a recording data sequence generated by RLL (1, 7) encoding, there cannot be one in which two or more '1's are continuous, that is, the following.

A [k] = 1, a [k−1] = 1, a [k−2] = 1 (3) a [k] = 1, a [k−1] = 1, a [k− 2] = 0 (4) a [k] = 0, a [k−1] = 1, a [k−2] = 1 (5) Based on such conditions imposed on the recording data sequence, Examining the conditions imposed on b [k] according to the equation (1), it can be seen that the two states S010 and S101 cannot occur. Therefore, there are 2 ³ −2 = 6 possible states.

Next, the steps will be described. In order to obtain a state that can occur at the next time point j + 1 from the state at a certain time point j as a starting point, it is necessary to separately examine the case where the value a [j + 1] of the recording data at the time point j + 1 is 1 and 0. There is.

Here, the state S000 will be described as an example. According to the above equation (1), S000, that is, n = b
[J] = 0, l = b [j-1] = 0, m = b [j-2]
The recording data pre-coded as = 0 is the following 2
Individuals can be considered.

A [j] = 0, a [j−1] = 0, a [j−2] = 1 (6) a [j] = 0, a [j−1] = 0, a [j− 2] = 0 (7) [when a [j + 1] = 1] At this time, according to equation (1),
b [j + 1] is calculated as follows.

[0054] Therefore, the value of the reproduced signal c [j] is calculated as follows in accordance with the above equation (2).

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 1 + 2A × 0 + B × 0} −AB = − A (9) Also, for the state Snlm at the next time point j + 1, n =
b [j + 1], 1 = b [j], and m = b [j-1]. Then, as described above, b [j + 1] = 1, b
Since [j] = 0 and b [j-1] = 0, the next time point j
The state at +1 is S100. Therefore, a [j
+1] = 1, it can be specified that a transition of S000 → S100 occurs.

[When a [j + 1] = 0] At this time, (1)
According to the equation, b [j + 1] is calculated as follows.

[0057] Therefore, the value of the reproduced signal c [j + 1] is calculated as follows in accordance with the above-described equation (2).

C [j + 1] = {B × b [j + 1] + 2A × b [j] + B × b [j−1]} − AB = {B × 0 + 2A × 0 + B × 0} −AB = − AB (11) Further, regarding the state Snlm at the next time point j + 1,
n = b [j + 1], 1 = b [j], and m = b [j-1]. Then, as described above, b [j + 1] = 0, b
Since [j] = 0 and b [j-1] = 0, the state at the next time point is S000. Therefore, a [j + 1]
If = 0, it can be specified that a transition of S000 → S000 occurs.

In this way, S000 at time j
, The state transitions that can occur at the next time point j + 1 starting from them and the correspondence between the recording data value a [j + 1] and the reproduction signal value c [j + 1] when such state transitions occur Can be requested.

As described above, for each state, the correspondence between the state transition that can occur starting from the state, the value of the recording data and the value of the reproduction signal at the time that each state transition occurs is determined, and the correspondence is shown in the form of a diagram. FIG. 6 shows the result. Time points j and j + 1 described above are not special time points. Therefore, the correspondence between the possible state transitions obtained as described above and the values of the recording data and the values of the reproduction signals accompanying them can be applied at any time. Therefore, FIG.
In, the value of the recording data accompanying the state transition occurring at an arbitrary time point k is denoted as a [k], and the value of the reproduced signal is denoted as c [k].

In FIG. 6, the state transition is represented by an arrow. In addition, the sign given to each arrow indicates [record data value a [k] / reproduction signal value c [k]]. State S
While there are two types of state transitions starting from 000, S001, S111, and S110, only one transition can occur starting from states S011 and S100.

Further, in FIG. 6, S000 and S001
Takes a value of c [k] =-A for a [k] = 1, and transits to S100. On the other hand, a
For [k] = 0, a value of c [k] =-AB is taken, and the process transits to S000. Also, S111 and S1
10 is also the same for the same value of a [k + 1].
It takes the value of [k + 1] and transitions to the same state. Therefore, S000 and S001 can be collectively expressed as S0, and S111 and S110 can be collectively expressed as S2. Further, S011 is set to S3, and S100 is set to S3.
FIG. 7 shows an arrangement that is expressed as 1.

As described above, FIG. 7 is a state transition diagram used in the 4-value 4-state Viterbi decoding method. In FIG. 7,
The four states S0 to S3 and the reproduced signal c [k + 1]
Are shown as -AB, -A, A, and A + B. There are two types of state transition starting from the states S0 and S2, whereas only one state transition starting from the states S1 and S3.

On the other hand, a trellis diagram as shown in FIG. 8 is used as a format for expressing a state transition along time. FIG. 8 shows a transition between two time points, but a transition between many more time points can also be shown. As the time elapses, a state in which the image sequentially transits to the right time point is expressed. Therefore, a horizontal arrow represents a transition to the same state, for example, S0 → S0, and a diagonal arrow represents, for example, S1 → S2.
And so on.

The steps of the above-described Viterbi decoding method, that is, a method of selecting the maximum likelihood state transition from the actual reproduced signal z [k] including noise, based on the state transition diagram shown in FIG. 7, will be described below. .

In order to select the maximum likelihood state transition, first, for the state at a certain time point k, the sum of the likelihoods of the state transitions between a plurality of time points passed in the process of reaching the state is calculated. It is necessary to select the maximum likelihood decoded sequence by comparing the calculated sums of likelihoods. Such a sum of likelihoods is called a path metric.

In order to calculate a path metric, it is first necessary to calculate the likelihood of a state transition between adjacent time points. Such calculation of the likelihood is performed as follows based on the value of the reproduced signal z [k] with reference to the above state transition diagram. First, as a general explanation, the time k-
Consider the case where the state is Sa in state No. 1. At this time, when the reproduction signal z [k] is input to the Viterbi decoder 31, the likelihood that a state transition to the state Sb occurs is calculated according to the following equation. However, the state Sa and the state Sb are any of the four states described in the state transition diagram of FIG.

(Z [k] −c (Sa, Sb)) ² (12) In the above equation, c (Sa, Sb) represents the state transition from the state Sa to the state Sb in the state transition diagram of FIG. This is the value of the described reproduction signal. That is, in FIG. 7 described above, for example, for the state transition S0 → S1, the value is calculated as −A. Therefore, equation (12) is the Euclidean distance between the value of the actual reproduced signal z [k] including noise and the value of the reproduced signal c (Sa, Sb) calculated without considering noise. The path metric at a certain point in time is defined as the sum of likelihoods of state transition between such adjacent points up to that point.

Now, consider the case where the state Sa is at time k. In this case, at time k-1, the state S
If the state that can transition to a is Sp, the path metric L
(Sa, k) is calculated by the following equation using the path metric at the time point k-1.

L (Sa, k) = L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² (13) That is, when the state Sp is reached at the time point k−1 The path metric L (Sp, k−1) and the likelihood (z (z) of the state transition Sp → Sa occurring between the time points k−1 and k)
[K] −c (Sp, Sa)) ² and the path metric L (Sa, k) is calculated. The likelihood of the latest state transition such as (z [k] -c (Sp, Sa)) ² is called a branch metric. However, the branch metric here is a branch metric calculation circuit (BMC) 2 in the Viterbi decoder 13 described later.
A branch metric calculated by 0, ie
The branch metric corresponding to the standardized metric is
Note that they are different.

When the state Sa is at the time point k, there may be a plurality of states that can transition to the state Sa at the time point k-1. In FIG. 7, states S0 and S2 are such cases. That is, if the state S0 is at time k, the state S
There are two states that can transition to 0: S0 and S3. Further, when the state is the state S2 at the time point k, the time point k−1
The states that can transition to the state S2 in are two of S1 and S2.
Individual. As a general explanation, at time k, state S
If the state is a and the two states that can transition to the state Sa at the time point k−1 are Sp and Sq, the path metric L (Sa, k) is calculated as in the following equation.

L (Sa, k) = min ｛L (Sp, k−1) + (z [k] −c (Sp, Sa)) ² , L (Sq, k−1) + (z [k] −c (Sq, Sa)) ² ｝ (14) That is, at time k−1, the state Sp is in effect, and Sp →
The sum of the likelihoods is calculated for each of the case where the state Sa is reached by the state transition Sa and the case where the state Sq is reached at the time k-1 and the state Sq is reached by the state transition Sq → Sa. Then, the respective calculated values are compared, and the smaller value is set as the path metric L (Sa, k) for the state Sa at the time point k.

The calculation of such a path metric is shown in FIG.
Is specifically applied to the above-described quaternary and four states by using, the respective states S0, S1, S2 and S3 at time k
Path metrics L (0, k), L (1,
k), L (2, k) and L (3, k) are at time k−1
Path metric L for each state S0 to S3 in
It can be calculated as follows using (0, k-1) to L (3, k-1).

L (0, k) = min {L (0, k−1) + (z [k] + A + B) ² , L (3, k−1) + (z [k] + A) ² } (15 ) L (1, k) = L (0, k−1) + (z [k] + A) ² (16) L (2, k) = min ｛L (2, k−1) + (z [k ] -AB) ² L (1, k-1) + (z [k] -A) ² 17 (17) L (3, k) = L (2, k-1) + (z [k] −A) ² (18) As described above, the path metric values calculated in this way are compared, and the maximum likelihood state transition may be selected. By the way, in order to select the maximum likelihood state transition, it suffices if the value of the path metric can be compared without calculating the value of the path metric itself. Therefore, in the actual four-value four-state Viterbi decoding method, by using a normalized path metric as defined below instead of the path metric, calculation based on z [k] at each time point k can be easily performed. It is made to do.

M (i, k) = [L (i, k) −z [k] ² − (A + B) ² ] / 2 / (A + B) (19) Equation (19) is applied to each of S0 to S3. When applied, the specific normalized path metric does not include the square calculation as follows. For this reason, addition, comparison,
Calculation in the selection circuit (ACS) 21 can be facilitated.

M (0, k) = min {m (0, k−1) + z [k], m (3, k−1) + α × z [k] −β} (20) m (1, k ) = M (0, k−1) + α × z [k] −β (21) m (2, k) = min ｛m (2, k−1) −z [k], m (1, k−) 1) −α × z [k] −β} (22) m (3, k) = m (2, k−1) + α × z [k] −β (23) However, Expressions (20) to (23) Α and β in the parentheses are as follows.

Α = A / (A + B) (24) β = B × (B + 2 × A) / 2 / (A + B) (25) State transition in the 4-value 4-state Viterbi decoding method based on such a normalized path metric FIG. 9 shows the condition (1). Since there are two expressions for selecting one from two of the four normalized path metrics, there are 2 × 2 = 4 conditions.

[Overview of 4-Valued 4-State Viterbi Decoder] A Viterbi decoder 1 that realizes the 4-valued 4-state Viterbi decoding method described above.
3 will be described below. FIG. 10 shows a Viterbi decoder 13.
1 shows the entire configuration. The Viterbi decoder 13 includes a branch metric calculation circuit (hereinafter, referred to as BMC) 20, an addition, comparison, and selection circuit (hereinafter, referred to as ACS) 2
1, a compression and latch circuit 22 and a path memory unit (hereinafter referred to as PMU) 23. The read clock DCK described above is applied to each of these components.
The operation timing of the entire Viterbi decoder 13 is adjusted by supplying (hereinafter, simply referred to as a clock) in the following description. Hereinafter, each component will be described.

The BMC 20 receives the reproduced signal z
Based on [k], branch metric values BM0, BM1, BM2 and B corresponding to the normalized path metric
Calculate M3. BM0 to BM3 are calculated by the above equation (20).
The following are required to calculate the normalized path metric of (23).

BM0 = z (k) (26) BM1 = α × z [k] −β (27) BM2 = −z (k) (28) BM3 = −α × z [k] −β (29) Α and β required for the calculation are reference values calculated by the BMC 20 according to the above equations (24) and (25). Such a calculation is detected by a method such as envelope detection based on the reproduced signal z [k], for example.
Based on the values of the discrimination points -AB, -A, A, and A + B.

The values of BM0 to BM3 are supplied to the ACS 21. On the other hand, the ACS 21 is supplied with the values of the normalized path metric one clock before (however, those subjected to compression as described later) M0, M1, M2, and M3 from the compression and latch circuit 22 described later. . Then, M0 to M3 and BM0 to BM3 are added, and the latest standardized path metric value L is added as described later.
Calculate 0, L1, L2 and L3. Since M0 to M3 are compressed, it is possible to avoid overflow when calculating L0 to L3.

Further, the ACS 21 selects the maximum likelihood state transition based on the latest standardized path metric values L0 to L3, as described later, and stores it in the path memory 23 in accordance with the selection result. The supplied selection signals SEL0 and SEL2 are set to “High” or “Low”.

The ACS 21 supplies L0 to L3 to the compression and latch circuit 22. The compression and latch circuit 22 latches the supplied L0 to L3 after compressing them. Thereafter, the normalized path metric M0 one clock before
To the ACS 21 as .about.M3.

As a compression method at this time, for example, as shown below, the latest standardized path metrics L0 to L3
Therefore, a method of uniformly subtracting one of them, for example, L0, is used.

M0 = L0-L0 (30) M1 = L1-L0 (31) M2 = L2-L0 (32) M3 = L3-L0 (33) As a result, M0 always takes a value of 0. However, in the following description, it is denoted as M0 as it is in order not to impair generality. The difference between the values of M0 to M3 calculated by the equations (30) to (33) is equal to the difference between the values of L0 to L3. As described above, in the selection of the maximum likelihood state transition, only the value difference between the normalized path metrics becomes a problem. Therefore, such a compression method is effective as a method of compressing the value of the normalized path metric without affecting the selection result of the maximum likelihood state transition and preventing overflow. Thus, the ACS 21 and the compression and latch circuit 22 form a loop related to the calculation of the normalized path metric.

The above-mentioned ACS 21 will be described in more detail with reference to FIG. The ACS 21 includes six adders 51, 52, 53, 54, 56, 58 and two comparators 55, 57. On the other hand, as described above, A
CS 21 is supplied with compressed standardized path metric values M0 to M3 one clock before and branch metric values BM0 to BM3 corresponding to the standardized path metric.

The adder 51 is supplied with M0 and BM0. The adder 51 adds these to calculate L00 as follows.

L00 = M0 + BM0 (34) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above-described equation (26) based on the reproduced signal z [k] input at the time point k, that is, the value of z [k] itself. Therefore, equation (34)
Is obtained by calculating the value of m (0, k-1) + z [k] in the above equation (20) under the effect of the above-described compression. That is, the state S0 at the time point k-1
This is a calculated value corresponding to the case where the state transition S0 finally arrives at the time point k by the state transition S0 → S0.

On the other hand, M3 and BM1 are added to the adder 52.
Is supplied. The adder 51 adds these to calculate the following L30.

L30 = M3 + BM1 (35) As described above, M3 is in the state S3 at the time point k-1.
, Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, B
M1 is calculated based on the reproduced signal z [k] input at the time point k in accordance with the above equation (27), that is, α × z [k] −β. Therefore, the value of equation (35) is calculated by the above equation (2) under the action of compression as described above.
0) in m (3, k-1) + α × z [k] −β. That is, this is a calculated value corresponding to the case where the state is S3 at the time point k−1 and finally reaches the state transition S0 by the state transition S3 → S0 at the time point k.

The above-mentioned L00 and L30 correspond to the comparator 55
Supplied to The comparator 55 compares the values of L00 and L30, and determines the smaller one as the latest standardized path metric L0.
Then, the polarity of the selection signal SEL0 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (20). That is, when L00 <L30 (in this case, S0 → S0 is selected), L00 is output as L0, and SEL0 is set to, for example, 'Low'. If L30 <L00 (in this case, S3 → S0 is selected), L30 is output as L0, and S30 is output.
EL0 is set to, for example, 'High'. SEL0 is supplied to the A-type path memory 24 corresponding to the state S0, as described later.

As described above, the adders 51 and 52 and the comparator 55 are the most likely state transitions at the time point k from S0 → S0 and S3 → S0 in accordance with the above equation (20). Is performed. Then, it outputs the latest standardized path metric L0 and the selection signal SEL0 according to the selection result.

The adder 56 has M0 and BM1.
Is supplied. The adder 51 adds these to calculate the following L1.

L1 = M0 + BM1 (36) As described above, M0 is in the state S0 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
1 is a value calculated according to the above equation (27) based on the reproduced signal z [k] input at the time point k, that is, α × z [k] −β. Therefore, the value of equation (36) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (0, k-1) + α × z [k] −β of 1) is calculated. That is, the calculated value corresponds to the case where the state S0 is at the time point k−1 and the state transition S1 is finally reached by the state transition S0 → S1 at the time point k. In response to the expression (21) not selecting a value, the output of the adder 56 is used as it is as the latest standardized path metric L1.

The adder 53 is supplied with M2 and BM2. The adder 53 adds these to calculate the following L22.

L22 = M2 + BM2 (37) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
0 is a value calculated according to the above equation (28) based on the reproduced signal z [k] inputted at the time point k, that is, -z [k]. Therefore, the value of Expression (37) is a value obtained by calculating the value of m (2, k-1) -z [k] in Expression (22) under the effect of the compression described above. . That is, the calculated value corresponds to the case where the state S2 is at the time point k−1 and the state transition S2 is finally reached by the state transition S2 → S2 at the time point k.

On the other hand, the adder 54 has M1 and BM3
Is supplied. The adder 53 adds these values to calculate L12 as described below.

L12 = M1 + BM3 (38) As described above, M1 is in the state S1 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, equation (38)
Is a value obtained by calculating the value of m (1, k−1) −α × z [k] −β in the above equation (22) under the effect of the above-described compression. That is, the calculated value corresponds to the case where the state S1 is at the time point k−1 and the state transition S2 is finally reached by the state transition S1 → S2 at the time point k.

The above-mentioned L22 and L12 are connected to the comparator 57.
Supplied to The comparator 57 compares the values of L22 and L12, and determines the smaller one as the latest standardized path metric L2.
At the same time, the polarity of the selection signal SEL2 is switched according to the selection result as described above. Such a configuration corresponds to the fact that the minimum value is selected in equation (22). That is, when L22 <L12 (in this case, S2 → S2 is selected), L22 is output as L2, and SEL2 is set to, for example, 'Low'. When L12 <L22 (in this case, S1 → S2 is selected), L12 is output as L2, and S12 is output.
EL2 is set to, for example, 'High'. SEL2 is supplied to the A-type path memory 26 corresponding to the state S2 as described later.

As described above, the adders 53 and 54 and the comparator 57 correspond to the above-mentioned equation (22) to determine the maximum likelihood state transition at time k from S1 → S2 and S2 → S2. Select Then, it outputs the latest standardized path metric L2 and the selection signal SEL2 according to the selection result.

The adder 58 includes M2 and BM3
Is supplied. The adder 58 adds these to calculate the following L3.

L3 = M2 + BM3 (39) As described above, M2 is in the state S2 at the time point k-1.
Is a compressed standardized path metric corresponding to the sum of the state transitions that have passed. Also, BM
Numeral 3 is a value calculated according to the above equation (29) based on the reproduced signal z [k] input at the time point k, that is, -α × z [k] -β. Therefore, the value of equation (39) is calculated by the above equation (2) under the action of compression as described above.
The value of the right side m (2, k-1) + α × z [k] −β of 3) is calculated. That is, the calculated value corresponds to the case where the state S0 is at the time point k−1 and the state transition S3 is finally reached by the state transition S2 → S3 at the time point k. In response to the expression (23) not selecting a value, the output of the adder 58 is used as it is as the latest standardized path metric L3.

As described above, the path memory unit (hereinafter referred to as PMU) 23 operates in accordance with SEL0 and SEL2 output from the ACS 21, thereby decoding the recording data a [k] as the maximum likelihood decoding sequence. Data a '[k] is generated. PMU23
In order to cope with the state transition between the four states shown in FIG. 7, it is composed of two A-type path memories and two B-type path memories.

The A-type path memory has two transitions (ie, a transition from itself and a transition from another state) as transitions to the state, and uses the state as a starting point. The configuration is such that it corresponds to a state having two transitions (ie, a transition leading to itself and a transition leading to another single state). Therefore, the A-type path memory corresponds to S0 and S2 among the four states shown in FIG.

On the other hand, the B-type path memory is configured to cope with a state in which there is only one transition to the state and only one transition starting from the state. Therefore, the B-type path memory corresponds to S1 and S3 among the four states shown in FIG.

In order for the two A-type path memories and the two B-type path memories to operate in accordance with the state transition diagram shown in FIG. 7, the PMU 23 transfers the decoded data as shown in FIG. It is configured to be. That is, the A-type path memory 24 corresponds to S0, and the A-type path memory 26 corresponds to S2. Also, the B-type path memory 25
Corresponds to S1, and the B-type path memory 27 corresponds to S3. With this configuration, state transitions that can occur starting from S0 are S0 → S0 and S0 → S1, and
S2 → S2 and S2
This corresponds to 2 → S3. In addition, the state transition that can occur with S1 as the starting point is only S1 → S2, and the state transition that can occur with S3 as the starting point is only S3 → S0.

FIG. 12 shows a detailed configuration of the A-type path memory 24. The A-type path memory 24 includes a number of flip-flops and selectors corresponding to the path memory length,
They are connected alternately. FIG. 12 shows a configuration corresponding to a decoded data length of 14 bits. That is,
Those having fourteen selectors 31 ₁ to 31 ₁₄ and 15 flip-flops 30 ₀ - 30 _14. Each of the selectors 31 _{1 to} 31 ₁₄ receives two pieces of data, and selectively supplies one of them to a subsequent stage. Further, since the clock is supplied to the flip-flop 30 ₀ - 30 _14, the operation timing of the entire A type path memory 24 is combined.

As described above with reference to FIG. 7, the transition to the state S0 is S0 → S0, that is, the transition inherited from itself, and S3 → S0. As a configuration corresponding to such a situation, each selector includes data supplied from the preceding flip-flop, that is, decoded data corresponding to S0 → S0, and B-type path memory 27 corresponding to state S3.
, Ie, decoded data PM3 corresponding to S3 → S0. Further, each selector has A
SEL0 is supplied from CS21. And SEL0
, One of the two supplied decoded data is supplied to the subsequent flip-flop. Further, the decoded data supplied to the subsequent flip-flop in this manner is also stored in the B-type path memory 25 corresponding to the state S1 in the PM.
Supplied as 0.

[0109] That is, for example, the selector 31 _14, the data supplied from the preceding flip-flops 30 _13, B
14-bit P supplied from the pattern path memory 27
And the data in the 14th bit position of M3. Then, the data selected as follows from these two data, and supplies the subsequent flip-flop 30 _14. As described above, SEL0 sets 'L' in accordance with the selection result.
ow 'or' High '. SEL0 When, for example, 'Low' is adapted to data from the preceding flip-flop 30 ₁₃ is selected. If SEL0 is, for example, 'Hig
At the time of h ', the data at the 14th bit position of PM3 is selected. The selected data is supplied to the subsequent flip-flops 30 _14, also 1 PM0
The data at the fourth bit position is supplied to the B-type path memory 25 corresponding to the state S1.

Another selector 31 in the A-type path memory 24
Also in _{1-31 13,} depending on the polarity of the SEL0, similar operations are performed. Therefore, when SEL0 is, for example, "Low", the A-type path memory 24 as a whole performs a serial shift in the A-type path memory 24 in which each flip-flop inherits the data of the flip-flop located at the preceding stage. . Further, when SEL0 is, for example, “High”, a parallel load that inherits the 14-bit decoded data PM3 supplied from the B-type path memory 27 is performed. In any case, the inherited decoded data is stored in the B-type path memory 2.
5 is supplied as 14-bit decoded data PM0.

[0111] In addition, the flip-flop 30 ₀ on the first stage, always in synchronization with the clock '0' is input. This operation is a state transition S0 → S0 and S0 leading to S0.
In any of 2 → S0, as shown in FIG. 7, since the decoded data is “0”, the latest decoded data always corresponds to “0”.

As described above, the configuration of the A-type path memory 26 corresponding to S2 is the same as that of the A-type path memory 2.
4 is exactly the same. However, the selection signal input from the ACS 21 is SEL2. In addition, as shown in FIG. 6, transitions to the state S2 include S2 → S2, that is, transitions inherited from itself, and S1 → S2. Therefore, the PM1 is stored in the B-type path memory 25 corresponding to the state S1.
Supplied. Further, in response to the state that can occur starting from the state S2 being S2, ie, itself, and S3, the PM2 is stored in the B-type path memory 27 corresponding to the state S3.
Supply.

The A-type path memory 26 corresponding to S2
In this case, '0' is always input to the flip-flop serving as the first processing stage in synchronization with the clock. This operation is performed when the decoded data is “0” as shown in FIG. 7 in any of the state transitions S2 → S2 and S1 → S0 leading to S2.
Therefore, the latest decoded data corresponds to always being '0'.

On the other hand, the detailed configuration of the B-type path memory 25 is shown in FIG. The B-type path memory 25 has a number of flip-flops connected to the path memory length. FIG. 13 shows a configuration corresponding to a decoded data length of 14 bits. That is, it has 15 flip-flops 32 _{0 to} 32 ₁₄ . By supplying a clock to the flip-flops 32 _{0 to} 32 ₁₄ , the operation timing of the entire B-type path memory 25 is adjusted.

Each of the flip-flops 32 _{1 to} 32 ₁₄ has
14-bit decoded data is supplied as PM0 from the A-type path memory 24 corresponding to the state S0. For example, the first bit of PM0 is supplied to the flip-flop 32 ₁ . Each of the flip-flops 32 _{1 to} 32 ₁₄ holds the supplied value for one clock. Then, it outputs it to the A-type path memory 26 corresponding to the state S2 as 14-bit decoded data PM1. For example, flip-flop 3
2 ₁ outputs the second bit of PM1.

Another selector 32 in the B-type path memory 25
Also in _{1-32 13,} similar operation is performed. Therefore, the entire B-type path memory 25 receives the 14-bit decoded data PM supplied from the A-type path memory 24.
0, and supplies 14-bit decoded data PM1 to the A-type path memory 26.

[0117] In addition, the flip-flop 32 _0, always in synchronization with the clock '1' is input. Such actions are:
As shown in FIG. 7, when the latest state transition is S0 → S1, this corresponds to that the decoded data is “1”.

As described above, the configuration of the B-type path memory 27 corresponding to the state S3 is exactly the same as that of the B-type path memory 25. However, as shown in FIG. 7, since the transition to the state S3 is from S2 to S3, PM2 is supplied from the A-type path memory 26 corresponding to the state S2. Further, in response to the state that can occur starting from the state S3 being S0, the A-type path memory 24 corresponding to the state S0
To supply PM3. B type path memory 2
Also in 7, the flip-flop as the first processing stage is always supplied with "1" in synchronization with the clock. This operation is performed as shown in FIG. 7, when the latest state transition is S2 →
The case of S3 corresponds to the fact that the decoded data is '1'.

As described above, each of the four path memories in the PMU 23 generates decoded data. The four pieces of decoded data generated in this way match each other if an accurate Viterbi decoding operation is always performed. By the way, in the actual Viterbi decoding operation, 4
A mismatch may occur in the pieces of decoded data. Such inconsistency is caused by an inaccurate Viterbi decoding operation due to factors such as an error in detecting the above-described identification points A and B due to the influence of noise included in the reproduced signal. .

In general, the probability of occurrence of such inconsistency can be reduced by setting the number of processing stages of the path memory sufficiently large in accordance with the quality of the reproduced signal. That is, when the quality of the reproduction signal such as C / N is good, the probability of occurrence of mismatch between decoded data is small even if the number of processing stages of the path memory is relatively small. On the contrary,
When the quality of the reproduced signal is not good, it is necessary to increase the number of processing stages of the path memory in order to reduce the probability of occurrence of the above-described mismatch. In the case where the number of processing stages of the path memory is relatively small with respect to the quality of the reproduced signal and the probability of occurrence of mismatch between decoded data cannot be sufficiently reduced, a method such as a majority decision is used from the four decoded data Thus, a configuration (not shown) for selecting a more accurate one is provided at the subsequent stage of the four path memories in the PMU 23.

[Viterbi decoding method other than 4-value 4-state Viterbi decoding method] In the 4-value 4-state Viterbi decoding method described above, the waveform equalization characteristic used in the filter unit 11 is PR.
(1, 2, 1) and RLL is used as recording data.
Used when the (1,7) code is adopted. For example, a recording linear density of 0.40 μm, a laser wavelength of 685 nm,
When NA = 0.55, the waveform equalization characteristic is set to PR (1,
2, 1), it is optimal to use a 4-value 4-state Viterbi decoding method. On the other hand, other types of Viterbi decoding methods may be used depending on the waveform equalization characteristics or the encoding method for generating the recording data.

For example, when the waveform equalization characteristic is PR (1, 1) and an RLL (1, 7) code is used as recording data, a ternary 4-state Viterbi decoding method is used. Further, the waveform equalization characteristic is PR (1, 3, 3, 1)
In the case where the RLL (1, 7) code is used as the recording data, a 7-value 6-state Viterbi decoding method is used. Among such Viterbi decoding methods, a waveform equalization characteristic that is one of the elements for selecting which method to use is preferably one that has a high degree of compatibility with intersymbol interference on a reproduced signal. Therefore, as described above, it is optimized in consideration of the linear recording density and the MTF. One embodiment of the present invention (method of generating offset detection timing using Viterbi decoding state data) can be applied to any Viterbi decoding method. In another embodiment of the present invention (method of generating the timing of offset detection using inversion of MSB (Most Significant Bit)), Viterbi decoding having a central amplitude reference value such as ternary or ternary value Not applicable to the method.

Further, deviation of the waveform equalization characteristic from the theoretical value,
Also, the value of the discrimination point may be different from the theory due to amplitude fluctuation of the reproduction signal, asymmetric distortion, and the like. In consideration of such a case, the Viterbi decoding method may be modified and used. For example, in the 4-value 4-state Viterbi decoding method, considering that it is difficult to accurately set the waveform equalization characteristics to PR (1, 2, 1), assuming six identification points as described later. The 6-value 4-state Viterbi decoding method described above may be used.

In the above-described magneto-optical disk device, the reproduced RF signal has a DC component due to optical characteristics (MTF). In the case where a digital modulation method in which the DC component becomes zero on average, such as 8-14 modulation in CD, is adopted, the DC offset does not pose a problem. However, the RLL (1,7) described above
In the case of a code, a DC component is included in the RF signal. Due to this DC component, the reproduced RF signal has an offset corresponding to the average. Moreover, the offset value fluctuates up and down depending on the data pattern of the reproduced RF signal. That is, when a data pattern having a short mark portion and a long space portion and a data pattern having a long mark portion and a short space portion are repeated, the offset value fluctuates considerably. In addition, due to the occurrence of mechanical distortion during the production of a digital substrate, optical birefringence occurs, and the DC level of the reproduced RF signal fluctuates. If there is a change in the offset, the accuracy of Viterbi decoding decreases, and the error rate of decoded data deteriorates.

In the case where the reproduced RF signal is binarized (decoded) using a Viterbi decoder, as shown in FIG. 1, the A / D conversion is performed after the waveform is selected by the filter unit 11 into the partial response characteristic. , And Viterbi decoding is performed digitally. In addition to this configuration, it is also possible to use a digital filter such as a transversal filter or the like to perform Viterbi decoding as partial response characteristics after A / D conversion. The present invention can be applied to any system. Further, in any of the methods, the peak-to-peak of the reproduced RF signal including the fluctuation of the offset needs to be within the dynamic range of the A / D converter. Therefore, if the fluctuation of the offset is large, the peak-to-peak of the actual reproduced RF signal becomes smaller than the dynamic range of the A / D converter. As a result, the resolution of the A / D converter for the reproduced RF signal decreases. This means
Decrease the decoding accuracy of the Viterbi decoder.

Therefore, when decoding a reproduced RF signal using a Viterbi decoder, it is necessary to cancel the fluctuation of the offset. In one embodiment of the present invention,
Generating an offset detection timing based on a sequence of state data (state data value representing a state transition itself selected by the ACS) of the SMU of the Viterbi decoder;
The offset is detected according to the detection timing.
Therefore, in order to perform the Viterbi determination mode, it is assumed that a Viterbi decoder that can generate state data is used. As will be described later, the Viterbi decoder 130 according to an embodiment of the present invention includes state data instead of the PMU 23 included in the Viterbi decoder 13 in the above-described magneto-optical disk device. Status memory unit to be generated (hereinafter referred to as SMU) 1
34 are used.

For example, when there are four states such as a four-valued four-state Viterbi decoding method, these four states can be expressed by two bits. Therefore, such two-bit data is used as a state data value. Can be. Therefore, S0, S1, S2, and S3 in FIG. 7 can be expressed using 2-bit state data values, 00, 01, 11, and 10, respectively. Therefore, in the following description, S in FIG.
0, S1, S2, and S3 are S00, S01, and S1, respectively.
1, and S10.

Also, in the following description, the waveform equalization characteristic is calculated using P (P, B, 2A, B) instead of PR (B, 2A, B).
It is assumed that R (α, β, γ). Such a premise is taken into consideration that in an actual magneto-optical disk device or the like, it is difficult to obtain an ideal partial response characteristic, and the waveform equalization characteristic is often asymmetric.

The reasons why it is difficult to obtain the ideal partial response characteristics include the limitation of the operation accuracy of the waveform equalizer, and asymmetry (waveform asymmetry) due to excessive or excessive laser power during recording. And a phase error of a read clock used when the A / D converter performs sampling from the reproduced signal.

Considering the same as in the case of the above-described four-value four-state Viterbi decoding method, RLL (1,7) coding or the like is performed so that RLmin = 2, and partial response characteristics during reproduction are performed. Is PR (α, β, γ), it can be seen that there are six values and four states. That is,
2 ³ -2 = 6 ｛b [j−1], b [j], b other than the two states excluded by the condition that RLmin = 2
For each set of [j + 1]}, the reproduced signal value c [j + 1] after waveform equalization in an ideal case with no noise takes a different value.

The values of the six discrimination points are denoted by cpqr. Here, p, q, and r are b [j−
1], b [j] and b [j + 1]. Therefore, the branch metric as defined is as follows. Here, since RLmin = 2, it should be noted that c010 and c101 do not exist. FIG. 14 shows the relationship between the value of each identification point and the state transition. The following description is made on the premise that the 6 values and 4 states follow the state transition diagram of FIG.

The branch metrics calculated corresponding to the six state transitions in FIG. 14 are described as follows. First, a 2-bit state data value representing the state before the transition and the state after the transition are written and arranged to form a sequence of four numbers. Next, a branch metric that can occur during one read clock is expressed as a sequence of three numbers by making the two numbers (ie, the second and third numbers) closer to the center into one number. . For example, state transition S11 →
The branch metric associated with S10 is denoted by bm110. In this way, the branch metrics corresponding to the six types of state transition in FIG. 14 can be represented as shown in FIG.

Further, the branch metric defined as the Euclidean distance between the actual reproduced signal value z [k] sampled by the A / D converter operating according to the read clock and the value of each discrimination point is calculated as follows. Is done.

Bm000 = (z [k] −c000) ² (40) bm001 = (z [k] −c001) ² (41) bm011 = (z [k] −c011) ² (42) bm111 = (z [ k] −c111) ² (43) bm110 = (z [k] −c110) ² (44) bm100 = (z [k] −c100) ² (45) When the branch metric is calculated in this way, The value of the identification point is used as it is as the amplitude reference value. When the normalized path metric is used for the purpose of avoiding the square calculation, etc., the branch metric corresponding to the normalized path metric is different from those according to the equations (40) to (45). In such a case, the value of each identification point cannot be used as it is as the amplitude reference value, but the present invention can be applied.

Using the value of such a branch metric, the path metric mij of the state Sij at the time point k is obtained.
[K] is calculated as follows. These equations correspond to the above-mentioned (15) to (1) in the 4-value 4-state Viterbi decoding method.
8).

M10 [k] = m11 [k−1] + bm110 (46) m11 [k] = min {m11 [k−1] + bm111, m01 [k−1] + bm011} (47) m01 [k] = m00 [K-1] + bm001 (48) m00 [k] = min {m00 [k-1] + bm000, m10 [k-1] + bm100} (49) Hereinafter, an embodiment of the present invention will be described with reference to FIG. This will be described below. In one embodiment of the present invention, the present invention is applied to a magneto-optical disk drive. The same components as those in the example of the magneto-optical disk device described above with reference to FIG. The recording system, servo system, and the like, not shown, are the same as those of the above-described magneto-optical disk device.

The structure and operation of the reproducing system will be described. The optical pickup 7, the amplifiers 8 and 9, the changeover switch 10, and the filter unit 11 are the same as those of the example of the magneto-optical disk device described above with reference to FIG. Although not shown, the read clock DCK is also supplied to the controller 2 and its operation timing is adjusted.

The reproduced signal whose waveform has been equalized by the filter unit 11 is output to a subtractor 10 for offset cancellation.
1 is supplied. As described later, the subtractor 101 includes:
The offset signal fed back is supplied, and a reproduced RF signal from which the offset has been removed is generated at the output of the subtractor 101. The output signal of the subtracter 101 is supplied to the A / D converter 12 and the PLL 14. A / D converter 12
Is supplied with a read clock DCK from the PLL 14,
The output of the subtractor 101 is digitized according to the read clock DCK. Then, the sampling value is supplied to the Viterbi decoder 130 and the shift register 102 as a reproduction signal value z [k].

In one embodiment of the present invention, A /
D converter 12 produces a digital output expressed in the form of a two's complement code. Also, if the offset is 0,
Assuming that the output of the A / D converter 12 when there is no signal is 0, the offset value of the reproduced RF signal is represented by the total average of the sampling values. According to the present invention, the offset value is not determined by the total average of the sampling values, and the reproduction RF
The offset is obtained as an average of the sample values at the rising and falling timings of the signal. When canceling the offset, the offset may be performed by digital processing. The present invention is not limited to the two's complement code, and can be applied to a case where the A / D converter 12 generates a binary code output.

The Viterbi decoder 130 generates state data by the SMU 134 based on the supplied reproduced signal value, and generates decoded data by the merge block 135 based on the generated state data, as described later.
Supply to the controller 2. The state data is also supplied to an offset detection timing generation circuit (hereinafter, referred to as a timing generation circuit) 100.

The timing generation circuit 100 generates an offset detection timing based on the status data supplied from the SMU 134 of the Viterbi decoder 130, as described later. Then, based on the offset detection timing, the sampling pulses VG _P , V
G _Q, to generate a VG _R and VG _S. These sampling pulses VG _P , VG _Q , V _{G R,} and V _{G S} are supplied to an offset calculation unit (hereinafter, referred to as OCU) 103
Supplied to

On the other hand, the shift register 102 supplies the reproduced signal value z [k] supplied from the A / D converter 12 to the OCU 103 with a predetermined delay as described above. Shift register 102, a sampling pulse VG _P supplied to OCU103, VG _Q, VG _R and V
It is provided in order to compensate the time shift between the G _S and the reproduction signal value z [k].

[0143] OCU103 is against this way reproduced signal value compensation is made in the delay time, it was sampled according to the sampling pulse VG _P, VG _Q, VG _R and VG _S, based on the sampling values, described later By performing such calculations, an offset signal corresponding to that included in the reproduced RF signal is generated. The offset signal is supplied to the D / A converter 104 and D / A converted. The D / A converted offset signal OE is fed back to the subtractor 101.

In order to generate the offset detection timing, it is assumed that a Viterbi decoder capable of generating state data is used. Viterbi decoder 130
Performs 6-value, 4-state Viterbi decoding as described above. 4
Since each state can be represented by 2 bits, such 2-bit data can be used as a state data value. In this example, the Viterbi decoder 130 performs six-value, four-state Viterbi decoding as shown in the state transition diagram of FIG.

The Viterbi decoder 130 will be described with reference to FIG. The Viterbi decoder 130 has a BMC 132,
ACS 133, SMU 134, and Merge Block 1
35. As the BMC 132 and the ACS 133, for example, the BMC 20 and the ACS 21 in the example of the magneto-optical disk device described above with reference to FIG. However, the selection signals generated by the ACS 133 are described as SEL00 and SEL11 in order to conform to the above-described state description method.

The SMU 134 is based on the selection signals SEL00 and SEL11 supplied from the ACS 133,
State data representing the selected state transition itself is generated and supplied to the timing generation circuit 100 and the merge block 135. The merge block 135 generates decoded data based on the supplied state data.

The SMU 134 will be described with reference to FIG. The PMU 23 described above with reference to FIG. 10 and the like performs processing in units of 1-bit decoded data values, whereas the SMU 134 performs processing in units of 2-bit state data values. .

[0148] As shown in FIG.
A type status memories 150 and 151 and two B type status memories 152 and 153 are provided. Further, select signals SEL00 and SEL1
1. A signal line for transferring a read clock DCK and status data to and from another status memory is connected. However, in the following description, the read clock DCK is referred to as a clock.

The A type status memories 150 and 151 are:
These correspond to states S00 and S11, respectively. Also, the B-type status memories 152 and 153 store the state S0
1 and S10. The connection between these four status memories is in accordance with the state transition diagram of FIG.

The A-type status memory 150 corresponding to the state S00 will be described with reference to FIG. The A-type status memory 150 has n processing stages. That is, n selectors 201 ₀ ... 201
_n-1 and n registers 202 ₀ ... 202 _n-1 are connected alternately. Each selector 201 _{0 to} 201
_The select signal SEL00 is supplied to _n-1 . Further, as described above, the state data inherited from the B-type status memory 153 corresponding to S10 is supplied to each selector as SMin having n bits. Also,
As described above, each register has B corresponding to S01.
The state data inherited by the type status memory 152 is n
It is output as SMout consisting of bits. A clock is supplied to each of the registers 202 _{0 to} 202 _n−1 .

The operation of each selector will be described. FIG.
As shown in FIG. 4, the state one clock before, which can transition to S00, is one of S00 and S10. When the state one clock before is S00, a transition that inherits itself is performed. Therefore, the first-stage selector 201
_{As 0} , 00 is input as the latest state data value in the state data generated by the serial shift. Further, the selector 201 ₀ has S as a parallel load.
10 is the latest status data value SMin [1] in the status data supplied from the B-type status memory 153 corresponding to.
Is supplied. The selector 201 ₀ outputs the selection signal S
According to EL00, one of these two status data values
Pieces supplies it to subsequent-stage register 202 _0.

Further, each of the selectors 201 ₁ to 201 ₁ to
201 _n-1 is two data, ie, one state data value supplied from the B-type status memory 153 corresponding to S10 as a parallel load and one state supplied from the preceding register as a serial shift. And data values. Then, from these two state data, the state data value determined to be the maximum likelihood is supplied to the subsequent register according to the selection signal SEL00. All of the selectors 201 _{0 to} 201 _n-1 have the same selection signal SEL0.
Since it follows 0, the state data as the series of the maximum likelihood state data value selected by the ACS 21 is inherited.

Further, each of the registers 202 _{0 to} 202 _n-1
Updates the held state data value by capturing the supplied state data value according to the clock as described above. Further, as described above, the output of each register is supplied to the status memory corresponding to a state to which a transition can be made after one clock. That is, since the transition can be made to S00 itself, it is supplied to the subsequent selector as a serial shift. The data is supplied to the B-type status memory 153 corresponding to S01 as a parallel load.
From the register 202 _{n-1 at the} last stage, the state data value VM0
0 is output. By outputting state data value VM00 according to the clock, state data is generated as a whole.

The A-type status memory 151 corresponding to the state S11 is configured similarly to the A-type status memory 150, and outputs the state data value VM11 from the last register. However, state data is supplied from the B-type status memory 152 corresponding to S01 as a parallel load corresponding to the state transition S01 → S11 in FIG. Further, the state data is supplied to the B-type status memory 153 corresponding to S10 as a parallel load corresponding to the state transition S11 → S10 in FIG.

Referring to FIG. 20, B-type status memory 152 corresponding to state S01 will be described.
The B-type status memory corresponds to a state in which it does not inherit itself in FIG. 14 and only one state can transition after one clock. Therefore, no serial shift is performed, and no selector is provided. Therefore, n registers 212 ₀ , 212 ₁ ,..., 21
2 _{n -1} are provided, and a clock is supplied to each register to adjust the operation timing.

Each register 212 ₀ , 212 ₁ ,... 2
12 _n−1 is an SM having n bits of status data inherited from the A-type status memory 150 corresponding to S00.
supplied as in. However, the register 212 ₀ on the first processing stage, always 00 are inputted in synchronization with the clock. Such an operation, as shown in FIG.
This corresponds to that the latest state transition that can transition to 1 is always S00. Each of the registers 212 _{0 to} 212 _n-1 is
The stored state data value is updated by capturing the supplied state data value according to the clock.

The output of each register made according to the clock is supplied to the A-type status memory 151 corresponding to the state S11 to which a transition can be made after one clock as state data SMout of n bits. The state data value VM01 is output from the register 212 _{n-1 at the} last stage. By outputting the state data value VM01 in accordance with the clock, the state data is generated as a whole.

The B-type status memory 153 corresponding to the state S10 is configured similarly to the B-type status memory 152, and outputs the state data value VM10 from the last register. However, state data is supplied from the A-type status memory 151 corresponding to S11 as a parallel load corresponding to the state transition S11 → S10 in FIG.
Further, the state data is supplied to the A-type status memory 150 corresponding to S00 as a parallel load corresponding to the state transition S10 → S00 in FIG.

Incidentally, in the Viterbi decoding method, the state data values VM00, V
M11, VM01 and VM10 match each other if the memory length n of the status memory is made sufficiently large. In such a case, any of the state data values generated by the four status memories may be output to the subsequent stage as sm [k + n]. The memory length n is determined in consideration of the C / N of the reproduced signal, frequency characteristics, and the like.

Next, the merge block 135 will be described. The merge block 135 is implemented by means such as a ROM in FIG.
1 is stored. Then, by referring to the decoding matrix, decoded data based on the state data is generated and supplied to the controller 2. It can be seen from the state transition diagram of FIG. 14 that the decoded data value corresponds to two consecutive state data values. That is, the state data value sm [k + n] generated corresponding to the reproduction signal value z [k] and the state data value generated corresponding to the reproduction signal value z [k-1] one clock before the same. Based on sm [k + n-1], the decoded data value at time point k + n can be determined.

For example, if sm [k + n] is “01” and sm
When [k + n-1] is "00", it is understood from FIG. 14 that "1" corresponds to the decoded data value. Such a correspondence is summarized in the decoding matrix table of FIG.

FIG. 22 shows an example of the merge block 135. The merge block 135 includes VM00, VM11,
A state selection circuit 250 for selecting an appropriate one from VM01 and VM10, a register 251 for delaying the output of the state selection circuit 250 by one clock, and a decoding matrix unit 25
2, and state data values VM00, VM11, VM01
Detection circuit 25 for detecting a mismatch between the data and the VM 10
Three.

The state selection circuit 250 outputs AC
With reference to the 2-bit signal MS supplied from S133, the most appropriate one of VM00, VM11, VM01 and VM10 is selected, and the selected state data value is output as VM. The signal MS is a 2-bit signal indicating which of S00, S11, S01, and S10 the path metric value is minimized at each time. The signal MS is, for example, ACS
135 or the like. In this way, the probability that the most correct state data value is selected can be increased.

The VM selected as described above is supplied to the register 251 and the decoding matrix unit 252. The register 251 supplies the supplied VM to the decoding matrix unit 252 with a delay of one clock. In the following description, the output of the register 251 is described as VMD. Accordingly, the state data value VM and the state data value VMD one clock before that are supplied to the decoding matrix unit 252. The decoding matrix unit 252 stores the decoding matrix table shown in FIG. 21 in a means such as a ROM, and refers to the decoding matrix table,
And outputting a decoded data value based on the VMD and the VM.

On the other hand, the mismatch detecting circuit 253 can be constituted by using, for example, an exclusive OR circuit. VM00, VM11, VM01, and VM10 are supplied to the mismatch detection circuit 253, and a mismatch between these four state data values is detected. The detection result is a mismatch detection signal N
Output as M. The non-coincidence detection signal NM is enabled or activated unless all four state data values match. Such a mismatch detection signal can be used for evaluating the quality of the decoded data and the reproduced signal. That is, decoding means for decoding user data or the like from decoded data based on the mismatch detection signal, or operating conditions of the reproduction system can be controlled. The mismatch detection circuit 253 may be provided at any position as long as four position data values can be supplied, and may not necessarily be provided in the merge block 135.

The configuration of the merge block 135 as described above is provided for a case where a mismatch occurs between the state data values due to poor signal quality of the reproduced signal or the like. Therefore, when the signal quality of the reproduced signal is sufficiently good and the probability of occurrence of a mismatch between the state data values is sufficiently small and there is no need to deal with the mismatch between the state data values, the merge block 135 includes the register 251 and the decoding matrix. What is necessary is just to have the part 252.

The merging block 135 is the state selecting circuit 25
If it has 0, the output VM of the state selection circuit 250 is converted to the state data value sm [k +
n] to the timing generation circuit 100.

Next, the Viterbi decoder 130 as described above
State data generated by the SMU 134 in the middle (or the output of the state selection circuit 250 of the merge block 135)
, The generation of the offset detection timing performed by the timing generation circuit 100 will be described with reference to FIG.

FIG. 23 shows an example of a reproduced RF signal supplied to the A / D converter 12, in which sampling points according to a clock are indicated by black circles. The state transition for each clock occurs according to the state transition diagram shown in FIG.
In FIG. 14, at time j, state S00 to state S
It can be seen that when the transition to 01 occurs, the state always transitions to the state S11 at the next time point j + 1. The value of the reproduced RF signal accompanying such a transition is z [j] = c001, z [j + 1] = c011 within the range of an error due to noise or the like.
Becomes Therefore, based on the state data, such a time point j can be recognized as a rising time point of the reproduced RF signal. This will be specifically described with reference to FIG.

In FIG. 23, P is a sampling value which is a reproduction signal value at the time of rising as described above.
That is, since the reproduction signal value P one clock after S00 takes a value near the identification point c001, a transition to the state S01 occurs. Then, the sampling value Q, which is the reproduced signal value one clock after the state S01, is the identification point c01.
Since the value takes a value near 1, a transition to the state S11 occurs. Therefore, it can be confirmed that the reproduced RF signal rises during the period when P and Q are sampled.

On the other hand, in FIG. 14, when a transition from the state S11 to the state S10 occurs at a certain time point j, it is understood that the state always transitions to the state S00 at the next time point. In this case, the transitions are z [j] = c110 and z [j + 1] = c100 within the range of an error due to noise or the like. Therefore, based on the state data, such a time j
Can be recognized as the falling point of the reproduction RF signal. This will be specifically described with reference to FIG.

In FIG. 23, R is a sampling value which is a reproduction signal value at the time of falling as described above.
That is, since the reproduction signal value R one clock after S11 takes a value near the identification point c110, a transition to the state S10 occurs. Then, the sampling value Q, which is the reproduced signal value one clock after the state S10, is the identification point c10.
Since the value takes a value near 00, a transition to the state S00 occurs. Therefore, it can be confirmed that the reproduction RF signal falls during the period in which R and S are sampled. The relationship between P, Q, R, and S and the state transition as described above is as follows.

P: rising point (state S01 → S1)
Reproduction signal value of 1) Q: One clock after rising (state S11 → S1)
0) Reproduced signal value R: Reproduced signal value at the falling point (state S11 → S10) S: One clock after the falling point (state S10 → S0)
The reproduction signal value offset value of 0) is given by the sum of these four sampling values. In Viterbi decoding with six values and four states, these four sampled values are four values excluding the peak-to-peak, so that an offset value can be obtained from the sum of these four sampled values.

Therefore, the values of P, Q, R and S can be sampled and the value of (P + Q + R + S) can be used as an offset. In order to perform such sampling, the timing generating circuit 100
As shown in the figure, the sampling pulses VG _P , VG _Q , V
Generating a G _R and VG _S. This offset value is updated each time a sampling pulse is supplied.

As shown in FIG. 24, the OCU 103
Registers 301, 302, 303 and 304;
An adder 305 for adding values supplied from the registers 301 to 304 is provided. Each register 301, 302, 30
3 and 304 respectively include sampling pulses VG _P,
VG _Q, V G _R, V G _S are supplied. According to such sampling pulses VG _P, VG _Q, V _{G R, and} V _{G S} , each of the registers 301, 302, 303, and 304 can appropriately capture the values of P, Q, R, and S, respectively. Further, a clock is supplied to the adding unit 305.

The reproduction signal value compensated for the delay time supplied from the shift register 102 and the set of sampling pulses VG _P , VG _Q , V _{G R} and V _{G S} are all supplied at the timing according to the clock. , It is not necessary to supply a clock to the adder 305, but the
Clock. Therefore, when the possibility that the operation timing of the adding unit 305 is shifted is sufficiently small, a configuration in which such clock supply is not performed may be adopted. In this manner, the value of the offset signal is calculated by the addition unit 305 adding the values of P, Q, R, and S.

The offset value calculated by the OCU 103 is converted into an analog signal by the D / A converter 104,
This is fed back to the subtractor 101. And the playback R
The offset in the F signal can be canceled.
When generating the timing for offset detection, the PLL 14 that generates the clock DCK needs to be locked. If the phase of the clock DCK is not correct, the phase error affects the detected offset, and the offset cannot be detected accurately. Therefore, the validity / invalidity of the offset detection operation may be determined with reference to a state signal indicating whether or not the PLL 14 is locked.

As described above, S of the Viterbi decoder 130
Using the status data value output from the MU 134 or the status data selected in the merge block 135,
When generating the timing of the offset detection, the offset detection is performed after the data is actually reproduced and the SMU1 is detected.
In addition to the delay up to the input of 34, the memory length of the SMU 134 is delayed. Normally, the SMU 13 of the Viterbi decoder 130
The memory length of No. 4 is long enough to determine the decoded data. Therefore, as described above, the delay between the reproduced RF signal and the detected offset increases, and there is a possibility that the process of canceling the offset may not be improved.

As a countermeasure against this problem, the maximum likelihood state at that stage may be detected from the middle stage of the SMU 134, and the offset detection timing may be generated based on the transition of the state. For example, if the memory length of the SMU 134 is n
In the case of a stage, a transition from the (k-1) th stage in the middle to the kth stage is selected. Then, the state corresponding to the smallest metric is selected. In the Viterbi decoder, the accuracy of the maximum likelihood path increases as the number of metric stages increases.Therefore, by selecting the state corresponding to the smallest metric, the correct state is selected even if the metrics are not merged. Very likely.

FIG. 25 shows another embodiment of the present invention. Portions corresponding to the configuration of the embodiment shown in FIG. 16 are denoted by the same reference numerals. In another embodiment, the timing of offset detection is detected based on the inversion of the MSB (most significant bit) of the output from the A / D converter 12.

In FIG. 25, the A / D converter 12 supplies the reproduction signal value z to the timing generation circuit 105.
The MSB of [k] is supplied. Timing generation circuit 10
5 generates sampling pulses MG _P , MG _Q , MG _R and MG _S having a predetermined time width based on the reproduced signal value. This sampling pulse is supplied to the OCU 103. The OCU 103 generates an offset signal by sampling a reproduction signal from the shift register 102 with a sampling pulse and adding the sampling value, as in the above-described embodiment. Then, the offset signal is supplied to the D / A converter 104, and the output of the D / A converter 104 outputs the offset signal OE.

In another embodiment of the present invention, A
MS in the reproduction signal value sampled by the / D converter 12 in a dynamic range of, for example, 6 to 8 bits.
B inversion is detected, and an offset is detected based on the timing at which MSB inversion occurs. The A / D converter 12 has 2
, The output of the complement code of
When SB is '0', the value of the reproduced signal value z [k] at this point is more than half of the dynamic range. Further, when the MSB at a certain point is “1”, the value of the reproduced signal value z [k] at that point is less than half the dynamic range.

FIG. 23 also shows the change of the MSB in FIG. 23, which is referred to for explaining the generation of the detection timing based on the Viterbi decoding state data. Here, a horizontal line indicating half of the dynamic range is added. The MSB is '0' when the reproduction signal value is half or more of the dynamic range.
/ '1'. As described above, in the 6-value 4-state Viterbi decoding method, since the identification points c001 and c100 are smaller than half of the dynamic range, the MSB is "1" when the reproduction signal value takes these values. Also, since the identification points c011 and c110 are at least half the size of the dynamic range, the MSB becomes '0' when the reproduction signal value takes these values. Therefore, MS
By detecting the bit inversion of B, the rising time and the falling time of the reproduced RF signal can be recognized.

That is, as shown in FIG. 23, when the reproduction signal value rises across the broken line, the MSB changes from “1” to “0”.
Flip to The reproduction signal value at a point one clock before the point at which such inversion is detected can be recognized as the sampling value P at the rising point. To sample the value of P, the sampling pulse MG _P of approximately 1 clock width from the rise time is generated. Further, the sampling value at a point one clock after the rising point is Q. Approximately 1 from MG _P to sample the value of Q
To generate a sampling pulse MG _Q that clock delay.

On the other hand, when the reproduction signal value falls across the broken line, the inversion of the MSB from “0” to “1” is detected. However, the reproduction at the time one clock before the time when the inversion is detected is detected. The signal value can be recognized as the sampling value R at the time of falling. To sample the value of R, and generates a sampling pulse MG _R of approximately 1 clock width from the falling time. In addition, 1
The sampling value at the time after the clock is S. To sample the value of S, to generate a sampling pulse MG _S was approximately 1 clock delay from MG _R.

In the above-described embodiment and other embodiments of the present invention, the offset is detected.
Similarly to the offset detection, it is possible to detect the phase error of the PLL. When there is no phase error of the PLL, the sampling values P, Q, R, and S are (P =
S) (Q = R) holds. Therefore, the phase error can be detected from the difference between these sampling values. As an example, if the phase error is expressed as PE, it can be obtained by the calculation of PE = (PS) + (QR).

FIG. 26 shows an example of an arithmetic circuit capable of generating an offset error OE and a phase error PE. Since any of the Viterbi decoding state data and the inversion of the MSB may be used to generate the timing for generating the sampling pulse, FIG. 26 simply shows the sampling pulses as G _P , G _Q , G _R and G _{Expressed as S.} Non-inverted (indicated by +) or inverted (indicated by-) sampled values P, Q, R, and S are supplied to the adders 305 and 306, respectively. Adder circuit 30
5 outputs the offset signal OE as described above, and the adding circuit 306 outputs the phase error signal PE.

In the above-described embodiment of the present invention, the present invention is applied to a magneto-optical disk device that performs a 4-value 4-state Viterbi decoding method. On the other hand, the present invention can be applied to a magneto-optical disk device that performs another type of Viterbi decoding method such as the above-described three-valued four-state Viterbi decoding method and seven-valued six-state Viterbi decoding method. .

Further, the present invention can be applied to an information reproducing apparatus which can use a Viterbi decoding method to decode read data from a reproduction signal reproduced from data recorded on a recording medium. That is, in addition to the magneto-optical disk (MO), for example, the phase-change disk P
The present invention can be applied to optical disk devices such as rewritable disks such as D and CD-E (CD-Erasable), write-once disks such as CD-R, and read-only disks such as CD-ROM.

Further, the present invention is not limited to this embodiment, and various applications and modifications can be considered without departing from the gist of the present invention.

[0191]

As described above, the present invention is based on the state data of the Viterbi decoder or the A / D conversion output.
The rising and falling timings of the reproduction RF signal are detected, and an offset is detected from the reproduction signal value at the detected timing. Therefore, the circuit to be added for offset cancellation can be made small.
In addition, according to the present invention, since signal processing is performed digitally, there is an advantage that it is not necessary to consider the influence of the temperature characteristics, the band, and the like of each element in the circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an example of a magneto-optical disk device that performs a 4-value 4-state Viterbi decoding method.

FIG. 2 is a schematic diagram for explaining a mark position recording method and a mark edge recording method.

FIG. 3 is a schematic diagram for explaining an example of a sector format of a magneto-optical disk.

FIG. 4 is a schematic diagram showing that the minimum magnetization reversal width is 2 in the RLL (1, 7) encoding method.

FIG. 5 shows a reproduction signal reproduced from data recorded by a combination of an RLL (1, 7) code and a mark edge recording method, with a partial response characteristic PR (1, 2, 2).
FIG. 6 is a schematic diagram for explaining an eye pattern when waveform equalization is performed under 1).

FIG. 6 is a schematic diagram for explaining a process of creating a state transition diagram of the 4-value 4-state Viterbi decoding method.

FIG. 7 is a schematic diagram illustrating an example of a state transition diagram of a 4-value 4-state Viterbi decoding method.

FIG. 8 is a schematic diagram illustrating an example of a trellis diagram in a 4-level 4-state Viterbi decoding method.

FIG. 9 is a schematic diagram showing conditions of state transition based on a standardized metric in a four-value four-state Viterbi decoding method.

FIG. 10 is a block diagram illustrating an overall configuration of a Viterbi decoder that performs 4-level 4-state Viterbi decoding.

FIG. 11 is a block diagram showing a configuration of a part of the Viterbi decoder in detail.

FIG. 12 is a block diagram showing the configuration of another part of the Viterbi decoder in detail.

FIG. 13 is a block diagram showing the configuration of still another portion of the Viterbi decoder in detail.

FIG. 14 is a schematic diagram illustrating an example of a state transition diagram of a 6-value 4-state Viterbi decoding method.

FIG. 15 is a schematic diagram illustrating an example of a trellis diagram in a 6-value 4-state Viterbi decoding method.

FIG. 16 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 17 is a block diagram illustrating an example of a Viterbi decoder used in an embodiment of the present invention.

FIG. 18 is a block diagram showing an example of a configuration of a status memory unit (SMU) used in one embodiment of the present invention.

FIG. 19 is a block diagram for describing a partial configuration of an SMU.

FIG. 20 is a block diagram for describing another partial configuration of the SMU.

FIG. 21 is a schematic diagram illustrating an example of a table referred to in a merge block according to an embodiment of the present invention.

FIG. 22 is a block diagram illustrating an example of a merge block according to an embodiment of the present invention;

FIG. 23 is a waveform chart for describing a method of detecting an offset.

FIG. 24 is a block diagram of an example of a configuration of an offset operation unit used in an embodiment of the present invention.

FIG. 25 is a block diagram of another embodiment of the present invention.

FIG. 26 is a block diagram illustrating an example of a configuration of a calculation unit that can obtain both an offset and a phase error.

[Explanation of symbols]

2 ... controller, 12 ... A / D converter, 13
0 ... Viterbi decoder, 132 ... Branch metric calculation circuit (BMC), 133 ... Addition, comparison, selection circuit (ACS), 134 ... Status memory unit (SMU), 135 ...・ Merge block, 100 ・
..Timing generation circuit, 101 ... subtractor, 103
... Offset calculation unit (OCU)

Claims (7)

[Claims] An information reproducing apparatus for decoding a reproduction signal reproduced on a recording medium by a Viterbi decoding method, wherein a maximum likelihood state transition itself is expressed based on a reproduction signal value sampled according to a clock. State data generating means for generating state data for each clock, decoded data output means for outputting decoded data based on the state data, and corresponding to a rising or falling edge of a reproduced signal from the state data. Means for generating an offset detection timing, means for generating an offset signal by calculating the reproduction signal value at the detection timing, and feedback for the offset signal to the reproduction signal to cancel the offset. And a signal path. Reproducing apparatus. 2. The information reproducing apparatus according to claim 1, wherein the status data is a sequence of status data values having a bit number determined according to a type of Viterbi decoding method. 3. The state data generating means according to claim 1, wherein said state data generating means includes a state memory unit, and based on state data extracted at a stage of a memory length shorter than a memory length of said state memory unit outputting decoded data. An information reproducing apparatus for generating the detection timing. 4. The reproduction signal value according to claim 1, wherein the reproduction signal value is in the form of a code having 2's complement, and the offset signal is generated by adding the reproduction signal value at the detection timing. An information reproducing apparatus characterized by the above-mentioned. 5. An information reproducing apparatus for decoding a reproduction signal reproduced on a recording medium by a Viterbi decoding method, wherein a predetermined number of bits are reproduced from an A / D converter provided in a stage preceding the Viterbi decoder. Means for generating an offset detection timing based on a timing at which inversion of the MSB in the signal occurs; means for generating an offset signal by calculating the reproduction signal value at the detection timing; And a signal path for canceling the offset by feeding back to the information reproducing apparatus. 6. An information reproducing method for decoding a reproduced signal reproduced on a recording medium by a Viterbi decoding method, wherein a maximum likelihood state transition itself is expressed based on a reproduced signal value sampled according to a clock. Generating state data for each clock, outputting decoded data based on the state data, and detecting an offset detection timing corresponding to a rising or falling edge of a reproduction signal from the state data. Generating an offset signal by calculating the reproduction signal value at the detection timing; and feeding back the offset signal to the reproduction signal to cancel the offset. An information reproducing method characterized by the following. 7. An information reproducing method for decoding a reproduction signal reproduced on a recording medium by a Viterbi decoding method, wherein a predetermined number of bits are reproduced from an A / D converter provided in a stage preceding the Viterbi decoder. Generating an offset detection timing based on the timing at which the MSB in the signal occurs; generating an offset signal by calculating the reproduction signal value at the detection timing; And a step of canceling the offset by feeding back the information.