JPH10303353A - Method for manufacturing composite lead frame with heat sink - Google Patents

Method for manufacturing composite lead frame with heat sink

Info

Publication number
JPH10303353A
JPH10303353A JP10495397A JP10495397A JPH10303353A JP H10303353 A JPH10303353 A JP H10303353A JP 10495397 A JP10495397 A JP 10495397A JP 10495397 A JP10495397 A JP 10495397A JP H10303353 A JPH10303353 A JP H10303353A
Authority
JP
Japan
Prior art keywords
metal
lead frame
layer
metal layer
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10495397A
Other languages
Japanese (ja)
Inventor
Katsumi Suzuki
勝美 鈴木
Takuya Yonekawa
琢哉 米川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP10495397A priority Critical patent/JPH10303353A/en
Publication of JPH10303353A publication Critical patent/JPH10303353A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for pasting a metal layer to an insulation layer for shorter manufacturing process while heat radiation characteristics and electric characteristics are improved, by irradiating an insulating layer of a composite interconnection board comprising a metal layer with a laser beam for removal, and forming a connection hole and an exposed part for metal lead frame connection. SOLUTION: On first and second surfaces of insulating layers 2 and 4, a composite interconnection board 10 comprising first and second metal layers 1 and 3 is prepared, and the first metal layer 1 is worked to form lead patterns 1a and 1b. A residual part of the first metal layer 1 is removed, and by forming connection holes 2a and 2b while a chip mounting region is allowed to remain at the insulating layer 2 from such part as the first metal layer 1 is removed, such an exposed part as exposed on the first surface side of the insulating layer 2 is formed at the second metal layer 3. A semiconductor chip 6 is fixed to a chip formation region 2a of the insulating layer, and the semiconductor chip 6 is connected to the lead patterns 1a and 1b and the exposed part of the second metal layer 3 with a bonding wire 8, and the entire is sealed up with a mold resin.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に用いら
れる複合リードフレームの製造方法に関し、特に、放熱
板を有する複合リードフレームの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite lead frame used for a semiconductor device, and more particularly to a method for manufacturing a composite lead frame having a heat sink.

【0002】[0002]

【従来技術】半導体パッケージに使用されるリードフレ
ームのひとつに、QFP(Quad Flat Package )型リー
ドフレームがある。このリードフレームは、所定の厚み
を有する銅板をプレス又はエッチング加工することによ
り構成され、機械的強度に優れる反面、半導体チップの
高集積化、高出力化の要求に対して電気特性および放熱
特性が追従できないという不都合がある。このような要
求に応えるため、絶縁層の一方の面に信号用リードを配
置し、もう一方の面に電源あるいは接地用リードを配置
した多層リードフレームや、半導体チップの放熱を促す
放熱板を設けた放熱板付きリードフレームが提案されて
いる。
2. Description of the Related Art One of lead frames used for a semiconductor package is a QFP (Quad Flat Package) type lead frame. This lead frame is formed by pressing or etching a copper plate having a predetermined thickness, and while having excellent mechanical strength, the electrical characteristics and heat radiation characteristics for the demand for higher integration and higher output of the semiconductor chip. There is an inconvenience of not being able to follow. To meet such demands, a multi-layer lead frame with signal leads on one side of the insulating layer and power or ground leads on the other side, and a heat sink that promotes heat dissipation from the semiconductor chip are provided. Further, a lead frame with a heat sink has been proposed.

【0003】しかし、これらのリードフレームは金属リ
ードフレームによって形成されているので、多ピン化、
狭ピッチ化に対応することが難しい。金属リードフレー
ムではインナーリードのピッチを0.2mm以下で形成
することは困難であり、多ピン化に限界がある。
However, since these lead frames are formed by metal lead frames, the number of pins is increased,
It is difficult to cope with narrow pitch. In a metal lead frame, it is difficult to form the inner lead with a pitch of 0.2 mm or less, and there is a limit to increasing the number of pins.

【0004】かかる問題を解決するものとして、特開平
5−21690号公報に開示される放熱板付き複合リー
ドフレームがある。この放熱板付き複合リードフレーム
は、絶縁フィルムの一方の面に銅箔で形成されたインナ
ーリードと、もう一方の面に銅箔で形成された接地層
と、接地層に取り付けられた放熱板より構成され、半導
体チップの電極は絶縁フィルムに形成された接続用の穴
を介して接地層とボンディングワイヤで電気的に接続さ
れており、インナーリードは金属リードフレームで構成
されたアウターリードと接続されている。
In order to solve such a problem, there is a composite lead frame with a heat sink disclosed in Japanese Patent Application Laid-Open No. Hei 5-21690. This composite lead frame with a heat sink is composed of an inner film made of copper foil on one side of an insulating film, a ground layer made of copper foil on the other side, and a heat sink attached to the ground layer. The electrodes of the semiconductor chip are electrically connected to a ground layer and bonding wires via connection holes formed in the insulating film, and the inner leads are connected to outer leads formed of a metal lead frame. ing.

【0005】[0005]

【発明が解決しようとする課題】しかし、従来の放熱板
付き複合リードフレームによると、絶縁フィルムに穴開
け等の所定の加工を施した後に金属層および放熱板を貼
り合わせているため、絶縁フィルムのパンチング工程や
金属層の貼り合わせ工程が必要となって製造に手間を要
する。また、複合リードフレームの多ピン化、狭ピッチ
化によって配線パターンの微細化が進むと、上記した貼
り合わせにおける位置決め精度に限界が生じる。従っ
て、本発明の目的は金属層と絶縁層の貼り付けを不要に
して製造工程を短縮でき、放熱特性および電気特性の改
善された放熱板付き複合リードフレームの製造方法を提
供することにある。
However, according to the conventional composite lead frame with a heat sink, the metal layer and the heat sink are bonded after the insulating film is subjected to predetermined processing such as perforation. This requires a punching step and a bonding step of a metal layer, which requires time and effort in manufacturing. Further, as the fineness of the wiring pattern progresses due to the increase in the number of pins and the pitch of the composite lead frame, the positioning accuracy in the above-mentioned bonding is limited. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of manufacturing a composite lead frame with a heat sink having improved heat dissipation characteristics and electrical characteristics, which eliminates the need for attaching a metal layer and an insulating layer, thereby shortening the manufacturing process.

【0006】本発明の他の目的は配線パターンが微細化
しても絶縁フィルムに高精度な穴開け等の加工処理を行
うことができる放熱板付き複合リードフレームの製造方
法を提供することにある。
Another object of the present invention is to provide a method of manufacturing a composite lead frame with a heat sink, which can perform a processing such as high-precision drilling on an insulating film even when a wiring pattern is miniaturized.

【0007】[0007]

【課題を解決するための手段】本発明は上記した目的を
実現するため、絶縁層の第1および第2の面に第1およ
び第2の金属層を有する複合配線基板を準備し、前記第
1の金属層を加工してリードパターンを形成し、かつ、
前記第1の金属層の残余の部分を除去し、前記第1の金
属層を除去した部分から前記絶縁層にチップ搭載領域を
残しながら接続用ホールを形成することにより前記第2
の金属層に前記絶縁層の前記第1の面側に露出した露出
部を形成し、前記絶縁層の前記チップ搭載領域に半導体
チップを固定し、前記半導体チップを前記リードパター
ンおよび前記第2の金属層の前記露出部にボンディング
ワイヤで接続し、前記リードパターンの外側に金属リー
ドフレームを配置して前記リードパターンに金属接合に
よって前記金属リードフレームを接続し、前記金属リー
ドフレームの所定の部分を露出しながら全体をモールド
樹脂で封止する放熱板付き複合リードフレームの製造方
法を提供する。
According to the present invention, there is provided a composite wiring board having first and second metal layers on first and second surfaces of an insulating layer. Forming a lead pattern by processing the first metal layer; and
By removing a remaining portion of the first metal layer and forming a connection hole while leaving a chip mounting region in the insulating layer from the portion from which the first metal layer has been removed, the second hole is formed.
Forming an exposed portion exposed on the first surface side of the insulating layer in the metal layer, fixing a semiconductor chip in the chip mounting region of the insulating layer, and attaching the semiconductor chip to the lead pattern and the second pattern. A metal wire is connected to the exposed portion of the metal layer with a bonding wire, a metal lead frame is arranged outside the lead pattern, the metal lead frame is connected to the lead pattern by metal bonding, and a predetermined portion of the metal lead frame is connected. Provided is a method for manufacturing a composite lead frame with a heat sink, which is entirely exposed and sealed with a mold resin.

【0008】本発明の実施の形態において、接続用ホー
ルおよび露出部の形成は、レーザビームの照射に基づい
て行われても良い。金属接合は、リードパターンの表面
に設けられるNi下地Auめっきと、金属リードフレー
ムの表面に設けられるSnめっきのAu−Sn共晶接合
に基づいて行われることが好ましい。第2の金属層は、
接続用ホールおよび露出部の形成面と反対面に銅よりな
る放熱板を固定されても良い。この放熱板は、放熱面に
ディンプル加工あるいはスルーホールを形成され、その
厚さは少なくとも100μmであることが好ましい。
In the embodiment of the present invention, the formation of the connection hole and the exposed portion may be performed based on laser beam irradiation. The metal bonding is preferably performed based on Au-Sn eutectic bonding of Ni plating Au plating provided on the surface of the lead pattern and Sn plating provided on the surface of the metal lead frame. The second metal layer is
A heat sink made of copper may be fixed to the surface opposite to the surface on which the connection hole and the exposed portion are formed. The heat sink has dimples or through holes formed on the heat dissipation surface and preferably has a thickness of at least 100 μm.

【0009】[0009]

【発明の実施の形態】図1は、本発明の第1の実施の形
態の放熱板付き複合リードフレームの製造工程を示す。
まず、図1(a) に示すように、リードパターンを形成す
るための厚さ18μmの金属層(銅箔)1と、厚さ25
μmのポリイミド層2と、接地層および放熱板を形成す
るための厚さ105μmの金属層(銅板)3と、厚さ1
5μmのポリイミド層4を積層して構成される複合配線
基板としての2層銅貼りTABテープ10を用意する。
FIG. 1 shows a manufacturing process of a composite lead frame with a heat sink according to a first embodiment of the present invention.
First, as shown in FIG. 1A, a metal layer (copper foil) 1 having a thickness of 18 μm for forming a lead pattern and a
μm polyimide layer 2, 105 μm thick metal layer (copper plate) 3 for forming a ground layer and a heat sink, and 1 μm thick
A two-layer copper-attached TAB tape 10 as a composite wiring board constituted by laminating 5 μm polyimide layers 4 is prepared.

【0010】以下、TABテープ10を用いた放熱板付
き複合リードフレームの製造工程を説明する。
Hereinafter, a manufacturing process of a composite lead frame with a heat sink using the TAB tape 10 will be described.

【0011】図1(b) は、配線パターン形成工程を示
し、TABテープ10に既知のレジスト塗布、マスク露
光、現像、エッチング、レジスト剥離等の処理を行うこ
とによって金属層1にリードパターン1aおよび1bを
形成する。
FIG. 1 (b) shows a wiring pattern forming step, in which a known process such as resist coating, mask exposure, development, etching, and resist stripping is performed on the TAB tape 10 to form a lead pattern 1a and a metal layer 1 on the metal layer 1. 1b is formed.

【0012】図1(c) は、素子搭載部およびリード接合
部の形成工程を示し、所定の位置に開口を有するレーザ
遮蔽金属マスク(図示せず)をTABテープ10に配置
してレーザビームを照射する。レーザビームの照射され
た部分はポリイミド層2が除去されて金属層3が露出す
る。このことによってグランドホール2aおよびリード
接合部2bが形成される。この後、レーザ加工時に残っ
た微細なポリイミドを50℃の過マンガン酸カリウムと
苛性ソーダ溶液によって除去する。また、図1(c) で
は、ポリイミド層2に素子搭載部2Aを形成している。
FIG. 1C shows a process of forming an element mounting portion and a lead bonding portion. A laser shielding metal mask (not shown) having an opening at a predetermined position is arranged on a TAB tape 10 to apply a laser beam. Irradiate. The polyimide layer 2 is removed from the portion irradiated with the laser beam, and the metal layer 3 is exposed. As a result, the ground hole 2a and the lead joint 2b are formed. Thereafter, the fine polyimide remaining during the laser processing is removed with potassium permanganate and a sodium hydroxide solution at 50 ° C. In FIG. 1C, the element mounting portion 2A is formed on the polyimide layer 2.

【0013】図1(d) は、Ni下地Auめっき工程を示
し、リードパターン1aおよび1bの表面と、グランド
ホール2aおよびリード接合部2bの形成に基づいて露
出した金属層3に厚さ2.0μmのNiめっきを施し、
その上層に厚さ0.8μmのAuめっきを施すことによ
ってNi下地Auめっき層5を形成する。このめっき処
理後、TABテープ10は個片に打ち抜かれる。
FIG. 1 (d) shows a Ni base Au plating step, in which the surface of the lead patterns 1a and 1b and the metal layer 3 exposed based on the formation of the ground holes 2a and the lead joints 2b have a thickness of 2.0 mm. 0μm Ni plating
An Au plating with a thickness of 0.8 μm is applied to the upper layer to form a Ni base Au plating layer 5. After this plating process, the TAB tape 10 is punched into individual pieces.

【0014】図1(e) は、金属リードフレームとの接続
工程を示し、先端にSnめっきを施された金属リードフ
レーム7を用意して、Ni下地Auめっき層5を形成さ
れたリードパターン1aおよびリード接合部2bに接触
させて所定の温度に加熱する。この加熱によってめっき
が溶融し、Ni下地AuめっきとSnめっきによるAu
/Sn共晶接合に基づいて金属リードフレーム7とリー
ドパターン1aおよびリード接合部2bが接合される。
また、素子搭載部2Aには半導体チップ6が搭載され
る。
FIG. 1 (e) shows a step of connecting to a metal lead frame. A metal lead frame 7 having a Sn plating applied to its tip is prepared, and a lead pattern 1a having a Ni base Au plating layer 5 is formed. Then, it is brought into contact with the lead joint 2b and heated to a predetermined temperature. The plating melts by this heating, and the Au by Ni plating and the Au by Sn plating are melted.
The metal lead frame 7 is joined to the lead pattern 1a and the lead joint 2b based on the / Sn eutectic joining.
The semiconductor chip 6 is mounted on the element mounting portion 2A.

【0015】図1(f) は、半導体チップ6とリードパタ
ーン1a,1b、およびグランドホール2aの接続工程
を示し、半導体チップ6の電極6aとリードパターン1
a,1b、およびグランドホール2aをボンディングワ
イヤ8によって電気的に接続する。この後、モールド樹
脂によって金属リードフレーム7の所定の部分を露出さ
せた状態で樹脂封止される。
FIG. 1F shows a process of connecting the semiconductor chip 6 to the lead patterns 1a and 1b and the ground hole 2a.
a, 1b and the ground hole 2a are electrically connected by the bonding wire 8. Thereafter, the metal lead frame 7 is sealed with a resin in a state where a predetermined portion of the metal lead frame 7 is exposed.

【0016】上記した放熱板付き複合リードフレームに
よると、金属層とポリイミド層が積層されたリードフレ
ーム材を使用するので、金属層とポリイミド層の貼り合
わせが不要になり、製造工程を短縮することができる。
また、ポリイミド層にレーザビームを照射してグランド
ホールおよびリード接合部を形成するので、リードフレ
ームの多ピン化、狭ピッチ化に関係なくポリイミド層の
高精度な加工が可能になる。第1の実施の形態では、接
地層の厚みがインナーリードの厚みより大なるリードフ
レーム材を使用することによって電気特性が改善される
とともに接地層の放熱性が向上する。
According to the above-described composite lead frame with a heat sink, a lead frame material in which a metal layer and a polyimide layer are laminated is used, so that the bonding of the metal layer and the polyimide layer becomes unnecessary, and the manufacturing process is shortened. Can be.
In addition, since the ground hole and the lead joint are formed by irradiating the polyimide layer with a laser beam, high-precision processing of the polyimide layer becomes possible irrespective of increasing the number of pins and reducing the pitch of the lead frame. In the first embodiment, by using a lead frame material in which the thickness of the ground layer is larger than the thickness of the inner lead, the electrical characteristics are improved and the heat dissipation of the ground layer is improved.

【0017】図2は、第2の実施の形態の放熱板付き複
合リードフレームの製造工程を示す。まず、図2(a) に
示すようにリードパターンを形成するための厚さ18μ
mの金属層(銅箔)1と、厚さ25μmのポリイミド層
2と、接地層を形成するための厚さ75μmの金属層
(銅板)3と、厚さ15μmのポリイミド層4を積層し
て構成される複合配線基板としての2層銅貼りTABテ
ープ20を用意する。以下、第1の実施の形態と共通す
る部分については重複する説明を省略し、製造工程の相
違する部分について説明する。
FIG. 2 shows a manufacturing process of the composite lead frame with a heat sink according to the second embodiment. First, as shown in FIG. 2A, a thickness of 18 μm for forming a lead pattern is formed.
m metal layer (copper foil) 1, a polyimide layer 2 having a thickness of 25 μm, a metal layer (copper plate) 3 having a thickness of 75 μm for forming a ground layer, and a polyimide layer 4 having a thickness of 15 μm. A two-layer copper-bonded TAB tape 20 as a composite wiring board to be configured is prepared. In the following, a description of a part common to the first embodiment will not be repeated, and a part different in the manufacturing process will be described.

【0018】図2(f) は、半導体チップ6とリードパタ
ーン1a,1b、およびグランドホール2aの接続工程
および放熱板9の貼り付け工程を示し、半導体チップ6
の電極6aとリードパターン1a,1b、およびグラン
ドホール2aをボンディングワイヤ8によって電気的に
接続した後、厚さ125μmの放熱板9をポリイミド層
4に貼り付けている。また、この放熱板9は、ポリイミ
ド層4を除去して金属層3に直接貼りつけることもでき
る。
FIG. 2F shows a step of connecting the semiconductor chip 6 to the lead patterns 1a and 1b and the ground hole 2a and a step of attaching the heat sink 9 to the semiconductor chip 6.
After the electrodes 6a are electrically connected to the lead patterns 1a and 1b and the ground holes 2a by bonding wires 8, a heat radiating plate 9 having a thickness of 125 μm is attached to the polyimide layer 4. Further, the heat sink 9 can be directly attached to the metal layer 3 after removing the polyimide layer 4.

【0019】上記した放熱板付き複合リードフレームに
よると、放熱板9を後付けすることによって放熱特性を
更に向上させることができる。また、放熱板9の表面に
ディンプル加工を施すことによって、樹脂封止時におけ
る放熱板9と封止樹脂との密着性が向上する。あるい
は、ディンプル加工以外の方法として多数のスルーホー
ルを放熱板9に形成しても同様の効果を奏することがで
きる。
According to the above-described composite lead frame with a heat radiating plate, the heat radiating characteristics can be further improved by attaching the heat radiating plate 9 later. Further, by performing dimple processing on the surface of the heat radiating plate 9, the adhesion between the heat radiating plate 9 and the sealing resin at the time of resin sealing is improved. Alternatively, the same effect can be obtained by forming a large number of through holes in the heat sink 9 as a method other than the dimple processing.

【0020】[0020]

【発明の効果】以上説明した通り、本発明の放熱板付き
複合リードフレームの製造方法によると、絶縁層の第1
および第2の面に第1および第2の金属層を有する複合
配線基板の絶縁層にレーザビームを照射して除去するこ
とによって接続用ホールおよび金属リードフレーム接続
用の露出部を形成するようにしたため、金属層と絶縁層
の貼り付けを不要にして製造工程を短縮でき、放熱特性
および電気特性を改善でき、配線パターンが微細化して
も絶縁フィルムに高精度な穴開け等の加工処理を行うこ
とができる。
As described above, according to the method for manufacturing a composite lead frame with a heat sink of the present invention, the first of the insulating layers is formed.
And irradiating the insulating layer of the composite wiring substrate having the first and second metal layers on the second surface with a laser beam to remove the insulating layer, thereby forming a connection hole and an exposed portion for connecting a metal lead frame. As a result, it is not necessary to attach the metal layer and the insulating layer, and the manufacturing process can be shortened, the heat radiation characteristics and the electric characteristics can be improved, and even if the wiring pattern is miniaturized, processing such as high-precision drilling is performed on the insulating film. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態における放熱板付き
複合リードフレームの製造工程を示す説明図。
FIG. 1 is an explanatory view showing a manufacturing process of a composite lead frame with a heat sink according to a first embodiment of the present invention.

【図2】本発明の第2の実施の形態における放熱板付き
複合リードフレームの製造工程を示す説明図。
FIG. 2 is an explanatory view showing a manufacturing process of a composite lead frame with a heat sink according to a second embodiment of the present invention.

【符号の説明】 1,銅箔層 1a,リードパターン 1b,リードパターン 2,ポリイミド層 2A,素子搭載部 2a,グランドホール 2b,リード接合部 3,銅板層 4,ポリイミド層 5,Ni下地Auめっき 6,半導体チップ 6a,電極 7,金属リードフレーム 8,ボンディングワイヤ 9,放熱板 10,TABテープ 20,TABテープ[Description of Signs] 1, copper foil layer 1a, lead pattern 1b, lead pattern 2, polyimide layer 2A, element mounting portion 2a, ground hole 2b, lead joint portion 3, copper plate layer 4, polyimide layer 5, Ni plating Au plating 6, semiconductor chip 6a, electrode 7, metal lead frame 8, bonding wire 9, heat sink 10, TAB tape 20, TAB tape

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層の第1および第2の面に第1およ
び第2の金属層を有する複合配線基板を準備し、 前記第1の金属層を加工してリードパターンを形成し、
かつ、前記第1の金属層の残余の部分を除去し、 前記第1の金属層を除去した部分から前記絶縁層にチッ
プ搭載領域を残しながら接続用ホールを形成することに
より前記第2の金属層に前記絶縁層の前記第1の面側に
露出した露出部を形成し、 前記絶縁層の前記チップ搭載領域に半導体チップを固定
し、 前記半導体チップを前記リードパターンおよび前記第2
の金属層の前記露出部にボンディングワイヤで接続し、 前記リードパターンの外側に金属リードフレームを配置
して前記リードパターンに金属接合によって前記金属リ
ードフレームを接続し、 前記金属リードフレームの所定の部分を露出しながら全
体をモールド樹脂で封止することを特徴とする放熱板付
き複合リードフレームの製造方法。
1. A composite wiring board having first and second metal layers on first and second surfaces of an insulating layer is prepared, and the first metal layer is processed to form a lead pattern;
And removing the remaining portion of the first metal layer, and forming a connection hole while leaving a chip mounting region in the insulating layer from the portion from which the first metal layer has been removed. Forming an exposed portion of the insulating layer exposed on the first surface side of the insulating layer, fixing a semiconductor chip to the chip mounting region of the insulating layer, and connecting the semiconductor chip to the lead pattern and the second
Connecting the metal lead frame to the exposed portion of the metal layer with a bonding wire, arranging a metal lead frame outside the lead pattern, connecting the metal lead frame to the lead pattern by metal bonding, and a predetermined portion of the metal lead frame. A method of manufacturing a composite lead frame with a heat sink, wherein the entire structure is sealed with a mold resin while exposing the resin.
【請求項2】 前記接続用ホールおよび前記露出部の形
成は、レーザビームの照射に基づいて行われる請求項第
1項記載の放熱板付き複合リードフレームの製造方法。
2. The method according to claim 1, wherein the formation of the connection hole and the exposed portion is performed based on laser beam irradiation.
【請求項3】 前記金属接合は、前記リードパターンの
表面に設けられるNi下地Auめっきと、前記金属リー
ドフレームの表面に設けられるSnめっきのAu−Sn
共晶接合に基づいて行われる請求項第1項記載の放熱板
付き複合リードフレームの製造方法。
3. The method according to claim 1, wherein the metal bonding is performed by Au plating of Ni underlayer provided on the surface of the lead pattern and Au-Sn of Sn plating provided on the surface of the metal lead frame.
The method for manufacturing a composite lead frame with a heat sink according to claim 1, wherein the method is performed based on eutectic bonding.
【請求項4】 前記第2の金属層は、前記接続用ホール
および前記露出部の形成面と反対面に銅よりなる放熱板
を固定される請求項第1項記載の放熱板付き複合リード
フレームの製造方法。
4. The composite lead frame with a radiator plate according to claim 1, wherein the second metal layer has a radiator plate made of copper fixed to a surface opposite to a surface on which the connection holes and the exposed portions are formed. Manufacturing method.
【請求項5】 前記放熱板は、放熱面にディンプル加工
あるいはスルーホールを形成され、その厚さは少なくと
も100μmである請求項第4項記載の放熱板付き複合
リードフレームの製造方法。
5. The method for manufacturing a composite lead frame with a heat sink according to claim 4, wherein the heat sink has dimple processing or through holes formed on a heat radiation surface, and has a thickness of at least 100 μm.
JP10495397A 1997-04-22 1997-04-22 Method for manufacturing composite lead frame with heat sink Pending JPH10303353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10495397A JPH10303353A (en) 1997-04-22 1997-04-22 Method for manufacturing composite lead frame with heat sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10495397A JPH10303353A (en) 1997-04-22 1997-04-22 Method for manufacturing composite lead frame with heat sink

Publications (1)

Publication Number Publication Date
JPH10303353A true JPH10303353A (en) 1998-11-13

Family

ID=14394468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10495397A Pending JPH10303353A (en) 1997-04-22 1997-04-22 Method for manufacturing composite lead frame with heat sink

Country Status (1)

Country Link
JP (1) JPH10303353A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7529093B2 (en) 2004-11-26 2009-05-05 Sanyo Electric Co., Ltd. Circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7529093B2 (en) 2004-11-26 2009-05-05 Sanyo Electric Co., Ltd. Circuit device

Similar Documents

Publication Publication Date Title
TWI316749B (en) Semiconductor package and fabrication method thereof
US5874784A (en) Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
JPH08148530A (en) Lead frame and manufacture thereof
JP7051508B2 (en) Semiconductor devices and methods for manufacturing semiconductor devices
US6583040B1 (en) Method of making a pillar in a laminated structure for a semiconductor chip assembly
JPH088293A (en) Structure for connecting electronic parts and connection method therefor
JP3513983B2 (en) Manufacturing method of chip carrier
JPH10303353A (en) Method for manufacturing composite lead frame with heat sink
JP2936540B2 (en) Circuit board, method of manufacturing the same, and method of manufacturing semiconductor package using the same
JP3337911B2 (en) Semiconductor device and manufacturing method thereof
JP3362636B2 (en) Method for manufacturing TAB tape carrier
JP2005072098A (en) Semiconductor device
JPH08102583A (en) Wiring circuit substrate
JPH11163197A (en) Semiconductor mounting board
JP3196758B2 (en) Lead frame, method of manufacturing lead frame, semiconductor device, and method of manufacturing semiconductor device
JPH09246416A (en) Semiconductor device
JP2669286B2 (en) Composite lead frame
JP3374296B2 (en) Manufacturing method of multilayer lead frame
JP3449097B2 (en) Semiconductor device
JPH11330301A (en) Semiconductor device and its mounting structure, resin wiring board and its manufacture
JPH0823067A (en) Lead frame
JPH0817998A (en) Lead frame
JPH09270443A (en) Method for mounting chips
JP3074667B2 (en) Chip carrier and manufacturing method thereof
JP2000082761A (en) Wiring board for bonding bump, manufacture thereof and semiconductor device assembled using it