JPH10293562A - Color liquid crystal display device and driving device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving device for a color liquid crystal display device having small scale circuit and low cost by making a spacial sampling position, for inputting a video signal to a memory, same as the spacial sampling position of a color liquid crystal panel. SOLUTION: Relating to a liquid crystal display device for non-interlace driving the video signals of a color liquid crystal panel 6, in which color pixels of RGB are arranged in delta and a different color pixel is connected to each vertical signal line, by using a memory 3; this display device comprises the driving device for the color liquid crystal display device for making a spacial sampling position, on which a video signal is inputted to the memory 3, a same as the spacial sampling position of the color liquid crystal panel 6 and the color liquid crystal panel 6. The inputted interlace signal is converted to a line sequential scanning signal by the line memory 3 after being decoded in a decoder 2 and the whole screen of the liquid crystal panel 6 is rewritten at the period of 60 Hz (NTSC) or 50 Hz (PAL).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color liquid crystal display for displaying non-interlaced video signals.

[0002]

2. Description of the Related Art Liquid crystal display devices are used not only for notebook personal computers but also for desktop personal computers. It is also used as a car navigation system, portable information tool, and home TV.

In this liquid crystal display device, non-interlaced driving of a panel having a large number of horizontal pixels (for example, 480 rows) uses a memory to perform writing for two rows in one horizontal scanning period. As a method, a memory is provided inside the panel, a video signal is serially input to the memory, output in parallel from the memory, and transferred to pixels of the panel.

[0004]

However, this serial-in / parallel-out method requires buffers for all signal lines in order to prevent the capacity division between each cell of the memory and the vertical signal line, thus increasing the circuit scale. And the associated cost rise.

It is an object of the present invention to provide a color liquid crystal display device which does not increase the circuit scale and a driving device for the same.

[0006]

Means for Solving the Problems In order to solve the above-mentioned problems, the present inventors have made intensive efforts and have obtained the following inventions. That is, the driving apparatus for a color liquid crystal display device according to the present invention is a non-interlaced driving method using a memory for a color liquid crystal panel in which RGB color pixels are arranged in a delta and video signals are connected to vertical signal lines to different color pixels. A spatial sampling position for inputting a video signal to the memory and a spatial sampling position of the color liquid crystal panel are equalized. Here, a sampling clock for outputting a video signal from the memory,
It is preferable that the sampling clocks of the color liquid crystal panels are equal. Further, it is preferable that two color pixels are connected to the same vertical signal line. Further, it is preferable that the video signal is inverted every two rows.

[0007] The present invention includes the invention of the color liquid crystal display device itself. That is, the color liquid crystal display of the present invention has
In a liquid crystal display device in which a color liquid crystal panel in which GB color pixels are arranged in a delta arrangement and a video signal is connected to a vertical signal line to a different color pixel by non-interlace driving using a memory, a video signal is input to the memory. The color liquid crystal display device includes a driving device for a color liquid crystal display device that makes the spatial sampling position equal to the spatial sampling position of the color liquid crystal panel, and a color liquid crystal panel.

[0008]

FIG. 1 shows a system configuration of a liquid crystal display device according to an embodiment of the present invention. 1 is an input terminal of a video signal such as a television signal, 2 is a decoder for converting to an RGB color signal, 3 is a line memory, and 4 is a signal which is sequentially switched to normal rotation inversion every predetermined period to be an AC signal for driving a liquid crystal. The inversion control and signal amplification unit 5 is a logic unit that forms pulses for memory control, inversion control, and liquid crystal panel driving. Reference numeral 6 denotes a liquid crystal panel, of which 7 is a horizontal shift register (HSR) as horizontal scanning means, and 8 is a vertical shift register (VS) as vertical scanning means.
R) and 9 are pixel portions. The interlace signal input to 1 is decoded by 2 and then converted into a line-sequential scanning signal by a 3 line memory.
Hz (NTSC) or 50 Hz (PAL) cycle, the entire screen is rewritten.

FIG. 2 shows a block diagram of the line memory unit. 31, 32, and 33 are input video signals of the memory unit;
Is a shift register (WSR) for writing to memory, 26
Is a start pulse (WST) for WSR, 27 is WSR
Reference numeral 18 denotes a memory read shift register (RSR), reference numeral 28 denotes a start pulse (RST) for RSR, and reference numeral 29 denotes a clock pulse for RSR.
Reference numerals 19, 20, and 21 are output lines for video signal data.

FIG. 3 shows a color arrangement of pixels. The pixels are arranged in a delta arrangement, and pixels of different colors are connected to the vertical signal line (15 in FIG. 4). In the even-numbered row and the odd-numbered row, the horizontal position of the pixel is 0.5 pixel, and the pixels of the same color are 1.5
Pixels are shifted.

FIG. 4 shows a circuit configuration of a display unit of the liquid crystal panel. Reference numeral 7 denotes a horizontal shift register (HSR), 8 denotes a vertical shift register (VSR), and 9 denotes a pixel portion. 10 is a thin film transistor, 11 is a liquid crystal, 12 is a storage capacitor, 13 is a counter electrode, 19, 20, and 21 are video signal input lines, which are connected to video signal data output lines 19, 20, and 21 in FIG. Reference numeral 15 denotes a vertical signal line, 16 denotes a gate line, and 17 denotes a signal line selection switch. 71 is an HSR start pulse (HST), 72 is an HSR clock pulse, 81 is V
An SR start pulse (VST), 82 is a VSR clock pulse.

FIG. 5 is a diagram showing operation timings of the line memory unit and the liquid crystal panel. SG1 is an input video signal (R, G, B) of the memory unit, and SG2 is a start of a shift register (WSR) for writing into the memory. Pulse, SG3 is WS
R clock pulse, SG4 is the start pulse of the memory read shift register (RSR), SG5 is the RSR
And HSR clock pulses. SG6 is a signal (ODD) indicating an odd row or an even row, SG7 is a video signal read from the memory, SG8 is an inversion control pulse of the video signal, and SG9 (R, G, B) is an AC video signal.
This becomes the input video signal of the liquid crystal panel.

In the present embodiment, a case of displaying on a liquid crystal panel having 600 and 480 horizontal pixels will be described with reference to FIG. The video signals 31, 32, and 33 that have been subjected to gamma correction suitable for liquid crystal display and intermediate amplification according to the dynamic range of the line memory in the preceding decoder unit are 2 × 600.
Are sampled by the stage shift register 4 and passed through the transistors 35, 36, 37,.
Is written to. Sampling is performed 1200 times in one horizontal period, which is twice the number of horizontal pixels of the liquid crystal panel.

Sampling is performed in accordance with the pixel arrangement of the liquid crystal panel, and Ro1, Be1, Bo1, Re1, Bo
1, Ge1... (Roi, Goi, Boi represent data corresponding to odd-numbered rows of the liquid crystal panel, and Rei, Gei, Bei represent data corresponding to even-numbered rows of the liquid crystal panel).

On the other hand, the reading of data from the line memory is performed by reading data Ro1 and Go for odd rows of the liquid crystal panel.
1, Bo1, Ro2, Go2, Bo2,.
Go200, Bo200 and data Re corresponding to even-numbered rows
1, Ge1, Be1, Re2, Ge2, Be2,... Re
200, Ge200, Be200
Both are transferred to the liquid crystal panel during the horizontal scanning period. Read from line memory and write to liquid crystal panel are R
oi, Goi, Boi, or Rei, Gei, Bei
Are performed simultaneously. That is, when transferring the data of the first row to the liquid crystal panel, the ODD signal 8 becomes “H”, and when the output of the first stage of the shift register 18 becomes “H”, the AND gate 10 becomes “H”. Therefore, the transistors 42, 43, and 44 become conductive, and the data Ro1, Go
1, Bo1 are simultaneously output to the output signal lines 19, 20, and 21.

Similarly, when transferring the data of the second row to the liquid crystal panel, the ODD signal 49 becomes "H", and if the output of the first stage of the shift register 18 is "H", the AND gate 11 is turned on. Since it becomes “H”, the transistors 45 and 4
6 and 47 become conductive, and data Be1, Re1, and Ge1 are simultaneously output to the output signal lines 19, 20, and 21.

Writing and reading to and from the line memory are performed as follows.
Perform in the following order. First, the shift register 4 starts operating in response to a start signal 26 of the write-side shift register 24, and performs sampling 1200 times within one horizontal scanning period, and sequentially writes the data in the line memory. (60
When the sampling of (0 + 6) is completed, the shift register 18 starts operating by the start signal 28 of the shift register 18 on the read side, and the line memories 1, 3, and
The data of the odd addresses are simultaneously read three by three in the order of addresses 5 (Ro1, Go1, Bo1), 7, 9, 11 (Ro2, Go2, Bo2). Assuming that the read clock cycle at this time is 1/3 of the write clock, (1)
200-6) Reading is performed up to the address, and no new data is written before reading from the line memory.

In this embodiment, it is desirable that the clock for outputting the video signal from the memory is equal to the sampling clock of the color liquid crystal panel. In this case, the RSR of the memory unit
The read from the memory and the write to the panel are performed simultaneously by making the clock of the HSR of the liquid crystal panel and the panel common, and the write to the first row of the liquid crystal panel is performed within t _H / 2 which is half of one horizontal scanning period t _H. To end. During the next t _H / 2 period, addresses 2, 4, and 6 (Be
1, Re1, Ge1), 8, 10, 12 (Be2,
Re2, Ge2)... Data of even addresses are simultaneously read out three by three in the order of Re2, Ge2). At this time, the video signal is sampled in the next horizontal scanning period, and data is written in the line memory. However, if reading is preceded by writing, the order of writing and reading will not be reversed.

When data is read out after the writing to the line memory is completed, a line memory for the video signal for two horizontal scanning periods is required. In the present embodiment, while the data is being written to the line memory. Then, by reading the video signal data from the same line memory, the line memory was halved.

The above timing is shown in FIG. The read data is converted into an AC signal by the inverting amplifier 4 in FIG. 1 and input to the liquid crystal panel 6. The inversion of the video signal for AC conversion is performed once every two rows by the SG8 signal in FIG. In this case, the color components included in the non-inverted video signal and the inverted video signal become equal, and the center value of the effective value of the two voltages becomes the center voltage of the AC component. By detecting this voltage and applying feedback so that the voltage always becomes a constant value, a DC component is prevented from being applied to the pixels of the liquid crystal panel.
The horizontal shift register 7 of the liquid crystal panel of the present invention is driven at the same number of stages and at the same timing as the shift register (18 in FIG. 2) of the line memory unit. The 480-stage vertical shift register 9 performs a shift operation prior to the read start signal of the line memory unit.

By repeating the above operation in the 240 horizontal scanning periods, video signal data can be written to 480 horizontal pixel columns of the liquid crystal panel in one field.

The horizontal pixel columns of the liquid crystal panel on which the video signal data for the same horizontal scanning period is written in the first field and the second field may be the same, or may be shifted by one row as shown in FIG. If the lines are shifted, the vertical resolution can be improved. FIG. 6 shows signals written on each row of 2k to 2 (k + 2) for each field on the liquid crystal panel.

Here, Ok and O'k are in the first field (odd field), and Ek and E'k
Is data obtained by sampling the video signal signal of the k-th horizontal scanning period of the interlace signal in the second field (even field) at different timings in accordance with the pixel arrangement of the odd and even rows of the liquid crystal panel. In this case, in the second field, the start timing of the vertical shift register is set to t _H /
2 and the read order of the line memory is changed from even data (Be1, Re1, Ge1,...).

In the present embodiment, the image signal is held in the form of an analog signal using a capacitor as a holding means (the memory unit 3 in FIG. 1). This part is an A / D converter, a digital line memory, It may be constituted by a D / A converter.

[0025]

According to the present invention, the circuit scale of the driving device of the color liquid crystal display device does not increase. Therefore, a low-cost color liquid crystal display device can be provided.

[Brief description of the drawings]

FIG. 1 is a system configuration of a liquid crystal display device according to the present invention.

FIG. 2 is a circuit configuration of a line memory unit according to the present invention.

FIG. 3 is a color arrangement of pixels in the present invention.

FIG. 4 is a circuit configuration of a display unit of the liquid crystal panel according to the present invention.

FIG. 5 is a timing chart of driving liquid crystal and memory during a horizontal scanning period according to the present invention.

FIG. 6 is a diagram showing signals written to each row of the liquid crystal panel for each field in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal input terminal 2 Decoder 3 Line memory 4 Signal amplification part 5 Logic part 6 Liquid crystal panel 7 Horizontal shift register 8 Vertical shift register 9 Pixel part

Claims (5)

[Claims] 1. A driving apparatus for non-interlace driving a color liquid crystal panel in which RGB color pixels are arranged in a delta arrangement and a video signal to which different color pixels are connected to a vertical signal line by using a memory, wherein the video signal is A driving apparatus for a color liquid crystal display device, wherein a spatial sampling position input to a memory is made equal to a spatial sampling position of the color liquid crystal panel. 2. The driving device according to claim 1, wherein a sampling clock for outputting a video signal from the memory is equal to a sampling clock for the color liquid crystal panel. 3. The driving device according to claim 1, wherein two color pixels are connected to the same vertical signal line. 4. The driving device according to claim 1, wherein the video signal is inverted every two rows. 5. A color liquid crystal display device comprising: the driving device according to claim 1; and a color liquid crystal panel.