JP2001324970A - Picture display device, picture display method and display driving device and electronic equipment using the display driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display device displaying a picture having no ghost by sampling stable picture data during a sampling period. SOLUTION: This picture display device has a picture display part 110 which is constituted by arranging pixels at pixel positions formed by intersections of plural data signal lines 112 and plural scanning lines 110 which are arranged in a matrix shape. A scanning signal line selecting circuit 102 successively supplies a scanning signal to the scanning lines 110. A phase developing circuit 32 samples a picture signal having data corresponding to respective pixel positions time sequentially and outputs plural phase developing signals which are converted into data lengths longer than the sampling period in parallel. Plural sampling circuits 106 connected respectively to respective data signal lines 112 make respectively one of the plural phase developing signals an input and sample pixel data in the phase developing signals to supply data signals to the data signal lines 112. A sampling signal generating circuit 104 generates sampling signals whose sampling periods are shorter than a period corresponding to the data length of the phase developing signal to supply them to the sampling circuits 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device such as an active matrix liquid crystal display device, an image display method, a display drive device, and an electronic apparatus using the same. More specifically, the present invention relates to an improvement in a data write operation capable of reducing a ghost phenomenon.

[0002]

BACKGROUND ART Problems to be solved by the invention
In an active matrix type liquid crystal display device, a plurality of TFTs (thin film transistors) connected to one scanning signal line
The operation of writing data to the liquid crystal layer of each pixel via a switching element such as described above is performed by dot sequential driving.

In order to respond to recent demands for multimedia, for example, a personal computer (P
C) or engineering workstation (E
In WS), when displaying a natural image such as a video signal, it is desired to cope with a multi-gradation such as 256 gradations.

[0004] If the conventional digital driver is used to cope with the multi-gradation, the number of input signals must be increased by the number of bits. For example, in the case of a 256-gradation color display, three (R, G, B) × 8 bits = 2
The number of input signals is four.

On the other hand, in the case of an analog driver, only three input signals are required for color display, and one input signal is required for monochrome display. Furthermore, while the digital driver has discrete gradation characteristics, the analog driver has continuous gradation characteristics, which is advantageous for display based on a normal video signal.

In the active matrix type liquid crystal display device, it is necessary to sample and hold data in an image signal using a TFT switch or the like for the above-described dot sequential driving. At this time, there arises a problem that the switching characteristics of the TFT or the like cannot sufficiently follow the frequency of the input image signal. In the case of a display device with a built-in driver, compared to a display device with an external driver,
The capability of the sample hold TFT is low, and the problem becomes more pronounced. Further, in the case of a high-definition display device having a large number of pixels, the frequency of the input image signal increases, so that the above problem becomes more remarkable.

For this reason, as shown in FIG. 32, the input image signal is expanded into, for example, six parallel signals, the data length per pixel is lengthened, and the signal frequency input to the liquid crystal panel is lowered. Has been proposed (Japanese Patent Application No.
No. 316988).

[0008] By this phase development, for example, even if the frequency characteristics of a TFT as a sample-and-hold switch are not sufficient, the data length per pixel can be increased and the resolution can be increased.

As shown in FIG. 32, the data length of each phase-expanded signal that is expanded in six phases and output in parallel is the length of six cycles of the reference clock.

When this is sampled by a sample and hold switch such as a TFT, for example, the sampling period of a sampling signal input to the gate of the TFT is
At first, as shown in FIG. 32, an attempt was made to set the length to eight periods of the reference clock.

This is because a sufficient sampling period is set for the data length in the phase expansion signal in consideration of the switching followability of the TFT. Also, a sampling signal having this sampling period can be easily generated by using only the shift register.

However, according to the experiment of the present inventor,
As schematically shown in FIG. 33, for example, when an arrow 1 is displayed on the screen 2, it has been found that a ghost 3 indicated by a broken line may occur at a stage subsequent to the arrow 1 in the scanning direction.

It is an object of the present invention to provide an image display device, an image display method, a display drive device, and an electronic apparatus using the same, which can reduce or prevent ghosting while expanding an input image signal. Is to do.

Another object of the present invention is to provide an image display device, an image display method and an image display method capable of performing display driving while reducing or preventing ghost even when dot-sequential driving cannot follow a sample-hold operation with the increase in dot clock speed. An object of the present invention is to provide a driving device and an electronic device using the driving device.

[0015]

According to the present invention, there is provided an image display device, comprising: a plurality of data signal lines and a plurality of scanning signal lines arranged in a matrix;
It has an image display section in which pixels are arranged. The scanning signal line selecting means sequentially supplies scanning signals to the scanning signal lines.
The phase expansion means samples an image signal having data corresponding to each of the pixel positions in a time series, and outputs a plurality of phase expansion signals converted to a data length longer than the sampling period in parallel. A plurality of sampling means respectively connected to each of the data signal lines receives one of the plurality of phase expansion signals as an input, samples the data in the phase expansion signal, and outputs the data to the data signal line. Supply as a signal. The sampling signal generating means generates a sampling signal for a sampling period shorter than a period corresponding to the data length of the phase expansion signal, and supplies the generated sampling signal to the sampling means.

The present invention functions as follows in order to reduce or prevent ghost, which is an object of the present invention.

First, the present inventor has analyzed that the generation of the ghost is caused by the inclusion of unnecessary components in the waveform supplied to the pixel via the sampling means as shown in FIG. As shown in FIG. 32, mixing of unnecessary components in the waveform is such that the data length of the phase development signal is six periods of the dot clock, while the sampling period is eight periods of the dot clock. It is due to

For this reason, in FIG. 32, for example, taking the signal line of video n as an example, the sampling signals S / H (n),
Since S / H (n + 6) and S / H (n + 12) are sampled while each having an overlap period,
For example, at the beginning of the sampling period of S / H (n + 6), S / H (n) also
The sampling signal of S / H (n + 6) was sampling.

The phenomenon in this case was observed by observing the potential waveform supplied to the liquid crystal layer. As a result, depending on the writing capability of the sampling means, as shown in FIG. 34, the influence of the data once written by the arrow 1 being mixed, unnecessary components are mixed in the waveform, and the level of the level that should be lowered is obtained. It was found that the level became higher at a position corresponding to the ghost 3 in FIG.

In the present invention, as symbolically shown in FIGS. 8, 11, 14 and 17, the sampling period of the sampling signal can be always set shorter than the data length of the phase expansion signal. Ghosts can be reduced or prevented.

In the present invention, the phase expansion means can sequentially shift the head position of the pixel data of each of the phase expansion signals based on a reference clock and output each of the phase expansion signals in parallel. At this time, the sampling signal generation means sets the start timing of the sampling period of the sampling signal output to each of the sampling means so as to be sequentially shifted. This makes it possible to drive the pixels connected to one scanning signal in a dot-sequential manner.

This sampling signal generating means has a shift register and an AND circuit.

The shift register has a plurality of stages for sequentially shifting an input signal, and the output signal of each stage is output at a timing where the output signal of the next stage partially overlaps the phase. More specifically, the shift register sequentially shifts and transmits an input signal having a pulse width of 2N (N is a natural number) times one cycle of the reference clock by one cycle of the reference clock. In the example of FIG. 7A, N = 4 and the pulse width of the input signal DX is eight times one cycle of the dot clock DC. In the example of FIG. 10, N = 3, and the pulse width of the input signal DX is six times one cycle of the dot clock DC. In the example of FIG. 13, N = 2, and the pulse width of the input signal DX is four times one cycle of the dot clock DC.

Further, the AND circuit connected to each of the sampling means is supplied with two outputs having different shift amounts from the shift register, and outputs the logical product as the sampling signal to the sampling means. ing.

Thus, the AND circuit connected to the n-th (1.ltoreq.n.ltoreq.the total number of pixels on one scanning signal line) sampling means has the n-th and (n) in one horizontal period.
The (N) th shift register output is input, and the sampling period of the sampling signal that is the logical product thereof is N times one cycle of the reference clock.

In FIG. 6 showing an embodiment in which N = 4, for example, n
If = 1, the outputs of the first and fifth shift registers are input to the AND circuit 160a, and the sampling period is 4 (= N) times one cycle of the dot clock DC as shown in FIG.

In FIG. 9 showing an embodiment in which N = 3, for example, n
If = 1, the outputs of the first and fourth shift registers are input to the AND circuit 160a, and the sampling period is 3 (= N) of one cycle of the dot clock DC as shown in FIG.
It is twice.

In FIG. 12, which is an embodiment of N = 2, if n = 1, for example, the outputs of the first and third shift registers are input to the AND circuit 160a, and as shown in FIG. One cycle of DC 2 (=
N) times.

In the present invention, the phase expansion means can output each of the phase expansion signals in parallel by matching the head of the pixel data. At this time, the sampling signal generation unit transmits the sampling signal whose start time of the sampling period is matched to a plurality of the sampling units connected to the same number of the data signal lines as the total number of the phase expansion signal lines. Supplying. As a result, FIG.
As symbolically shown in FIG. 7, a plurality of the pixels connected to one scanning signal can be simultaneously driven by the total number of the phase development signal lines.

The sampling signal generating means has a shift register for sequentially shifting the input signal by one period of the reference clock and transmitting the shifted signal. More specifically, the shift register sequentially shifts and transmits an input signal having a pulse width of 2N (N is a natural number) times one cycle of the reference clock, one cycle of the reference clock.

In the example of FIG. 16, when N = 4, the input signal DX
Is eight times as large as one period of the dot clock DC.

In this way, at the time of the m-th (1 ≦ m ≦ the total number of pixels on one scanning signal line / the total number of the phase development signal lines) th simultaneous driving, the (3m−2) -th (3m−2) th in one horizontal period The shift register output is input to the plurality of sampling units, and the sampling period of the sampling unit is N times one cycle of the reference clock.

In the example of FIG. 15, for example, in the case of m = 1st simultaneous driving, 3m−2 = 1st shift register output is:
The signals are input to six sampling units 106. Similarly, in the case of m = second simultaneous driving, 3m−2 = fourth shift register output is output from the next six sampling units 10
6 and for m = third simultaneous drive, 3m−2 =
The output of the seventh shift register is input to the next six sampling means 106.

According to the present invention, the image display section is a liquid crystal panel in which liquid crystal is interposed between a pair of substrates, and the plurality of sampling means include a plurality of thin film transistors (TFTs) formed on one of the substrates. Wherein the sampling signal from the sampling signal generating means is supplied to the gate of each of the thin film transistors.

Although a TFT has a limited writing capability, a sufficient sampling period can be secured by inputting a phase development signal having pixel data having a long data length, and the previous pixel data is written during the sampling period. Since there is no occurrence, unnecessary components are reduced from being mixed in the waveform, and generation of ghost can be effectively prevented.

In the present invention, the image display unit may calculate a difference voltage between a voltage applied to one end of the pixel via the data signal line and a voltage applied to the other end of the pixel by using a liquid crystal at the pixel position. And driving the liquid crystal by inverting the polarity of the electric field applied to the liquid crystal.

In this case, a first polarity image signal for driving the pixel with a first polarity with respect to a polarity reversal reference potential from the input image signal before the phase expansion means; And a second polarity image signal for driving the pixel with a second polarity having a polarity opposite to that of the second polarity image signal, and outputting one of the first and second polarity signals to the phase developing means. Further, it can be provided. At this time, the phase developing means outputs first and second polarity phase developing signals based on the first and second polarity image signals.

Further, the polarity inverting means includes the first,
A first polarity inverting means for outputting one of the second polarity image signals, and a second polarity inversion means for outputting the other of the first and second polarity image signals
And a polarity inversion means.

In the present invention, a plurality of polarity reversing means may be provided at a stage subsequent to the phase developing means. In this case, the plurality of polarity inversion means may include, based on one of the plurality of phase development signals, a first polarity phase development signal for driving the pixel with a first polarity with respect to a polarity inversion reference potential; And a second polarity phase development signal for driving the pixel with a second polarity opposite to the polarity of the first and second polarity phase development signals. Output to

Each of these polarity inversion means is provided by the first,
It can have a first polarity inversion unit that outputs one of the second polarity phase expansion signals, and a second polarity inversion unit that outputs the other of the first and second polarity phase expansion signals.

In the present invention, switching means for switching the plurality of phase development signals (or first and second polarity phase development signals) and supplying the signals to the plurality of sampling means, and changing the development order in the phase development means Control means for controlling and changing the supply destination of the plurality of phase development signals (or first and second polarity phase development signals) by the switching means in accordance with the deployment order. Can be.

In this way, it is possible to prevent a variation in, for example, a DC offset component generated for each phase development signal from being emphasized by a vertical line on the screen.

According to the present invention, the display driving device for driving the image display unit can be an external circuit for the image display unit.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an active matrix type liquid crystal display device will be specifically described below with reference to the drawings.

(1) First Embodiment (Schematic Configuration of Device) FIG. 1 shows an overall outline of a liquid crystal display device according to a first embodiment. As shown in FIG. 1, the liquid crystal display device is a small liquid crystal display device used as a light valve of an electronic device, for example, a liquid crystal projector, and includes a liquid crystal panel block 10 and a timing circuit block 20.
And a data processing block 30.

The timing circuit block 20 receives the clock signal CLK and the synchronization signal SYNC and outputs a predetermined timing signal.

The data processing circuit block 30 has a phase expansion circuit 32 and an amplification / inversion circuit 34. Phase expansion circuit 3
Reference numeral 2 denotes a single image signal (in this embodiment, black and white grayscale display, and one image signal) Data is input, and pixel information is expanded into n phases (in FIG. 1, n = 6 phases). The n-phase expansion signals are output in parallel. In addition,
When the liquid crystal panel 100 in the liquid crystal panel block 10 is a color liquid crystal panel having color filters of three primary colors, three image signals of R, G, and B are input to the phase development circuit 32. For example, six phase development signals can be generated from the book image signals. This n-phase expansion will be described later.

The amplifying / inverting circuit 34 amplifies the n phase expansion signals to a voltage necessary for driving the liquid crystal panel and, if necessary, inverts the polarity with reference to the polarity inversion reference potential. The positions of the amplification / inversion circuit 34 and the phase expansion circuit 32 shown in FIG. 1 may be reversed. That is, after the image signal is amplified and inverted in polarity by the amplification / inversion circuit 34, the phase expansion circuit 32 may expand the phase.

Since the output lines of the data processing circuit block 30 of the present embodiment are implemented with six-phase expansion, FIG.
As shown in the figure, the data is branched into six, Data1 to Data6.

The liquid crystal panel block 10 includes the liquid crystal panel 1
00, the scanning side driving circuit 102, and the data side driving circuit 1
04 is provided on the same circuit board. These drive circuits are separated from the liquid crystal panel substrate and external IC
It may be constituted as.

On the liquid crystal panel 100, for example, a plurality of scanning signal lines 110 extending in the row direction of FIG. 1 and a plurality of data signal lines 11 extending in the column direction, for example.
2 are formed. In this embodiment, the total number of the scanning signal lines 110 is 492, and the total number of the data signal lines 112 is 652. Each line 11
At a pixel position formed by the intersection of 0 and 112, the switching element 114 and the liquid crystal layer 116 are connected in series to form a display element, which forms a pixel.
A period during which the switching element 114 is turned on is referred to as a selection period, and a period during which the switching element 114 is turned off is referred to as a non-selection period. A storage capacitor (not shown) that holds the voltage supplied to the liquid crystal layer 116 via the switching element 114 during the selection period during the non-selection period is connected to the liquid crystal layer 116. In this embodiment, the switching element 114 is, for example, a three-terminal switching element, and is configured by, for example, a TFT. The present invention is not limited to this, and two-terminal switching elements such as M
An IM (metal-insulating layer-metal) element, a MIS (metal-insulating layer-semiconductor layer) element, or the like can be used. In addition,
The liquid crystal panel 100 of the present embodiment is not limited to an active matrix type liquid crystal display panel using two-terminal or three-terminal switching, but may be various other liquid crystal panels such as a simple matrix type liquid crystal display panel. Is also good. The liquid crystal panel 100 of this embodiment has a first substrate on which a scanning signal line 110, a data signal line 112, and a TFT connected to the scanning signal line 110 and the data signal line 112 are formed. The first substrate is further provided with a pixel electrode connected to the TFT and a storage capacitor having the pixel electrode as one side electrode. The liquid crystal panel 100 further has a second substrate disposed opposite to the first substrate and having a common electrode formed thereon. And the first,
Liquid crystal is sealed between the second substrates to form the liquid crystal panel 100. One end of the liquid crystal layer at each pixel position is a pixel electrode,
An electric field is applied by the bipolar electrodes with the other end as a common electrode.

The scanning-side driving circuit 102 outputs a scanning signal in which a selection period for sequentially selecting the scanning signal lines 110 from the plurality of scanning signal lines 110a, 110b,... Is set.

The data side driving circuit 104 is arranged between six phase development signal lines Data1 to Data6, which are output lines of the data processing circuit block 30, and the data signal lines 112a, 112b... Of the liquid crystal panel 100. The liquid crystal panel 1
This is to output a sampling signal for driving 00 in a dot sequential manner.

The first phase expansion signal line Data1
Is the first through the sample and hold switch 106a.
Is connected to the data signal line 112a. Similarly, the second to sixth phase expansion signal lines Data2 to Dat
a6 represents each of the sample and hold switches 106b to 106b.
06f, the second to sixth data signal lines 112
b to 112f. Further, the first phase expansion signal line Data1 is connected to the seventh data signal line 112 via the sample hold switch 106g.
g. Similarly, the first phase expansion signal line Data1 is connected to the data signal line 1 six lines ahead.
12 is connected. Similarly, the second to sixth phase expansion signal lines Data2 to Data6 are sequentially connected to respective data signal lines that are an integral multiple of 6 from the second to sixth data signal lines 112b to 112f.

(Operation of N-Phase Expansion) Next, with reference to FIG. 2, an operation of n-phase expansion, for example, six-phase expansion, in the phase expansion circuit 32 in the data processing circuit block 30 will be described.

As shown in FIG. 2, the image signal input to the data processing circuit block 30 is an analog signal having data corresponding to each pixel of the liquid crystal panel 100 in time series. The phase expansion circuit 32 that performs six-phase expansion includes:
This image signal is used as a reference clock, for example, a dot clock DC.
Sampling at Then, the image signal is sampled to generate six phase expansion signals converted into a data length longer than the sampling period. In the present embodiment, the data length is expanded to an integral multiple of one cycle of the dot clock DC, and is expanded into six parallel phase expansion signals. In this sense, the phase expansion circuit 32 has a function of extending the data length and a function of performing serial-parallel conversion from a serial image signal to a parallel image signal. For example, the first phase expansion signal output to the first phase expansion signal line Data1 is such that the data of the first, seventh, and thirteenth pixels of the image signal is, for example, six times one cycle of the dot clock DC Data length. Similarly, 6
The data at the pixel destination is sequentially expanded to the data length.

Similarly, the second phase expansion signal output to the second phase expansion signal line Data2 is the second, eighth, and fourteenth signal.
The data of the pixels and the like are expanded to the data length and output.

In this embodiment, this expansion and expansion operation is
This is performed using an analog interface IC, and analog image signals are developed in six phases.

Note that in the first embodiment, the first to sixth
The first to sixth phase development signals output to the phase development signal lines Data1 to Data6 are output in a state where the head positions of the respective pixel data are sequentially shifted by one cycle of the dot clock DC.

(Explanation of Specific Examples of Six-Phase Expansion Circuit and Polarity Inverting Circuit) FIGS. 3 and 4A and 4B show specific examples of the six-phase expanding circuit and the polarity inverting circuit. In FIG. 3, the phase expansion circuit 32 includes switches 500a to 500f.
, Capacitors 502a to 502f, and buffer 504
a to 504f. And the switch 500
For example, sampling clocks SCLK1 to SCLK6 whose phases are shifted as shown in FIG. Each switch 500
a to 500f, when turned on by the clock,
The data is sampled, and the capacitor 50 in the subsequent stage is sampled.
2a to 502f are charged with data charges. Each of the switches 500a to 500f holds the data potential while being turned off by the clock. This allows
As shown in FIG. 5, a six-phase expanded signal is obtained via buffers 504a to 504f.

At the subsequent stage of each of the buffers 504a to 504f, amplification circuits 506a to 506f and a polarity inversion circuit 50 are provided.
8a to 508f are provided. FIGS. 4A and 4B show an example of the amplifier circuit and the polarity inversion circuit.

As shown in FIG. 4A, the amplifier circuit is composed of, for example, a video amplifier (or an operational amplifier) 510. The polarity inversion circuit includes the resistors R1 and R2 and the first
A polarity inversion unit 520 including a transistor TR1,
A buffer 530 including a resistor R3 and a second transistor TR2, a buffer 540 including a resistor R4 and a third transistor TR3, and buffers 530 and 540.
And a switch SW1 for selecting one of the outputs.

For convenience of explanation, a case where the output of the video amplifier 510 is a rectangular wave as shown in FIG. Here, the resistance values of the resistors R1 and R2 in FIG. 4A are substantially equal, and Vdd is 12V. In this case, FIG.
Each potential at point A and point B in (A) is, for example, as shown in FIG. 4A, a potential substantially line-symmetric with an intermediate potential, for example, 6 V. The potential of the point A is, for example, 11 V for the black level and 7 V for the white level, and the potential of the point B is, for example, 1 for the black level.
V and the white level are 5V. Thus, points A and B
Are inverted in polarity with reference to the polarity inversion reference potential between the black levels of both signals. In this embodiment, the signal appearing at the point B is a negative image signal,
The signal appearing at the point A is defined as a positive image signal. The reference potential for the polarity inversion is the center potential of the power supply potential Vdd and the ground potential GND, that is, the amplitude center potential Vref of the analog image signal.

The signal of the negative polarity appearing at the point B is
The signal of the positive polarity, which is output to the terminal C via the terminal 40 and appears at the point A, appears at the terminal D via the buffer 530. One of these positive and negative phase development signals is selected and output by a switch SW1 that is switched based on a polarity inversion timing signal.

FIG. 4B is a circuit diagram showing the amplifier circuit 506 shown in FIG.
5A to 506f and other examples of the polarity inversion circuits 508a to 508f. In FIG. 4B, the amplifier circuit 510,
Differential amplifier circuits 550 and 560 are provided. Amplifier circuit 5
The level of the image signal input to the differential amplifier circuit 550 via 10 is set to a potential having a positive polarity with respect to the above-described amplitude center potential Vref, and is output from the differential amplifier circuit 550 to the terminal C. Similarly, the level of the image signal input to the differential amplifier circuit 560 via the amplifier circuit 510 is set to a potential having a negative polarity with respect to the above-described amplitude center potential Vref. Is output. Each terminal C, D
Is selectively output by switching the switch SW1 based on the polarity inversion timing signal.

In the example shown in FIG. 3, since amplification and polarity inversion are performed after the phase expansion, the amplification circuits 506 of six systems are used.
a to 506f, and six polarity inversion circuits 508a to 508
8f is required. However, since the charge of the signal can be charged to the capacitors 502a to 502f at the stage where the signal amplitude before the signal amplification is small, there is an advantage that the charging time is short and the speed can be increased.

(Regarding Configuration of Data Sampling) Next, the data side driving circuit 10 which is a characteristic configuration of this embodiment is described.
4 will be described with reference to the circuit diagram of FIG. 6 and the timing chart of FIG.

As shown in FIG. 6, the data-side driving circuit 104 includes shift registers 120 to 15 in the first to fourth columns.
It has 0. These shift registers 120 to 15
0 inputs the input signal DX which is the common shift data shown in FIG. This input signal DX is shown in FIG.
As shown in FIG. 7, the signal is HIGH over eight periods of the dot clock signal DC. The first clock signal CLX1 shown in FIG. 6 and its first inverted clock signal are input to the shift register 120 in the first column.
As shown in FIG. 7A, the first clock signal CLX1 is a pulse having a half pulse width of the input signal DX and the input signal DX.
It is repeatedly output at a cycle of the pulse width of X. Similarly, the shift registers 130 to 150 in the second to fourth columns include:
The second to fourth clock signals CLX2 to CLX4 and their inverted clock signals are input. The rising timing of the second to fourth clock signals CLX2 to CLX4 is sequentially shifted from the rising timing of the first clock signal CLX1 for each period of the dot clock DC.

The shift registers 120 to 150 in each column are
Each is configured to include a multi-stage master-slave type clocked inverter. First shift register 12
0, the first clocked inverter 121a serving as a master and the inverter 121b
Are directly connected, and a second clocked inverter 121c serving as a slave is connected to a feedback line connecting the input / output line of the inverter 121b. The clocked inverter 121a serving as a master receives the first clock signal CL
When X1 is HIGH, the input clock signal DX is inverted and output. Similarly, the second clocked inverter 121c serving as a slave also receives the first inverted clock signal / CL
When X1 is HIGH, the output signal of the inverter 121b is inverted and output.

The operation of the first-stage shift register 120 in the first column will be described with reference to the timing chart of FIG. For reference, various signal waveforms output by the scanning side driving circuit 102 are shown in FIG.
It was shown to.

In the first half (four periods of the dot clock DC) when the input clock signal DX becomes HIGH,
The first clock signal CLX1 becomes HIGH, and the input signal D as an output of the first clocked inverter 121a.
LOW is output with X inverted. This LOW signal is
The output of the first-stage shift register 120 is inverted as shown in FIG.
As shown by R1-OUT1, HIGH is output only in the first half of the input clock signal DX.

In the latter half of the input clock signal DX, while the clock signal CLX1 becomes LOW,
The first inverted clock signal / CLX1 input to the slave second clocked inverter 121c becomes HIGH. The signal input to the second clocked inverter 121c is a HIGH signal from the inverter 121b, and as a result, the second clocked inverter 121c
The output from LOW is the LOW that is obtained by inverting the input HIGH signal.
Signal. This LOW signal is inverted by the inverter 121b. Therefore, shift register 1 in the first column
20, a first output signal SR which is the output of the first stage
The HIGH signal is output also in the latter half of 1-OUT1.

The seventh (A) SR1-OUT1,...
SR4-OUT1,... SR3-OUT2 are first to fourth
4 shows the outputs of column shift registers 120-150. Reference numerals SR1 to SR4 indicate the first to fourth columns of the shift register, and reference numerals OUT1, OUT2,... Indicate outputs of the first stage, the second stage,.

The second and third output signals SR2-OUT1-
SR4-OUT1 is driven by the operation of the first stage of the shift registers 130 to 150 in the second to fourth columns, as shown in FIG.
As shown in (1), the first output signal SR1-OUT1 is output in a state of being sequentially shifted by one period of the dot clock DC from the rise of the first output signal SR1-OUT1.

The fifth output signal SR1-OUT2 is
It is generated using the master-slave type clocked inverter of the second stage of the shift register 120 in the first column.

The shift registers 12 in the first to fourth columns
If the output signals of 0 to 150 are output to the sample and hold switches 106a, 106b,... As they are, the conventional ghost phenomenon described with reference to FIGS.

Therefore, in the first embodiment, the first
The NAND circuits 160a, 160b,... And the inverter 162 are provided between the shift registers 120 to 150 in the first to fourth columns and the sample and hold switches 106a, 106b.
a, 162b ... are provided. The NAND circuit and the inverter function as a circuit that calculates the logical product of two timing signals output from the shift register.

The NAND circuit 160a provided before the sample and hold switch 106a connected to the first data signal line 112a has a first output signal SR1-from the first stage of the shift register 120 in the first column. OUT
1 and the fifth output signal SR1-OOT2 from the second stage
Is input. Therefore, the sampling signal SL1-Data1 obtained via the NAND circuit 160a and the subsequent inverter 162a is the first output signal S1.
The logical product of R1-OUT1 and the fifth output signal SR1-OUT2 is obtained, and as shown in FIG. 7A, a period of four periods of the dot clock DC is set as a sampling period.

SL1-Data1,... SL in FIG.
4-Data4,...
6a,... 106d,.
When the level is at the high level, the TFT is turned on. When the signal is represented by SL (n) -Data (m), m (m = 1 to 6) of the code Data (m) indicates the number of the phase development signal lines Data1 to 6 sampled by the signal. . The symbol n in the symbol SL (n) indicates the order of the sampling signal.

In a stage preceding the sample-and-hold switch 106b connected to the second data signal line 112b, the NAND circuit 160b is connected to the shift register 1 in the second column.
The signal SR2-OUT1 from the first stage and the signal SR2-OUT2 from the second stage are input. Therefore, the second sampling signal SL2-Data2 obtained via the NAND circuit 160b and the subsequent inverter 162b rises by one period of the dot clock DC more than the first sampling signal SL1-Data1. Although delayed, the sampling period is also a period of four periods of the dot clock DC. Note that the same applies to data signal lines after the third data signal line.

(Data Sampling Operation) FIG.
Shows the relationship between the phase expansion signals Data1 to Data6 input to the respective sample and hold switches 106 and the sampling signals SL (n) to Data (m). In FIG. 8, the sampling signals SL1-Data1, SL7-Da for sampling the phase expansion signal Data1 are shown.
ta1 and SL13-Data1 are shown. As shown in FIG. 8, information having a data length of six periods of the dot clock DC is input to the first sample hold switch 106a to the source line of the TFT constituting the sample hold switch 106a. On the other hand, the sampling signal SL1-Data1 that has passed through the NAND circuit 160a and the inverter 162a is input to the gate of the TFT included in the sample hold switch 106a. The sampling signal Sl-Data1 has a data length of the phase expansion signal of six periods of the dot clock signal, and a sampling period (High period) of four periods in which one period is removed before and after the period. Is set to

By setting such a sampling period, even if the sample hold switch 106 is
Even if the writing capability of this TFT is limited, it is not affected by the previous data on the liquid crystal display.
In other words, a ghost-free liquid crystal display can be performed.

The reason is that the sample hold switch 1
After the image data on the phase development signal line is stabilized, the gate of the TFT forming the sampling signal High
Because it will be opened by the level. Moreover,
Before the data on this phase expansion signal line changes, TF
This is because the gate of T is closed. Further, the sample and hold switches 106a, 106g, 106n,... Connected to the same phase development signal line Data1 are SL1-Da.
As is apparent from the shift in the High level periods of ta1, SL7-Data1, and SL13-Data1, the gates are driven with the opening and closing timings shifted, and a plurality of gates are not opened simultaneously. As described above, by setting the sampling period only for the stable data area in the data length of the phase expansion signal, only the stable data which is not affected by the previous data is transferred to the data signal line 11.
2 can be sent. This data is written to the liquid crystal layer 116 and the storage capacitor via the switching element 114 that is turned on by a scanning signal from the scanning side driving circuit 102.

Similarly, the stable data is sequentially sent to the corresponding data signal lines 112b, 112c,... Via the sampling switches 106b, 106c, and so on, and the switching element 114 is sent to the first scanning signal line 110a. Is written to the liquid crystal layer 116 connected via the dot sequential driving. Thereafter, the above-described data writing is repeatedly performed while the switching elements 114 connected to the second and subsequent scanning signal lines 110 are sequentially turned on by the scanning signal from the scanning side driving circuit 102.

(2) Second Embodiment This second embodiment uses a phase expansion signal having a data length of six dot clock cycles and a sampling signal having a sampling period of three dot clock cycles. , For driving a liquid crystal display.

The difference from the first embodiment is that the data side drive circuit and the like shown in FIG. 6 are changed to those shown in FIG.

As shown in FIG. 9, the data side driving circuit 104
Has shift registers 200 to 220 in the first to third columns. These shift registers 200 to 220 are
As shown in FIG. 10, an input signal D serving as common shift data
Enter X. As shown in FIG. 10, this input signal DX is HIGH for six periods of the dot clock signal DC.
The signal is as follows. The first column of the shift register 200 has the first clock signal CLK1 shown in FIG.
And its first inverted clock signal / CKL1 are input. As shown in FIG. 10, the first clock signal CLK1 is a pulse having a half pulse width of the input signal DX,
It is repeatedly output at a cycle of the pulse width of X. Similarly, the second and third clock signals CLK2 and CLK3 and their inverted clock signals / CLK2 and / CLK3 are input to the second and third column shift registers 210 and 220, respectively. Second and third clock signals CLK2, CLK3
Has a rising time of the first clock signal CLK.
This is sequentially shifted from the rising timing of 1 for each cycle of the dot clock DC.

The shift registers 200 to 220 in each column are
Each is configured to include a multi-stage master-slave type clocked inverter.

The shift registers 20 in the first to third columns
0-220 output signals SR1-OUT1,... SR3-O
UT2 is as shown in FIG.

The NAND circuit 160a provided before the sample-and-hold switch 106a connected to the first data signal line 112a has a first output signal SR1-from the first stage of the shift register 200 in the first column. OUT
1 and the fourth output signal SR1-OUT2 from the second stage
Is input. Therefore, the sampling signal SL1-Data1 obtained via the NAND circuit 160a and the subsequent inverter 162a is the first output signal S1.
The logical product of R1-OUT1 and the fourth output signal SR4-OUT2 is obtained. As shown in FIG. 10, a High period of three periods of the dot clock DC is set as a sampling period.

Similarly, the second data signal line 112b
Is connected to the NAND circuit 160b, the signal SR2-OUT1 from the first stage of the shift register 210 in the second column is supplied to the NAND circuit 160b.
And a signal SR2-OUT2 from the second stage. Therefore, the second sampling signal SL2-Data2 obtained via the NAND circuit 160b and the inverter 162b at the subsequent stage has a dot clock D higher than the first sampling signal SL1-Data1.
Although the rise is delayed by one cycle of C, the sampling period is also a High period of three periods of the dot clock DC. Note that the same applies to data signal lines after the third data signal line.

Note that the seventh sampling signal SL7-Data1 in FIG.
Phase expansion signal line Data1 identical to L1-Data1
Is a signal for sampling. As is clear from FIG. 10, both sampling periods are set to be shifted.

(Regarding Data Sampling Operation) FIG.
Reference numeral 1 denotes a relationship between the phase expansion signals Data1 to Data6 input to the respective sampling switches 102 and the sampling signals SL (n) -Data (m).
FIG. 11 shows a waveform similar to FIG. For example,
The first sample and hold switch 106a has the configuration shown in FIG.
As shown in FIG. 7, information having a data length of six periods of the dot clock DC is
Input to the source line of the TFT that constitutes a. On the other hand, the TF constituting the sample and hold switch 106a
The NAND gate 160a and the inverter 16
The sampling signal SL1-Data1 via 2a is input. This sampling signal SL1-Dat
As shown in FIG. 11, a1 is set to a sampling period of three periods in which the data length of the phase expansion signal is six periods of the dot clock signal and 1.5 periods are removed before and after that. Have been. Therefore, similarly to the first embodiment, it is possible to write stable data that is not affected by the previous data.

(3) Third Embodiment This third embodiment uses a layer development signal having a data length of six periods of the dot clock and a sampling signal having a sampling period of two periods of the dot clock. The display drive is performed.

The difference from the first embodiment is that the data side drive circuit and the like shown in FIG. 2 are changed to those shown in FIG.

As shown in FIG. 12, the data side driving circuit 10
4 has first and second columns of shift registers 300 and 310. An input signal DX serving as shift data commonly input to each of the shift registers 300 and 310 is:
As shown in FIG. 13, the signal becomes HIGH over four periods of the dot clock signal DC. Also, the first
The first clock signal CLK1 shown in FIG. 12 and its first inverted clock signal are input to the column shift registers 300. As the first clock signal CLK1, as shown in FIG. 13, a pulse having a half pulse width of the input signal DX is repeatedly output at a cycle of the pulse width of the input signal DX. Similarly,
The second clock signal CLK2 and its inverted clock signal are input to the second column of shift registers 310, respectively. The rising timing of the second clock signal CLK2 is different from the rising timing of the first clock signal CLK1 by one period of the dot clock DC.

The shift registers 300 and 310 in each column are
Each is configured to include a multi-stage master-slave type clocked inverter.

The first and second columns of shift registers 30
0, 310 output signals SR1-OUT1,... SR1-O
The UT 4 is as shown in FIG.

The NAND circuit 160a provided before the sample and hold switch 106a connected to the first data signal line 112a has a first output signal SR1-from the first stage of the shift register 300 in the first column. OUT
1 and the third output signal SR1-OUT2 from the second stage
Is input. Therefore, the sampling signal SL1-Data1 obtained via the NAND circuit 160a and the subsequent inverter 162a is the first output signal S1.
The logical product of R1-OUT1 and the third output signal SR1-OUT2 is obtained, and as shown in FIG. 13, a period of two periods of the dot clock DC is set as a sampling period.

Similarly, the second data signal line 112b
Is connected to the NAND circuit 160b, the signal SR2-OUT1 from the first stage of the shift register 310 in the second column is supplied to the NAND circuit 160b.
And a signal SR2-OUT2 from the second stage. Therefore, the second sampling signal SL2-Data2 obtained via the NAND circuit 160b and the inverter 162b at the subsequent stage is smaller than the first sampling signal SL1-Data1 in the dot block D.
Although the rise is delayed by one cycle of C, the sampling period is also a period of two periods of the dot clock DC.
Note that the same applies to data signal lines after the third data signal line.

(Regarding Data Sampling Operation) FIG.
4 shows a relationship between the phase expansion signals Data1 to Data6 input to the respective sampling switches 102 and the sampling signals SL (n) -Data (m).
FIG. 14 shows a signal waveform similar to that of FIG. For example, the first sample and hold switch 106a includes:
As shown in the figure, information having a data length of six periods of the dot clock DC is input to the source line of the TFT constituting the sample and hold switch 106a. On the other hand, the sampling signal SL1-Dat via the NAND circuit 160a and the inverter 162a is connected to the gate of the TFT constituting the sample-and-hold switch 106a.
a1 has been input. This sampling signal SL1-
Data1 is set to a sampling period of two cycles in which the data length of the phase expansion signal is six cycles of the dot clock signal DC and two cycles before and after that are removed. Therefore, similarly to the first and second embodiments, it is possible to write stable data that is not affected by the previous data.

(4) Fourth Embodiment In the fourth embodiment, the dot sequential driving of the first and third embodiments is changed to, for example, simultaneous driving of six pixels of the same number as the number of phase developments. For example, in the case of an engineering workstation (EWS), the frequency of the dot clock is increased (for example, 130 MHz), and the phase difference for the dot sequential driving is 10 nsec or less. In this case, if the sample and hold switch is a TFT, the switching cannot follow at all. Therefore, in such a case, simultaneous driving of a plurality is effective. Hereinafter, the fourth embodiment will be described with reference to FIGS.

(Regarding Configuration of Data Processing Circuit Block and Phase Expansion Signal) In the fourth embodiment, the first to sixth phase expansion signals output to the first to sixth phase expansion signal lines Data1 to Data6 are: In order to realize the simultaneous writing of six pixels, the leading positions of the switching of the respective pixel data coincide with each other as shown in FIG.

For this reason, in the fourth embodiment, FIG.
A data processing block 30 shown in FIG.
Has been added. By the first sample and hold operation in the phase expansion circuit 32, as shown in FIG. 2, the head position of each pixel data of each phase expansion signal is set to one dot clock DC.
It will be shifted by the period. However, as shown in FIG. 17, the first to sixth phase expansion signal lines Data1 to Data6 output to the first to sixth phase development signal lines Data1 to Data6 by collectively sampling and holding again in the subsequent sample and hold circuit 36. In the phase development signal, the head positions of the respective pixel data coincide. Incidentally, as the sample-hold circuit 36 in the subsequent stage,
A buffer memory can be used. Further, an amplifying / inverting circuit 34 may be arranged at a stage preceding the phase expanding circuit 32.

(Regarding the configuration and operation of the data side drive circuit) As shown in FIG.
Has a first column of shift registers 400. The input signal DX, clock signal CLK, and its inverted clock signal, which are shift data input to the shift register 400, are the input signal DX of the first embodiment shown in FIG.
The same as the clock signal CLX and its inverted clock signal. That is, the input signal DX is, as shown in FIG.
It is a signal that becomes HIGH over eight periods of the dot clock signal DC. As the clock signal CLK, as shown in FIG. 16, a pulse having a half pulse width of the input signal DX is repeatedly output at a cycle of the pulse width of the input signal DX.

The shift register 400 includes a multi-stage master-slave type clocked inverter. The output signal SL of each stage of the shift register 400
1,... SL8 are as shown in FIG.

In the fourth embodiment, the first to the sixth
The first output signal SL1 from the first stage of the shift register 400 is commonly input to the gates of the sample and hold switches 106a to 106f connected to the data signal lines 112a to 112f.

Similarly, the gates of the sample and hold switches 106g to 106l connected to the seventh to twelfth data signal lines 112g to 112l are connected to the fourth output signal SL4 from the fourth stage of the shift register 400. Are commonly input. The same applies to data signal lines after the thirteenth data signal line.

As a result, as shown in FIG. 17, a phase development signal having a data length of six periods of the dot clock DC is
The period of four periods of the dot clock DC is commonly set as the sampling period. Therefore, similarly to the first to third embodiments, it is possible to write stable data which is not affected by the previous data.

In the fourth embodiment, the same input signal DX, clock signal CLX and its inverted clock signal as in the first embodiment are used, but corresponding signals in the second and third embodiments may be used. it can. When the signal of the second embodiment is used, three periods of the dot clock DC are commonly set as the sampling period. Similarly, when the signal of the third embodiment is used, two periods of the dot clock DC are commonly set as the sampling period.

(5) Fifth Embodiment The fifth embodiment is a modification of the first to third embodiments.
As shown in FIG. 18, in the data processing circuit block 30, amplification and polarity inversion are performed first, and then, six-phase expansion is performed. In this case, as shown in FIG. 18, only one amplification and polarity inversion circuit 34 is required. Therefore, the circuit scale is reduced as compared with the case of FIG. 3, and the variation in the signal potential between the six phase expansion signal lines is reduced only by the DC offset of the six sample and hold circuits. It should be noted that the variation in the signal potential between the six phase-expanded signal lines in the case of FIG. 3 is larger due to the variation in the gain in the six video amplifiers. The amplifying / polarity inverting circuit 34 in FIG. 18 may use the configuration shown in FIG. 4B, and the same applies to the sixth and subsequent embodiments described below.

(6) Sixth Embodiment The sixth embodiment is a modification of the fourth embodiment. As in the fifth embodiment, as shown in FIG. And the polarity is reversed, and then the six-phase development is performed. In this case, as shown in FIG. 19, only one amplification / polarity inversion circuit 34 is required. Therefore, the circuit scale is reduced as compared with the case of FIG. 3, and the variation in the signal potential of the six image signal lines is reduced.

FIG. 20 is a timing chart for explaining the operation of the circuit of FIG. As described above, the output of the phase expansion circuit 32 in FIG. 19 corresponds to the first sample-and-hold output shown in FIG. The switches 550a to 550f provided in the sample and hold circuit 36 in FIG. 19 are simultaneously turned on and off based on the second sample and hold clock SCLK7 in FIG. As a result, the buffers 554a to 554a in FIG.
In the output of 554f, as shown as the second sample-and-hold output in FIG. 20, the head position of each pixel data matches.

(7) Seventh Embodiment This seventh embodiment is a modification of FIG. 19, in which two sample-and-hold circuits 36 and 38 are provided after the phase expansion circuit 32 as shown in FIG. I have. FIG. 22 is a timing chart illustrating the operation of the circuit of FIG. FIG.
The output of one phase expansion circuit 32 corresponds to the first sample-and-hold output shown in FIG. The switches 550a to 550c provided in the sample and hold circuit 36 in FIG. 21 are simultaneously turned on and off based on the sampling clock SCLK7 in FIG. As a result, the output positions of the buffers 554a to 554c in FIG. 21 coincide with the head positions of the respective pixel data, as shown as the second sample and hold output in FIG. The switches 550d to 550f provided in the sample and hold circuit 36 in FIG. 21 are simultaneously turned on and off based on the sampling clock SCLK8 in FIG. As a result, the outputs of the buffers 554a to 554c in FIG.
As shown as the second sample-and-hold output in FIG. 22, the head positions of the respective pixel data match. The switches 560a to 560f provided in the sample-hold circuit 38 at the last stage in FIG. 21 are simultaneously turned on and off based on the sampling clock SCLK9 in FIG.
As a result, the outputs of the buffers 564a to 564f in FIG. 21 have the same head positions of the respective pixel data as shown as the third sample and hold output in FIG.

Thus, in each data sampling, a portion other than the end of the data area having the data length expanded into six phases can always be sampled. Therefore, unnecessary components are prevented from being mixed into the waveform supplied to the display element of the liquid crystal panel, and the image quality is improved.

(8) Eighth Embodiment In the above-described first to seventh embodiments, the polarity of an image signal is inverted for each line or frame.
The polarity inversion drive can be performed for each line or each frame of the liquid crystal panel. In the eighth embodiment, the polarity inversion driving for each dot of the liquid crystal panel is enabled, and the unevenness in signal variation among the six phase development signal lines is reduced.

As shown in FIG.
And second polarity inverting circuits 600 and 6 receiving the output of
10 are provided. The circuit configurations of the first and second polarity inversion circuits 600 and 610 are the same as those in FIG. 4, and the switches at the last stage are a first switch SW1 and a second switch SW2, respectively. The first and second switches SW
1 and 2 are driven so as to select mutually different polarities in the case of dot inversion driving. When performing line inversion and frame inversion, the first and second switches SW1,
2 are driven to select the same polarity.

The output of the first switch SW1 is connected to the first, third and fifth switches 500a, 500 of the phase expansion circuit 34.
c, 500e. The output of the second switch SW2 is the second, fourth, and sixth switches 50 of the phase expansion circuit 34.
0b, 500d, and 500f.

The first to sixth switches 500a to 500a-5
00f to drive 00f
As shown in FIG. 24, six types of HCLs 6 are prepared, and are generated by the timing generation circuit block 20 based on the select signals S1 to S6. In this device, the liquid crystal panel 1
Based on the horizontal synchronization and vertical synchronization of the driving of 0, supply of six types of sampling clocks SHCL1 to SHCL6 is
Switching is performed by selecting from the patterns of S1 to S6. For this purpose, a hexadecimal counter for counting the horizontal synchronization signal is provided in the timing generation circuit 20.
Each time the hexadecimal counter counts, in other words, one horizontal scan (1
H), the select signals S1 to S6 are sequentially switched and output.

Here, the phase expansion signal outputs of the buffers 504a to 504f, which are the outputs of the phase expansion circuit 32, are respectively represented by V
1 to V6. When the outputs V1 to V6 are rearranged to pixel positions, the driving method shown in FIG. 25 can be considered.

FIG. 25 shows that the select signal S is applied to the first line.
The sampling order is switched according to the select signal S2 for the first and second lines, the select signal S3 for the third line,... The sixth line according to the select signal S6, and this is repeated for the subsequent lines. In FIG. 25, + and-indicate the polarity of data. By switching the first and second switches SW1 and SW2 according to a signal from the timing generation circuit block 20, so-called dot inversion driving as shown in FIG. 25 is possible. Becomes The drive output shown in FIG.
.. (First line) and b1, b2... (Second line) must be supplied to each pixel as shown in FIG.

In the eighth embodiment, the output of FIG.
A connection switching circuit (rotation circuit) 700 for switching the connection between the six phase development signal output lines 505a to 505f and the six phase development signal supply lines Data1 to Data6 so as to be supplied to each pixel as shown in FIG. Is provided. This switching must be performed in synchronization with the switching of the phase expansion order in the above-described phase expansion circuit 34. Based on the signal from the timing generation circuit block 20, the switching shown in FIG.
Selected from the street. By this switching, the dot inversion drive shown in FIG. 26 can be realized.

Here, according to the eighth embodiment, even if there is a variation in the gain of, for example, an amplifier in the middle of the six phase expansion signal lines, for example, even if the gain of one amplifier is high, LCD panel 10
Since it is not continuous in the vertical direction of 0 and is scattered in an oblique direction, it can be visually inconspicuous.

(9) Ninth Embodiment An electronic apparatus using the image display device of each of the above embodiments includes a display information output source 1000, a display information processing circuit 1002, a display drive circuit 1004, and a display information output circuit 1000 shown in FIG. Display panel 1006 such as a liquid crystal panel, clock generation circuit 100
8 and a power supply circuit 1010. The display information output source 1000 includes a memory such as a ROM and a RAM, a tuning circuit for tuning and outputting a television signal, and the like. And output display information such as a video signal. Display information processing circuit 1
002 is the data processing circuit block 3 of each embodiment described above.
0, which processes and outputs the display information based on the clock from the clock generation circuit 1008. The display information processing circuit 1002 can include a known gamma correction circuit, a clamp circuit, and the like in addition to the above-described amplification / polarity inversion circuit, phase expansion circuit, rotation circuit, and the like. The drive circuit 1004 includes the above-described scan-side drive circuit 102 and data-side drive circuit 104, and includes a liquid crystal panel 1006.
Is driven for display. The power supply circuit 1010 supplies power to each of the above circuits.

FIG. 28 shows an electronic apparatus having such a configuration.
29, a multimedia personal computer (PC) and an engineering workstation (EWS) shown in FIG. 29, a pager shown in FIG. 30, or a mobile phone, a word processor, a television, a viewfinder type video or a monitor direct view type video. Examples include a tape recorder, an electronic organizer, an electronic desk calculator, a car navigation device, a POS terminal, and a device having a touch panel.

The liquid crystal projector shown in FIG. 28 is a projection type projector using a transmission type liquid crystal panel as a light valve, and uses, for example, a three-plate prism type optical system.

In FIG. 28, in a projector 1100, projection light emitted from a lamp unit 1102 of a white light source is divided into R, G, and B light by a plurality of mirrors 1106 and two dichroic mirrors 1108 inside a light guide 1104. It is divided into primary colors and guided to three active matrix type liquid crystal panels 1110R, 1110G and 1110B for displaying images of each color. Then, the respective liquid crystal panels 1110R, 111
Light modulated by OG and 1110B is incident on dichroic prism 1112 from three directions. In the dichroic prism 1112, the red R and blue B lights are bent by 90 °, and the green G light goes straight, so that the images of the respective colors are synthesized, and a color image is projected on a screen or the like through the projection lens 1114.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206.

A pager 1300 shown in FIG. 30 includes a liquid crystal display substrate 1304, a light guide 1306 provided with a backlight 1306a, a circuit board 1308, and first and second shield plates 1310 and 13 in a metal frame 1302.
12, two elastic conductors 1314 and 1316, and a film carrier tape 1318. Two elastic conductors 1314 and 1316, and film carrier tape 1
Reference numeral 318 connects the liquid crystal display substrate 1304 and the circuit substrate 1308.

Here, the liquid crystal display substrate 1304 is one in which liquid crystal is sealed between two transparent substrates 1304a and 1304b, thereby constituting at least a liquid crystal display panel. The drive circuit 100 shown in FIG.
4 or in addition thereto, a display information processing circuit 1002 can be formed. Circuits not mounted on the liquid crystal display substrate 1304 are external circuits of the liquid crystal display substrate,
In the case of 3, it can be mounted on the circuit board 1308.

FIG. 30 shows the configuration of the pager, so a circuit board 1308 is required. However, when a liquid crystal display device is used as one component for an electronic device, and a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is a liquid crystal display substrate 130.
4. Alternatively, a structure in which the liquid crystal display substrate 1304 is fixed to a metal frame 1302 serving as a housing can be used as a liquid crystal display device which is one component for electronic devices. Further, in the case of a backlight type, a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a can be incorporated in a metal frame 1302 to constitute a liquid crystal display device. Instead of these, as shown in FIG.
Polyimide tape 13 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting
22 with an IC chip 1324 mounted on it (TCP (Tape)
Carrier Package) 1320 can be connected to use as a liquid crystal display device, which is one component of electronic equipment.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-described various liquid crystal panels, but is also applicable to an image display device using an electroluminescence, a plasma display device, a CRT, or the like. Further, the number of phase expansions, the data length of the phase expansion signal, and the length of the sampling period corresponding thereto can be variously modified other than the above-described embodiment.

In the above embodiment, the description has been made based on the example in which the analog image signal is phase-expanded and sampled and held. However, the capacity for phase expansion and sampling in the embodiment can be a digital memory. In this case, the digital image signal is converted into parallel 4-bit data, Data1-1 to 1-4,... Data6-1 to 6-4.
And the data 1-1 to 1-4 are sampled by the latch circuit using the same sampling signal. The output of the latch circuit is subjected to D / A conversion or pulse width modulation, and is output to a data signal line.
4 to the liquid crystal layer 116.

Further, in the above embodiment, an example in which a TFT is used as a switching element of a pixel has been described, but the switching element may be a two-terminal element such as an MIM. In this case, since a two-terminal element and a liquid crystal layer are connected in series between the scanning signal line and the data signal line to form a pixel, a difference voltage between the two signal lines is supplied to the pixel.

In the above embodiment, the TFT is used as a switching element, and the substrate on which the elements of the liquid crystal panel are formed is a glass or quartz substrate. However, a semiconductor substrate can be used instead. In this case, not the TFT but the MOS transistor becomes the switching element.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory view of an active matrix type liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a schematic explanatory diagram for explaining six-phase deployment driving.

FIG. 3 is a circuit diagram showing a circuit configuration example of a data processing circuit block of FIG. 1;

FIGS. 4A and 4B are circuit diagrams each showing a specific example of the amplification and polarity inversion circuit shown in FIG. 3;

FIG. 5 is a timing chart showing an operation of the phase expansion circuit of FIG. 3;

FIG. 6 is a circuit diagram showing details of a data-side drive circuit of the first embodiment.

7A is a timing chart of the data driving circuit shown in FIG. 6, and FIG. 7B is a timing chart of the scanning driving circuit.

FIG. 8 is a characteristic diagram illustrating a relationship between a data length of a phase expansion signal and a sampling period according to the first embodiment.

FIG. 9 is a circuit diagram showing details of a data-side drive circuit according to a second embodiment of the present invention.

FIG. 10 is a timing chart of the data-side processing circuit shown in FIG. 9;

FIG. 11 is a characteristic diagram illustrating a relationship between a data length of a phase expansion signal and a sampling period according to the second embodiment.

FIG. 12 is a circuit diagram showing details of a data-side drive circuit according to a third embodiment of the present invention.

13 is a timing chart of the data-side drive circuit shown in FIG.

FIG. 14 is a characteristic diagram illustrating a relationship between a data length of a phase expansion signal and a sampling period according to the third embodiment.

FIG. 15 is a circuit diagram showing details of a data side driving circuit and a data processing circuit block according to a fourth embodiment of the present invention.

16 is a timing chart of the data-side drive circuit shown in FIG.

FIG. 17 is a characteristic diagram illustrating a relationship between a data length of a phase expansion signal and a sampling period according to the fourth embodiment.

FIG. 18 is a circuit diagram showing a configuration example of a data processing circuit block according to a fifth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration example of a data processing circuit block according to a sixth embodiment of the present invention.

20 is a timing chart showing a phase expansion operation in the circuit of FIG.

FIG. 21 is a circuit diagram showing a configuration example of a data processing circuit block according to a seventh embodiment of the present invention.

FIG. 22 is a timing chart showing a phase expansion operation in the circuit of FIG. 21;

FIG. 23 is a circuit diagram showing a configuration example of a data processing circuit block according to an eighth embodiment of the present invention.

24 is a schematic explanatory diagram for explaining types of sampling signals input to the phase expansion circuit shown in FIG. 23 and corresponding line connection states switched by the connection switching circuit.

25 is a schematic explanatory diagram in which the buffer output shown in FIG. 23 at the time of polarity inversion driving for each dot is rearranged into pixel positions.

26 is a schematic explanatory diagram showing the polarity of pixel data at the time of polarity inversion drive for each dot achieved by the drive of FIG. 25.

FIG. 27 is a block diagram of an electronic device according to a ninth embodiment of the present invention.

FIG. 28 is a schematic explanatory view of a projector to which the present invention is applied.

FIG. 29 is an external view of a personal computer to which the present invention is applied.

FIG. 30 is an exploded perspective view of a pager to which the present invention is applied.

FIG. 31 is a schematic perspective view showing an example of a liquid crystal display device provided with an external circuit.

FIG. 32 is a schematic explanatory diagram for explaining a problem when phase development is performed.

FIG. 33 is a schematic explanatory diagram for explaining generation of a ghost when an image is displayed using the phase expansion signal of FIG. 32;

FIG. 34 is a waveform diagram schematically showing a voltage waveform supplied to the liquid crystal layer, which is a waveform in which the ghost of FIG. 33 occurs.

[Explanation of symbols]

 32 phase expansion circuit 34 amplification / inversion circuit 36 sample hold circuit 100 liquid crystal panel 102 scan side drive circuit 104 data side drive circuit 106a-106g sample hold switch 110 scan signal line 112 data signal line 120-150, 200-220 shift register 506a To 506f Amplifying circuits 508a to 508f Polarity inverting circuits 600, 610 First and second polarity inverting circuits

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 611 G09G 3/20 611H 611G 623 623M 633 633C

Claims (15)

[Claims] An image display section having pixels arranged at pixel positions formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines arranged in a matrix; Scanning signal line selecting means for supplying a line, and a plurality of phase expansion signals obtained by sampling an image signal having data corresponding to each of the pixel positions in time series and converting the data into a data length longer than the sampling period. Phase expansion means for outputting in parallel each of the data signal lines, each of which receives one of the plurality of phase expansion signals as input, samples the pixel data in the phase expansion signal, A plurality of sampling means for supplying a data signal to the data signal line as a data signal; and a sampling signal having a sampling period shorter than a period corresponding to the data length of the phase expansion signal. To generate an image display, comprising in that a, a sampling signal generating means for supplying to said sampling means. 2. The phase expansion unit according to claim 1, wherein the phase expansion unit sequentially shifts a head position of pixel data of each of the phase expansion signals based on a reference clock, and outputs each of the phase expansion signals in parallel. The sampling signal generation unit sets the start time of the sampling period of the sampling signal output to each of the sampling units so as to be sequentially shifted, and drives the pixels connected to one scanning signal line in a point-sequential manner. An image display device comprising: 3. The sampling signal generating means according to claim 2, wherein the sampling signal generating means has a plurality of stages for sequentially shifting the input signal, and the output signal of each stage has a timing at which the output signal of the next stage partially overlaps the output signal of the next stage. A plurality of shift registers which are connected to each of the sampling means to be output, and which receive the two output signals from the shift register whose signal phases overlap with each other, and output a logical product of the output signals as the sampling signals to the sampling means; An image display device, comprising: a logical product circuit of: 4. The phase expansion unit according to claim 1, wherein the phase expansion unit outputs each of the phase expansion signals in parallel by matching the head of the pixel data, and the sampling signal generation unit outputs the phase expansion signal line. A plurality of sampling means connected to the same number of the data signal lines are supplied with the sampling signals having the same start time of the sampling period, and the plurality of sampling means connected to one scanning signal line. The pixel of
An image display device, wherein the image display device is simultaneously driven by the total number of the phase expansion signal lines. 5. The scanning signal generating device according to claim 4, wherein the sampling signal generating means has a shift register for sequentially shifting and transmitting an input signal by one cycle of a reference clock, and m (1 ≦ m ≦ one scanning signal line). (3m-2) th shift register output in one horizontal period is input to the plurality of sampling means during the (d) total number of pixels / total number of phase development signal lines) simultaneous drive. Image display device. 6. The image display unit according to claim 1, wherein the image display unit is a liquid crystal panel having a liquid crystal interposed between a pair of substrates, and the plurality of sampling units are formed on one of the substrates. An image display device comprising: a plurality of thin film transistors; and wherein the sampling signal from the sampling signal generating unit is supplied to a gate of each of the thin film transistors. 7. The image display unit according to claim 1, wherein the image display unit is a liquid crystal panel having a liquid crystal interposed between a pair of substrates, and the image display unit is connected to the image display unit via the data signal line. A difference voltage between a voltage applied to one end of a pixel and a voltage applied to the other end of the pixel is applied to the liquid crystal at the pixel position, and the polarity of an electric field applied to the liquid crystal is inverted to drive the liquid crystal. A first polarity image signal for driving the pixel with a first polarity with respect to a polarity inversion reference potential from an input image signal before the phase expansion means; Generates a second polarity image signal for driving the pixel with a second polarity having the opposite polarity, and outputs one of the first and second polarity image signals to the phase developing means. The phase expansion means is further provided, wherein the first and second poles are provided. An image signal phase expansion, first, an image display apparatus and outputting the second polar phase-expanded signal. 8. The method according to claim 7, wherein the polarity inverting means outputs first polarity inverting means for outputting one of the first and second polarity image signals, and the other of the first and second polarity image signals. An image display device comprising: a second polarity inverting means for outputting. 9. The image display unit according to claim 1, wherein the image display unit is a liquid crystal panel having a liquid crystal interposed between a pair of substrates, and the image display unit is connected to the image display unit via the data signal line. A difference voltage between a voltage applied to one end of a pixel and a voltage applied to the other end of the pixel is applied to the liquid crystal at the pixel position, and the polarity of an electric field applied to the liquid crystal is inverted to drive the liquid crystal. A first polarity phase development signal for driving the pixel with a first polarity with respect to a polarity inversion reference potential from one of the plurality of phase development signals at a stage subsequent to the phase development means; A second polarity phase development signal for driving the pixel with a second polarity having a polarity opposite to the first polarity, and generating one of the first and second polarity phase development signals using the plurality of signals. A plurality of polarity inversion means for outputting to the sampling means are further provided. An image display device characterized by the above-mentioned. 10. The polarity inverting means according to claim 9, wherein said polarity inversion means outputs one of said first and second polarity phase development signals, and said first and second polarity inversion means.
An image display device comprising: a second polarity inversion unit that outputs the other of the polarity phase expansion signals. 11. A switching means according to claim 1, wherein said plurality of phase development signals are switched and supplied to said plurality of sampling means, and a development order in said phase development means is changed and controlled, and An image display device, further comprising: change control means for changing and controlling supply destinations of the plurality of phase expansion signals by the switching means in accordance with the expansion order. 12. A switching means according to claim 7, wherein said first and second polarity phase development signals are switched and supplied to said plurality of sampling means, and a development order in said phase development means is changed. An image display device, further comprising: control means for controlling and changing the supply destinations of the first and second polarity phase development signals by the switching means in accordance with the development order. 13. An electronic apparatus comprising the image display device according to claim 1. 14. A display driving apparatus for driving an image display unit having pixels arranged at pixel positions formed by intersections of a plurality of data signal lines and a plurality of scanning signal lines arranged in a matrix, Scanning signal line selecting means for sequentially supplying signals to the scanning signal lines; sampling an image signal having data corresponding to each of the pixel positions in a time series, and converting the image signal into a data length longer than the sampling period. Phase expansion means for outputting the plurality of phase expansion signals in parallel, each of the plurality of phase expansion signals being connected to each of the data signal lines, receiving one of the plurality of phase expansion signals as inputs, and A plurality of sampling means for sampling and supplying the data signal line to the data signal line as a data signal; and a sampler shorter than a period corresponding to the data length of the phase expansion signal. And it generates a sampling signal of ring period, a display driving apparatus is characterized by providing a sampling signal generating means for supplying to said sampling means. 15. An image display method for driving a pixel at a pixel position formed by the intersection of a plurality of data signal lines and a plurality of scanning signal lines arranged in a matrix, wherein data corresponding to each of the pixel positions is stored. Sampling an image signal having a time series, and outputting in parallel a plurality of phase expansion signals converted to a data length longer than the sampling period, and the data in the plurality of phase expansion signals, Sampling each in a sampling period shorter than a period corresponding to the data length of the phase expansion signal, and sequentially selecting the scanning signal lines, and applying the phase expansion to a plurality of pixels on the selected scanning signal lines. Supplying data sampled from a signal as a data signal via the data line.