JPH10289996A - Semiconductor quantum dot and its manufacture - Google Patents

Semiconductor quantum dot and its manufacture

Info

Publication number
JPH10289996A
JPH10289996A JP9756997A JP9756997A JPH10289996A JP H10289996 A JPH10289996 A JP H10289996A JP 9756997 A JP9756997 A JP 9756997A JP 9756997 A JP9756997 A JP 9756997A JP H10289996 A JPH10289996 A JP H10289996A
Authority
JP
Japan
Prior art keywords
growth
type growth
semiconductor quantum
island
quantum dot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9756997A
Other languages
Japanese (ja)
Other versions
JP4066002B2 (en
Inventor
Yoshiaki Nakada
義昭 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9756997A priority Critical patent/JP4066002B2/en
Publication of JPH10289996A publication Critical patent/JPH10289996A/en
Application granted granted Critical
Publication of JP4066002B2 publication Critical patent/JP4066002B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To realize a device such as a single electronic element wherein a plurality of quantum dots are connected (arranged), by controlling arrangement of a semiconductor quantum dot consisting of an S-K type growth mode, and enabling a semiconductor quantum dot without damage to be generated in uniform size and uniform density in a semiconductor quantum dot, and its manufacturing method. SOLUTION: An S-k (stranski-Krastanor) type growth mode 13A which is generated in an initial stage during formation of strain hetero crystal (such as InAs to GaAs of a foundation) is formed, a first over-growth layer 14 whose material (GaAs, for example) is different from a constituent mateal of the S-K type growth mode 13A and whose thickness is at most a height of the S-K type growth mode 13A is formed, and heat treatment is carried out to vaporize or extend a top part of the S-K type growth mode 13A to make it flush with the surface of the first over-growth layer 14.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、化合物半導体から
なる量子ドット、例えばInAs/GaAsなどの歪み
系ヘテロ結晶を成長させる際の初期に出現するS−K
(Stransky−Krastanov)型成長島を
利用する半導体量子ドット及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SK which appears at the initial stage of growing a quantum dot composed of a compound semiconductor, for example, strained heterocrystal such as InAs / GaAs.
The present invention relates to a semiconductor quantum dot using a (Transky-Krastanov) type growth island and a method of manufacturing the same.

【0002】現在、個別の半導体量子ドットが実現さ
れ、多くの実験や測定がなされているところであるが、
これをデバイスとして用いるには、アレイ化することが
必要であり、しかも、成長島の形状を均一にしなければ
ならない。
At present, individual semiconductor quantum dots have been realized and many experiments and measurements have been made.
In order to use this as a device, it is necessary to form an array, and the shape of the growth island must be uniform.

【0003】然しながら、均一な半導体量子ドットを制
御された状態に配列してアレイ化することは甚だ困難で
あって、これが実用化を妨げる主因になっているので、
この問題を解消しなければならず、本発明は、それに応
える一手段を提供することができる。
However, it is extremely difficult to arrange uniform semiconductor quantum dots in a controlled state to form an array, and this is a major factor hindering practical use.
This problem must be solved, and the present invention can provide a means for responding thereto.

【0004】一般に、半導体量子ドット(箱)を形成す
る方法としては、大別して二種類の方法が知られてい
る。即ち、 リソグラフィ技術などで加工することに依って構造
を実現する方法 結晶成長時の表面現象(自然現象)を利用して自己
形成的に構造を成長する方法である。
[0004] Generally, two types of methods are known for forming semiconductor quantum dots (boxes). That is, a method of realizing a structure by processing with a lithography technique or the like A method of growing a structure in a self-forming manner using a surface phenomenon (natural phenomenon) during crystal growth.

【0005】具体的に説明すると、 (1)分子線エピタキシャル成長(molecular
beam epitaxy:MBE)法や有機金属化
学気相堆積(metalorganic chemic
al vapour deposition:MOCV
D)法などを適用することに依り、基板上に必要な半導
体層を積層形成し、これをリソグラフィ技術、特に電子
ビーム・リソグラフィやイオン・ビーム・リソグラフィ
などを適用し、エッチングを行なって箱状に加工する。
Specifically, (1) molecular beam epitaxial growth (molecular)
Beam epitaxy (MBE) and metalorganic chemical vapor deposition
al vapor deposition: MOCV
D) By applying the method or the like, a necessary semiconductor layer is formed on the substrate by lamination, and this is etched and box-shaped by applying lithography technology, in particular, electron beam lithography or ion beam lithography. Process into

【0006】(2)前記(1)と同様にして基板の加工
を行い、その後、MBE法やMOCVD法などに於ける
成長の選択性を利用して箱状構造を形成する。
(2) The substrate is processed in the same manner as in the above (1), and thereafter, a box-shaped structure is formed by utilizing the selectivity of growth in the MBE method, the MOCVD method or the like.

【0007】(3)微傾斜基板上の表面ステップやキン
クを利用し、結晶成長を横方向にも制御して箱を形成す
る。
(3) A box is formed by controlling crystal growth in the lateral direction by using surface steps and kinks on a vicinal substrate.

【0008】(4)InAs/GaAs等の高歪み系ヘ
テロ構造の成長初期に出現するS−K型成長島を利用し
て箱を得る。などが挙げられる。
(4) A box is obtained by using SK type growth islands appearing at an early stage of growth of a high strain type heterostructure such as InAs / GaAs. And the like.

【0009】ところで、前記(1)及び(2)に挙げた
手段を採った場合、半導体層の表面から内部に向かって
ダメージが入り易く、そして、箱のサイズが現用加工技
術の精度に依存するので、100〔nm〕以下のサイズ
制御は難しく、また、サイズのばらつきが大きい。
By the way, when the means described in the above (1) and (2) are adopted, damage is easily caused from the surface of the semiconductor layer toward the inside, and the size of the box depends on the precision of the current working technology. Therefore, it is difficult to control the size to 100 nm or less, and the size varies greatly.

【0010】また、前記(3)に挙げた手段を採った場
合、表面ステップの形状制御が難しいのに加えて横方向
で材料のミキシングが起こる為、サイズ、組成、横方向
界面の急峻性を精密に制御することができない。
When the means described in (3) above is employed, it is difficult to control the shape of the surface steps and, in addition, mixing of the material occurs in the lateral direction, so that the size, composition, and abruptness of the lateral interface are reduced. Cannot be precisely controlled.

【0011】更にまた、前記(4)に挙げた手段を採っ
た場合、加工プロセスを一切用いていない為、加工ダメ
ージはなく、成長島形成が表面エネルギや歪みエネルギ
に起因している為、平衡状態に近付けることに依り、箱
のサイズをかなり揃えることができ、実験レベルではあ
るが、標準偏差10〔%〕程度が得られている。
Furthermore, when the means described in (4) above is employed, no processing is used, and no processing damage is caused. Since the growth island formation is caused by surface energy and strain energy, the equilibrium is not obtained. By approaching the state, the sizes of the boxes can be considerably uniformed, and a standard deviation of about 10% is obtained although it is an experimental level.

【0012】このように、前記(4)に挙げた手段に
は、前記(1)乃至(3)の手段にはない利点があるも
のの、成長島の生成が、下地の表面状態、即ち、ステッ
プ或いはキンク、表面に於ける原子の再配列構造、表面
ディフェクトなどに強く依存することから、様々な問題
が発生する。
As described above, although the means described in (4) has an advantage that is not provided in the means described in (1) to (3), the formation of the growth island is achieved by the surface condition of the base, that is, the step. Alternatively, various problems occur because they strongly depend on kinks, rearrangement structure of atoms on the surface, surface defects, and the like.

【0013】即ち、形成される量子ドットに疎密が発生
し、均一な密度にならず、そして、これに起因してサイ
ズにも若干のばらつきが生じ、しかも、通常の方法で得
られる発光半値幅(PL)は80〔meV〕〜100
〔meV〕になっている。
That is, the formed quantum dots are sparse and dense, do not have a uniform density, and due to this, there is a slight variation in the size. (PL) is 80 [meV] to 100
[MeV].

【0014】この発光半値幅は、現在、半導体レーザの
活性層として実用化の域にある量子井戸に比較して遙に
大きく、従って、前記S−K型成長島をもつ半導体レー
ザを作製したとしても、期待されるほどの特性改善、例
えば、しきい値が低下するなどの効果は得られない。
This emission half width is much larger than that of a quantum well which is currently in practical use as an active layer of a semiconductor laser. Therefore, it is assumed that a semiconductor laser having the SK type growth island is manufactured. However, such an effect cannot be obtained that the characteristics are improved as expected, for example, the threshold value is lowered.

【0015】前記(4)の手段を採った場合に於いて、
若し、量子ドットの配置制御が可能となり、ダメージが
ない量子ドットを均一サイズで均一な密度で生成させる
ことができれば、量子ドットを複数個連結(配列)した
デバイス、例えば単電子素子への応用も可能になる。
In the case where the means (4) is adopted,
If the arrangement of the quantum dots can be controlled and quantum dots without damage can be generated with a uniform size and a uniform density, application to a device in which a plurality of quantum dots are connected (arranged), for example, a single electron element Also becomes possible.

【0016】これまでに、前記(4)の手段を採って、
且つ、均一な形状の半導体量子ドットを制御された状態
に配列することについて、種々な試みがなされていて、
例えば、
Up to now, the above-mentioned means (4) has been adopted,
Various attempts have been made to arrange semiconductor quantum dots of a uniform shape in a controlled state,
For example,

【0017】(A)基板表面に段差が生成されるように
加工し、段差近傍に半導体量子ドットを生成させる方法
(要すれば、「D.S.L.Mui et al.,A
ppl.Phys.Lett.66(1995)」、を
参照)。
(A) A method of processing a substrate so that a step is formed on the substrate surface and generating semiconductor quantum dots in the vicinity of the step (if necessary, see DSL Mui et al., A
ppl. Phys. Lett. 66 (1995) ").

【0018】(B)パターンを形成した基板上に選択成
長法を適用してV字型の溝を形成し、その底部に半導体
量子ドットを配列する方法(要すれば、「IPRM′9
5 Late Newsにて口頭発表」、を参照)。
(B) A method of forming a V-shaped groove by applying a selective growth method on a substrate on which a pattern is formed, and arranging semiconductor quantum dots at the bottom thereof (if necessary, "IPRM'9").
Oral Presentation at 5 Late News ").

【0019】(C)ステップ・バンチングを生じた多段
ステップを形成し、半導体量子ドットを前記多段ステッ
プ上に優先的に生成させる(要すれば、「M.Kita
muraet al.,Proc. of IPRM′
95,(1995)p.736」、を参照)。が知られ
ている(尚、前記記述に於いて、「IPRM′95」
は、「The Seventh Internatio
nal Conference on Indium
Phosphide and Related Mat
erials」、である)。
(C) A multi-step with step bunching is formed, and semiconductor quantum dots are preferentially generated on the multi-step (refer to “M. Kita if necessary”).
muraet al. Proc. of IPRM '
95, (1995) p. 736 "). (Note that in the above description, “IPRM '95”
Is "The Seventh International
nal Conference on Indium
Phosphide and Related Mat
erials ").

【0020】[0020]

【発明が解決しようとする課題】前記(A)の問題点
は、半導体量子ドットを配列する為の段差形状の制御が
難しいことである。
The problem (A) is that it is difficult to control the shape of the step for arranging the semiconductor quantum dots.

【0021】前記(B)の問題点は、V字型の溝を形成
するのに費やされる領域、即ち、半導体量子ドットが生
成されない領域を広く必要とし、従って、高密度化する
ことができず、しかも、加工の工程が煩雑であり、そし
て、平坦(Planer)にならない。
The problem of the above (B) is that a region used for forming a V-shaped groove, that is, a region where semiconductor quantum dots are not generated, needs to be large, and therefore, it is impossible to increase the density. In addition, the processing steps are complicated, and the processing does not become flat (Planer).

【0022】前記(C)の問題点は、表面ステップのバ
ンチング制御が難しく、バンチング面に局所的にキンク
が集中したり、バンチング面にゆらぎが生じたりする
為、均一サイズの量子ドットを均一間隔で形成すること
ができない。
The problem (C) is that it is difficult to control the bunching of the surface steps, and the kink is locally concentrated on the bunching surface or the bunching surface fluctuates. Cannot be formed by

【0023】本発明は、S−K型成長島からなる半導体
量子ドットの配置を制御できるようにし、ダメージがな
い半導体量子ドットを均一サイズで均一な密度で生成さ
せることを可能にして、量子ドットを複数個連結(配
列)したデバイス、例えば単電子素子を実現できるよう
にする。
The present invention makes it possible to control the arrangement of semiconductor quantum dots composed of SK type growth islands and to produce semiconductor quantum dots having no damage at a uniform size and a uniform density. Are connected (arranged), for example, a single electron element can be realized.

【0024】[0024]

【課題を解決するための手段】本発明では、InAs/
GaAs等の高歪み系ヘテロ構造の成長初期に出現する
S−K型成長島からなる半導体量子ドットを形成してか
ら、成長島を構成する材料に比較して蒸気圧が低く、且
つ、熱的に安定な材料を用い、第1オーバ・グロース層
を成長島の高さよりも低く形成し、熱処理を行なって、
第1オーバ・グロース層から突出した部分を再蒸発、若
しくは、周囲に散らせてしまうことで、成長島の高さを
均一化することが基本になっている。
According to the present invention, InAs /
After forming semiconductor quantum dots composed of SK type growth islands appearing in the early stage of growth of a high strain type heterostructure such as GaAs, the vapor pressure is lower than that of the material forming the growth islands, and the thermal pressure is lower. The first overgrowth layer is formed to be lower than the height of the growth island using a material which is stable to
Basically, the height of the growth island is made uniform by re-evaporating or scattering the portion protruding from the first over-growth layer.

【0025】図4はS−K型成長島の高さについて説明
する為の半導体量子ドットの要部説明図であり、図に於
いて、1はGaAs基板、2はInAs層、3はInA
s成長島、Hは成長島の高さ、Dは成長島3に於ける底
面の直径をそれぞれ示している。
FIG. 4 is an explanatory view of a principal part of a semiconductor quantum dot for explaining the height of the SK type growth island. In the figure, 1 is a GaAs substrate, 2 is an InAs layer, and 3 is InA.
H indicates the height of the growing island, and D indicates the diameter of the bottom surface of the growing island 3.

【0026】通常、S−K型成長で生成される成長島、
例えば、図4に見られるようなGaAs基板1上のIn
As成長島3に於いては、高さHが3〔nm〕〜5〔n
m〕の範囲で、また、直径Dが20〔nm〕〜25〔n
m〕の範囲で分布が見られ、また、成長島3の切断側面
は扁平である。
Usually, a growth island generated by SK type growth,
For example, the In on the GaAs substrate 1 as shown in FIG.
In the As growth island 3, the height H is 3 [nm] to 5 [n
m] and the diameter D is 20 [nm] to 25 [n
m], and the cut side surface of the growth island 3 is flat.

【0027】この成長島3に於ける量子レベルに関して
は、成長島3の高さHが支配的であり、高さHのゆらぎ
が生む量子レベルのゆらぎの方が、直径Dのゆらぎが生
む量子レベルのゆらぎよりも遙に大きく、発光半値幅
は、高さのゆらぎに支配されているものと考えられる。
With respect to the quantum level in the growing island 3, the height H of the growing island 3 is dominant, and the fluctuation of the quantum level caused by the fluctuation of the height H is the quantum level generated by the fluctuation of the diameter D. It is much larger than the fluctuation of the level, and it is considered that the emission half width is dominated by the fluctuation of the height.

【0028】従って、成長島3の高さHを均一化するこ
とができれば、これまでに実現されている発光半値幅を
大きく低減することができる。因みに、直径Dのゆらぎ
で決定される発光半値幅は約10〔meV〕であり、こ
の値は、量子井戸の半値幅と略等しい。
Therefore, if the height H of the growth island 3 can be made uniform, the half-width of light emission that has been realized so far can be greatly reduced. Incidentally, the emission half width determined by the fluctuation of the diameter D is about 10 [meV], and this value is substantially equal to the half width of the quantum well.

【0029】前記したところから、本発明に依る半導体
量子ドット及びその製造方法に於いては、(1)歪み系
ヘテロ結晶(例えばGaAsとInAs)を成長させる
初期に生成され且つ高さが全面を覆う第1オーバ・グロ
ース層(例えば第1オーバ・グロース層14)の厚さに
合わせて均一化されたS−K型成長島(例えば成長島1
3A)からなることを特徴とするか、又は、
As described above, in the semiconductor quantum dot and the method for manufacturing the same according to the present invention, (1) the strain is generated at the initial stage of growing a strained heterocrystal (for example, GaAs and InAs) and the height is entirely SK-type growth islands (for example, growth island 1) that are made uniform according to the thickness of the first over-growth layer (for example, first over-growth layer 14) to be covered.
3A), or

【0030】(2)前記(1)に於いて、第1オーバ・
グロース層がS−K型成長島の構成材料に比較して蒸気
圧が低い構成材料(例えば成長島がInAsである場
合、GaAsとする)からなることを特徴とするか、又
は、
(2) In the above (1), the first over
The growth layer is made of a constituent material having a lower vapor pressure than that of the constituent material of the SK type growth island (for example, GaAs when the growth island is InAs), or

【0031】(3)歪み系ヘテロ結晶を成長させる初期
に生成されるS−K型成長島を形成する工程と、該S−
K型成長島の構成材料とは異なる材料からなり且つ厚さ
が該S−K型成長島の高さ以下である第1オーバ・グロ
ース層を形成する工程と、熱処理を施して該S−K型成
長島の頂部を蒸発若しくは横方向に展延して高さを該第
1オーバ・グロース層の表面に合わせる工程とが含まれ
てなることを特徴とする。
(3) a step of forming an SK type growth island generated at the initial stage of growing the strain-based heterocrystal;
Forming a first over-growth layer made of a material different from the constituent material of the K-type growth island and having a thickness equal to or less than the height of the SK-type growth island; Evaporating or spreading the top of the mold growth island in the lateral direction to adjust the height to the surface of the first overgrowth layer.

【0032】前記手段を採ることに依り、S−K型成長
島からなる半導体量子ドットの配置を制御でき、ダメー
ジがない半導体量子ドットを均一サイズで均一な密度で
生成させることが可能となり、量子ドットを複数個連結
(配列)したデバイス、例えば単電子素子を実現した
り、しきい値電流が小さく、温度特性に優れた半導体レ
ーザなどを実現することができる。
By employing the above means, the arrangement of semiconductor quantum dots composed of SK type growth islands can be controlled, and semiconductor quantum dots without damage can be generated with uniform size and uniform density. A device in which a plurality of dots are connected (arranged), for example, a single-electron element, or a semiconductor laser with a small threshold current and excellent temperature characteristics can be realized.

【0033】[0033]

【発明の実施の形態】図1乃至図3は方法の発明に関す
る実施の形態を説明する為の工程要所に於ける半導体量
子ドットを表す要部切断側面図であり、以下、これ等の
図を参照しつつ説明する。
1 to 3 are cutaway side views showing a main part of a semiconductor quantum dot in a process step for explaining an embodiment of a method invention. This will be described with reference to FIG.

【0034】図1(A)参照 1−(1) 面指数が(001)であるGaAs基板11をMBE
(molecularbeam epitaxy)装置
に於ける成長室内にセットし、温度を680〔℃〕で熱
処理することで酸化膜を除去する。
1 (A) 1- (1) A GaAs substrate 11 having a plane index of (001) is formed by MBE.
(Molecular beam epitaxy) An oxide film is removed by setting the apparatus in a growth chamber and performing a heat treatment at a temperature of 680 ° C.

【0035】1−(2) MBE法を適用することに依り、GaAs基板11上に
厚さが例えば400〔nm〕のGaAs層12を形成す
る。
1- (2) A GaAs layer 12 having a thickness of, for example, 400 [nm] is formed on a GaAs substrate 11 by applying the MBE method.

【0036】この時の主な成長条件を列挙すると、 成長温度:620〔℃〕 成長速度:0.8〔μm/時間〕 As圧:6×10-6〔Torr〕 である。The main growth conditions at this time are listed as follows: growth temperature: 620 ° C., growth rate: 0.8 μm / hour, As pressure: 6 × 10 -6 [Torr].

【0037】図1(B)参照 1−(3) MBE装置に於けるGa分子線セルのシャッタを閉じ
て、GaAs層12上に厚さが例えば約1.8分子層相
当分のInAs層13を成長させる。
Referring to FIG. 1B, the shutter of the Ga molecular beam cell in the MBE apparatus is closed, and the InAs layer 13 having a thickness corresponding to, for example, about 1.8 molecular layers is formed on the GaAs layer 12. Grow.

【0038】この時の主な成長条件を列挙すると、 成長温度:510〔℃〕 成長速度:0.1〔分子層/秒〕 As圧:6×10-6〔Torr〕 である。The main growth conditions at this time are as follows: growth temperature: 510 [° C.] growth rate: 0.1 [molecular layer / second] As pressure: 6 × 10 −6 [Torr].

【0039】これに依って、底面の直径Dが20〔n
m〕〜25〔nm〕程度、そして、高さHが3〔nm〕
〜5〔nm〕程度に分布している円錐状の成長島13A
が1×1011〔cm-2〕の密度で形成される。
According to this, the diameter D of the bottom surface is 20 [n
m] to about 25 [nm], and the height H is 3 [nm].
Conical growth islands 13A distributed to about 5 [nm]
Are formed at a density of 1 × 10 11 [cm −2 ].

【0040】図2(A)参照 2−(1) Asのみを照射した状態で、同一温度、即ち、510
〔℃〕を維持した状態で30〔秒〕間放置する。
2 (A) 2- (1) In the state where only As is irradiated, the same temperature, that is, 510
It is left for 30 [seconds] while maintaining [° C].

【0041】2−(2) MBE法を適用することに依り、厚さが例えば2〔n
m〕であるGaAsからなる第1オーバ・グロース層1
4を形成する。
2- (2) The thickness is, for example, 2 [n] by applying the MBE method.
m], the first overgrowth layer 1 made of GaAs
4 is formed.

【0042】成長島13Aの高さHには、ばらつきが在
るので、その頂部は第1オーバ・グロース層14から突
出するものがあり、また、その突出した部分の高さにつ
いてもばらつきが在る。
Since the height H of the growth island 13A varies, the top of the growth island 13A protrudes from the first overgrowth layer 14, and the height of the protruding portion also varies. You.

【0043】図2(B)参照 2−(3) Asのみを照射した状態で、同一温度、即ち、510
〔℃〕を維持した状態で3〔分〕間放置する。尚、この
際に適用する温度は、第1オーバ・グロース層14がダ
メージを受けないように選択しなければならない。
2 (B) 2- (3) In the state where only As was irradiated, the same temperature, that is, 510
Leave for 3 minutes while maintaining [° C]. The temperature applied at this time must be selected so that the first overgrowth layer 14 is not damaged.

【0044】これに依って、第1オーバ・グロース層1
4から突出している成長島13Aに於ける頂部が再蒸発
されたり、或いは、横方向に拡がって平坦化され、成長
島13Aの高さHは均一化され、第1オーバ・グロース
層14の厚さに略一致することになる。
Accordingly, the first overgrowth layer 1
The top of the growth island 13A protruding from the growth island 4 is re-evaporated or spread out in the lateral direction and flattened, the height H of the growth island 13A is made uniform, and the thickness of the first overgrowth layer 14 is increased. It will be almost the same.

【0045】また、GaAsからなる第1オーバ・グロ
ース層14とInAs層13或いは成長島13Aとの間
の歪みに依る効果で成長島13Aの移動を生じて等間隔
化、即ち、配列が起こる。尚、記号15で指示した部分
はInAs層13から供給されるInAsで構成された
二次元の成長島である。
The movement of the growth islands 13A is caused by the effect of the strain between the first over-growth layer 14 made of GaAs and the InAs layer 13 or the growth islands 13A, so that an equal spacing, that is, an arrangement occurs. The portion indicated by the symbol 15 is a two-dimensional growth island composed of InAs supplied from the InAs layer 13.

【0046】図3参照 3−(1) MBE法を適用することに依り、GaAsからなる第2
オーバ・グロース層16を形成して成長島13Aを完全
に覆う。
Referring to FIG. 3, 3- (1) the second GaAs layer is formed by applying the MBE method.
An overgrowth layer 16 is formed to completely cover the growth island 13A.

【0047】前記のようにして作製した成長島13Aに
於けるPL半値幅は、従来の技術に依存した成長島に比
較し、1/2〜1/3程度に小さくなっているので、サ
イズの均一化が起こっていることを確認できる。
Since the PL half-width of the grown island 13A manufactured as described above is reduced to about 1/2 to 1/3 as compared with the grown island depending on the conventional technique, It can be confirmed that homogenization has occurred.

【0048】本発明では、前記説明した実施の形態に限
られることなく、他に多くの改変を実現することができ
る。
In the present invention, without being limited to the above-described embodiment, many other modifications can be realized.

【0049】例えば、下地結晶及び第1オーバ・グロー
ス層の主組成としては、GaAsの他にAlGaAs、
InGaPを用いることができ、その場合、成長島の主
組成としては、InAsの他にInP、GaSb、In
Sb、或いは、それ等の混合物を用いることができる。
For example, as the main composition of the base crystal and the first overgrowth layer, in addition to GaAs, AlGaAs,
InGaP can be used. In this case, the main composition of the growth island is InP, GaSb, In, in addition to InAs.
Sb or a mixture thereof can be used.

【0050】また、このような材料の選択は、他の材料
系に於いても可能であり、下地結晶及び第1オーバ・グ
ロース層の主組成をSiとし、成長島の主組成をSiG
e、Geなどを用いることができる。
The selection of such a material is also possible in other material systems. The main composition of the underlying crystal and the first overgrowth layer is Si, and the main composition of the growth island is SiG.
e, Ge, etc. can be used.

【0051】[0051]

【発明の効果】本発明に依る半導体量子ドット及びその
製造方法に於いては、歪み系ヘテロ結晶を成長させる初
期に生成され且つ高さが全面を覆う第1オーバ・グロー
ス層の厚さに合わせて均一化されたS−K型成長島を形
成する。
According to the semiconductor quantum dot and the method for manufacturing the same according to the present invention, the height is adjusted to the thickness of the first overgrowth layer which is formed at the initial stage of growing the strained heterocrystal and has a height covering the entire surface. To form a uniform SK type growth island.

【0052】前記構成を採ることに依り、S−K型成長
島からなる半導体量子ドットの配置を制御でき、ダメー
ジがない半導体量子ドットを均一サイズで均一な密度で
生成させることが可能となり、量子ドットを複数個連結
(配列)したデバイス、例えば単電子素子を実現した
り、しきい値電流が小さく、温度特性に優れた半導体レ
ーザなどを実現することができる。
By adopting the above configuration, the arrangement of semiconductor quantum dots composed of SK type growth islands can be controlled, and semiconductor quantum dots without damage can be generated at a uniform size and a uniform density. A device in which a plurality of dots are connected (arranged), for example, a single-electron element, or a semiconductor laser with a small threshold current and excellent temperature characteristics can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】方法の発明に関する実施の形態を説明する為の
工程要所に於ける半導体量子ドットを表す要部切断側面
図である。
FIG. 1 is a fragmentary side view showing a semiconductor quantum dot at a key point in a process for describing an embodiment of a method invention.

【図2】方法の発明に関する実施の形態を説明する為の
工程要所に於ける半導体量子ドットを表す要部切断側面
図である。
FIG. 2 is a fragmentary side view showing a semiconductor quantum dot at a key point in a process for describing an embodiment of a method invention;

【図3】方法の発明に関する実施の形態を説明する為の
工程要所に於ける半導体量子ドットを表す要部切断側面
図である。
FIG. 3 is a cutaway side view showing a main part of a semiconductor quantum dot at a main point of a process for describing an embodiment of a method invention.

【図4】S−K型成長島の高さについて説明する為の半
導体量子ドットの要部説明図である。
FIG. 4 is an explanatory view of a main part of a semiconductor quantum dot for explaining the height of an SK type growth island.

【符号の説明】[Explanation of symbols]

11:GaAs基板 12:GaAs層 13:InAs層 13A:成長島 14:第1オーバ・グロース層 15:二次元の成長島 16:第2オーバ・グロース層 11: GaAs substrate 12: GaAs layer 13: InAs layer 13A: growth island 14: first overgrowth layer 15: two-dimensional growth island 16: second overgrowth layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】歪み系ヘテロ結晶を成長させる初期に生成
され且つ高さが全面を覆う第1オーバ・グロース層の厚
さに合わせて均一化されたS−K型成長島からなること
を特徴とする半導体量子ドット。
1. An SK type growth island formed at the initial stage of growing a strained heterocrystal and having a uniform height according to the thickness of a first overgrowth layer covering the entire surface. Semiconductor quantum dots.
【請求項2】第1オーバ・グロース層がS−K型成長島
の構成材料に比較して蒸気圧が低い構成材料からなるこ
とを特徴とする請求項1記載の半導体量子ドット。
2. The semiconductor quantum dot according to claim 1, wherein the first overgrowth layer is made of a constituent material having a lower vapor pressure than a constituent material of the SK type growth island.
【請求項3】歪み系ヘテロ結晶を成長させる初期に生成
されるS−K型成長島を形成する工程と、 該S−K型成長島の構成材料とは異なる材料からなり且
つ厚さが該S−K型成長島の高さ以下である第1オーバ
・グロース層を形成する工程と、 熱処理を施して該S−K型成長島の頂部を蒸発若しくは
横方向に展延して高さを該第1オーバ・グロース層の表
面に合わせる工程とが含まれてなることを特徴とする半
導体量子ドットの製造方法。
3. A step of forming an SK-type growth island generated at the initial stage of growing a strain-based heterocrystal, and comprising a material different from a constituent material of the SK-type growth island and having a thickness of the SK-type growth island. Forming a first overgrowth layer having a height equal to or less than the height of the SK type growth island; and performing heat treatment to evaporate or spread the top of the SK type growth island in the lateral direction to increase the height. Adjusting the surface of the first overgrowth layer to the surface of the first overgrowth layer.
JP9756997A 1997-04-15 1997-04-15 Manufacturing method of semiconductor quantum dots Expired - Lifetime JP4066002B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9756997A JP4066002B2 (en) 1997-04-15 1997-04-15 Manufacturing method of semiconductor quantum dots

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9756997A JP4066002B2 (en) 1997-04-15 1997-04-15 Manufacturing method of semiconductor quantum dots

Publications (2)

Publication Number Publication Date
JPH10289996A true JPH10289996A (en) 1998-10-27
JP4066002B2 JP4066002B2 (en) 2008-03-26

Family

ID=14195877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9756997A Expired - Lifetime JP4066002B2 (en) 1997-04-15 1997-04-15 Manufacturing method of semiconductor quantum dots

Country Status (1)

Country Link
JP (1) JP4066002B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242326B1 (en) * 1998-12-02 2001-06-05 Electronics And Telecommunications Research Institute Method for fabricating compound semiconductor substrate having quantum dot array structure
WO2002090625A1 (en) * 2001-05-08 2002-11-14 Btg International Limited A method to produce germanium layers
KR100599357B1 (en) 2005-01-12 2006-07-12 한국과학기술연구원 Method for fabricating semiconductor device having quantum dot structure
JP2007208241A (en) * 2005-12-27 2007-08-16 Commiss Energ Atom Method for preparing nano-level systematic structure
US7294202B2 (en) 2004-08-09 2007-11-13 National Chiao Tung University Process for manufacturing self-assembled nanoparticles
JP2008198677A (en) * 2007-02-09 2008-08-28 Fujitsu Ltd Manufacturing method of semiconductor device
JP2009231601A (en) * 2008-03-24 2009-10-08 Pioneer Electronic Corp Forming method of quantum dot
JP2011129733A (en) * 2009-12-18 2011-06-30 Nec Corp Quantum dot structure manufacturing method and quantum dot structure
US20120119188A1 (en) * 2009-07-24 2012-05-17 Pioneer Corporation Semiconductor apparatus manufacturing method and semiconductor apparatus
JP2012099698A (en) * 2010-11-04 2012-05-24 Fujitsu Ltd Optical semiconductor element, and method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242326B1 (en) * 1998-12-02 2001-06-05 Electronics And Telecommunications Research Institute Method for fabricating compound semiconductor substrate having quantum dot array structure
WO2002090625A1 (en) * 2001-05-08 2002-11-14 Btg International Limited A method to produce germanium layers
US6958254B2 (en) 2001-05-08 2005-10-25 Btg International Limited Method to produce germanium layers
US7294202B2 (en) 2004-08-09 2007-11-13 National Chiao Tung University Process for manufacturing self-assembled nanoparticles
KR100599357B1 (en) 2005-01-12 2006-07-12 한국과학기술연구원 Method for fabricating semiconductor device having quantum dot structure
JP2007208241A (en) * 2005-12-27 2007-08-16 Commiss Energ Atom Method for preparing nano-level systematic structure
JP2008198677A (en) * 2007-02-09 2008-08-28 Fujitsu Ltd Manufacturing method of semiconductor device
JP2009231601A (en) * 2008-03-24 2009-10-08 Pioneer Electronic Corp Forming method of quantum dot
US20120119188A1 (en) * 2009-07-24 2012-05-17 Pioneer Corporation Semiconductor apparatus manufacturing method and semiconductor apparatus
JP2011129733A (en) * 2009-12-18 2011-06-30 Nec Corp Quantum dot structure manufacturing method and quantum dot structure
JP2012099698A (en) * 2010-11-04 2012-05-24 Fujitsu Ltd Optical semiconductor element, and method of manufacturing the same

Also Published As

Publication number Publication date
JP4066002B2 (en) 2008-03-26

Similar Documents

Publication Publication Date Title
JP4066002B2 (en) Manufacturing method of semiconductor quantum dots
JP2000196193A (en) Semiconductor device and its manufacture
JP4651759B2 (en) Device with quantum dots
JP3045115B2 (en) Method for manufacturing optical semiconductor device
JP2757258B2 (en) Superlattice element manufacturing method
KR100331687B1 (en) fabrication method of semiconductor device for growth of self-aligned array of self-assembled quantum dots and current blocking structure
JP2762800B2 (en) Manufacturing method of quantum wire structure
JP2006114612A (en) Optical semiconductor device
JP2003309331A (en) Semiconductor device
JPH05175118A (en) Method for creating compound semiconductor having quantum fine line or quantum box structure
JP2504849B2 (en) Semiconductor quantum box structure and manufacturing method thereof
JPH09283737A (en) Quantum dot array structure
JP2794506B2 (en) Compound semiconductor heteroepitaxial growth method
JP2000183327A (en) Formation of quantum dots, quantum dot structure formed thereby and semiconductor quantum dot laser
JPH05343801A (en) Manufacture of multiwavelength laser
JP2650770B2 (en) Manufacturing method of vertical superlattice element
JPH04306821A (en) Compound semiconductor crystal growth method
JP2004281954A (en) Method of manufacturing quantum dot
JPH11111618A (en) Manufacture of semiconductor quantum dot structure
JP2000124441A (en) Preparation of semiconductor quantum dot
JPH11126945A (en) Manufacture of strained semiconductor crystal and manufacture of semiconductor laser using it
JP5493124B2 (en) Quantum dot structure manufacturing method
JPS62108592A (en) Manufacture of semiconductor
JPH06151881A (en) Manufacture of quantum effect device
JPH0228387A (en) Manufacture of quantum fine line structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070130

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070330

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070612

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070806

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071120

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071219

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110118

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110118

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120118

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130118

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130118

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140118

Year of fee payment: 6

EXPY Cancellation because of completion of term