JP2000124441A - Preparation of semiconductor quantum dot - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow carrier to pass through a quantum dot part normally by preparing a quantum dot structure by self organization growth of crystal, annealing it and making a quantum well disappear. SOLUTION: An n-type GaAs layer 12 and a non-doped GaAs layer 13 are formed on a GaAs board 11 and etched by using SiO2 14 as a mask, a bottom of a TSR groove 15 is formed to almost a circumscribed equilateral triangle to a circular opening part formed in a mask, and a depth of a groove is the size of an opening part and is almost accurately regulated. When a non-doped GaAs layer 16 and a non-doped InGaAs layer 17 and a non-doped GaAs layer 18 are formed one by one, a quantum dot 19 is formed in a tip part of the TSR groove 15, a quantum well 20 is formed in a 111} A surface, and a quantum well (quantum fine line) is formed along a ridge. Therefore, since a quantum well 20, etc., which are incidental to a quantum dot 19 are made to disappear by annealing treatment, characteristic of a quantum dot itself can be obtained when a voltage is applied between electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor quantum dot device, and more particularly to a method for forming a pure quantum dot used in a single electron device (SET) or a quantum dot semiconductor laser. And a method for manufacturing a semiconductor quantum dot device characterized by the following.

[0002]

2. Description of the Related Art With the progress of semiconductor processes in recent years, nanoscale growth technology and microfabrication technology have been used for manufacturing semiconductor devices. In addition to the improvement in the degree of integration, a semiconductor device utilizing the wave nature of electrons, that is, a so-called quantum mechanical effect, for example, a strained quantum well semiconductor laser has been put to practical use.

In a semiconductor device utilizing such a quantum mechanical effect, for example, a one-dimensional quantum well structure semiconductor laser, an oscillation threshold value caused by heat generated due to the movement of many electrons and a threshold value It has been pointed out that there is a limit to the improvement of the temperature characteristics of the semiconductor device. One of the methods for solving this problem is a three-dimensional confined quantum well structure in which carriers such as electrons and holes are confined in a narrow region from three directions. The adoption of a structure called a quantum box (QB: Quantum Box) or a quantum dot (QD: Quantum Dot) has been proposed.

The quantum dot is a box of potential that is extremely fine enough to give the carrier three-dimensional quantum confinement. In this quantum dot, the state function density of the carrier is discretized as a delta function, and its ground level is obtained. Can have only two carriers, for example, only two electrons in the conduction band, and the excited level can have a plurality of electrons depending on the order of the level. .

The small size of the quantum dot at the atomic level pushes the miniaturization of electronic devices to the utmost, and the quantum mechanical effect unique to the quantum dot realized there can promote the development of a new functional element. For example, by using quantum dots as the active region of a semiconductor laser, there is a merit that the interaction between electrons / holes and light can be made as efficient as possible. Attention is drawn from the application point of view.

Various techniques have been proposed for fabricating such a semiconductor quantum dot structure. Among them, there is a method using so-called self-organized growth in crystal growth.
In this case, since fine processing techniques such as exposure and etching are not required, high quality quantum dots can be obtained without mechanical damage to crystals due to the fine processing.

[0007] Here, with reference to FIGS. 11 to 13, some of the methods of manufacturing quantum dots using so-called self-assembled growth will be described. First, referring to FIG. 11, a tetrahedral groove (TSR: Tetrahedral-Shaped) which is a quantum dot formed at the tip of a groove provided in a semiconductor substrate.
(Recesses) A semiconductor quantum dot device using dots will be described (see Japanese Patent Application Nos. 7-49534 and 7-61339 if necessary). Note that FIG.
FIG. 11A is a schematic plan view of a semiconductor quantum dot using a TSR dot, and FIG. 11B is a cross-sectional view taken along a dashed-dotted line connecting aa ′ in FIG.

Referring to FIGS. 11 (a) and 11 (b), first, GaAs having a zinc blende type crystal structure having a (111) B main surface.
An inverted regular triangular pyramid surrounded by three equivalent {111} A planes by providing an SiO ₂ mask 62 on a substrate 61 and performing anisotropic etching using a Br ₂ methanol solution or the like, that is, a regular tetrahedron A TSR groove 63 is formed, and the size of the groove is defined by the size of the opening of the SiO ₂ mask 62. The inclination angle of the side wall surface composed of the three {111} A surfaces of the TSR groove 63 with respect to the (111) B surface is about 7
The angle is 0.5 °, and the ridgeline shows a crystal state close to the {100} plane, and the inclination angle of the ridgeline with respect to the (111) A plane is about 54.7 °.

Next, a 30 ° thick AlAs layer 64 serving as a barrier layer, a 50 ° thick GaAs layer 65 serving as a well layer and a 50 ° thick GaAs layer 65 are formed in the TSR trench 63 by a reduced pressure MOVPE method using the SiO ₂ mask 62 as a growth inhibiting mask. By growing the AlAs layer 66 having a thickness of 30 ° as a barrier layer, the quantum dots 67 are self-organized at the apex of the TSR groove 63, and the quantum dots 67 are formed along the side walls of the {111} A plane. A well 68 is formed. In the region along the ridge, a quantum wire is formed.

In the case where the device is used as an actual semiconductor quantum dot device, an n ⁺ -type GaAs epitaxial layer and an n-type GaAs layer are grown on a GaAs substrate.
TS reaching n ⁺ -type GaAs layer using SiO ₂ mask
In addition to forming the R groove 63, an n-type GaAs layer and an n ⁺ -type GaAs
A contact layer is grown, and finally an electrode for applying a voltage is an n ⁺ -type GaAs epitaxial layer and an n ⁺ -type Ga
It is provided on the As contact layer.

Next, a semiconductor quantum dot device using an inverted square pyramid groove will be described with reference to FIG.
The above-mentioned Japanese Patent Application No. 7-61339). FIG.
12A is a schematic plan view of a semiconductor quantum dot using an inverted square pyramid groove, and FIG. 12B is a cross-sectional view taken along a dashed-dotted line connecting aa ′ in FIG. is there.

Referring to FIGS. 12 (a) and 12 (b), first, an n-type silicon layer 71 having a (100) main surface is etched.
SiO serving both as a etching mask and a selective growth mask_Twotrout
72, and ethylenediamine [NH_Two(CH _Two)_TwoNH
_Two]: Pyrocatechol [C₆H_Four(OH)_Two]: H_TwoO = 4
6.4 mol%: 4 mol%: 49.6 mol% in water
Etching at about 100 ° C using liquid
The inverse normal four surrounded by four equivalent {111} planes
A pyramidal groove 73 is formed. In addition, this inverted square pyramid groove 73
It corresponds to the (100) plane of the side wall composed of four {111} planes.
The angle of inclination is about 54.74 ° and the size of the groove
-Depth is SiO as an etching mask_TwoMask 72
Is determined by the size of the opening.

Next, low pressure chemical vapor deposition (LPCVD)
Thickness), which has a larger forbidden band width than silicon.
After epitaxially growing a SiC barrier layer 74, a silicon well layer 75 having a thickness of 50 mm, and a SiC barrier layer 76 having a thickness of 20 mm, an n-type silicon layer and an n ⁺ -type silicon contact layer (not shown) are grown. By embedding the remaining portion of the inverted square pyramid groove 73 and finally providing an electrode for applying a voltage, a quantum dot 77 is formed at the tip of the inverted square pyramid groove 73, and four equivalent ｛11
A quantum well 78 is formed along the side wall surface composed of the 1 ° plane. In this case as well, a quantum wire is formed in a region along the ridge line.

Next, with reference to FIG.
A process of forming quantum dots in the nski-Krastanov mode will be described. Referring to FIG. 13A, first, TEGa (triethylgallium) and AsH ₃ are supplied on a GaAs substrate (not shown) by MOVPE (metal organic chemical vapor deposition) to have a thickness of 500 nm (= 0.5 μm) GaAs buffer layer 81
After forming the substrate, the substrate temperature is set to 500 ° C., and A
When an As raw material 82 such as sH ₃ , an In raw material 83 such as TMIn (trimethylindium), and a Ga raw material 84 such as TMGa (trimethylgallium) are simultaneously supplied, the growth of the InGaAs growth layer at the beginning of the growth is based on the lattice mismatch. Since the limit is not exceeded, growth is performed two-dimensionally and InGa
An As wetting layer 85 is grown.

Referring to FIG. 13B, when the growth is continued, when the thickness of the InGaAs wetting layer 85 exceeds the elastic limit, the angstrom order as a growth nucleus for forming quantum dots on the surface of the InGaAs wetting layer 85 is obtained. Are formed discretely.

Further, as shown in FIG. 13C, when the growth is continued, the three-dimensional nucleus 86 is used as a growth nucleus and the In composition ratio is relatively large in the order of nanometers.
The nGaAs quantum dots 87 are formed, and the peripheral portion of the InGaAs quantum dots 87 has an In composition ratio of relatively small I.
It becomes the nGaAs wetting layer 88.

This is because when the thickness of the InGaAs wetting layer 85 exceeds the elastic limit, the In composition ratio is relatively large.
It is considered that the local generation of the nGaAs quantum dots 87 lowers the strain energy of the whole InGaAs growth layer as compared with the case where the strain is generated on the entire surface of the InGaAs growth layer, resulting in crystallographically stable growth.

This Transki-Krastano
Self-forming method by v-mode (for example, Japanese Patent Application No. 7-21)
No. 7466) is the most commonly used method because it is easy to manufacture. In this method, a high number density, for example, a number density of up to about 40% by area ratio is realized. Therefore, this is a preferable manufacturing method for manufacturing a quantum dot laser.

[0019]

However, in a conventional semiconductor quantum dot device by self-organization, a one-dimensional confined quantum well or a two-dimensional confined quantum well (quantum wire) is inevitably attached to the quantum dot. In some cases, these quantum well portions have a problem in that they hinder obtaining the inherent characteristics of the semiconductor quantum dot device.

That is, in the case of a semiconductor quantum dot device using a TSR groove or an inverted square pyramid groove, a side wall surface becomes a one-dimensional confined quantum well, and a ridge line is formed with a two-dimensional confined quantum well (quantum fine wire). Therefore, when a voltage is applied between the contact layer in which the TSR groove or the inverted regular pyramid groove is buried and the substrate or the high impurity concentration layer provided on the substrate, carriers are one-dimensional confined in addition to the quantum dot portion. It may flow through the quantum well portion or the two-dimensional confined quantum well portion, and the characteristics in the one-dimensional confined quantum well portion or the two-dimensional confined quantum well portion may affect the characteristics of the semiconductor quantum dot device. There's a problem.

Also, Transki-Krastan
In a semiconductor quantum dot device manufactured by an ov mode self-assembly method, when a wetting layer around a quantum dot becomes a one-dimensional confined quantum well and a current flows between the substrate and the contact layer, this recombination occur in wetting layer, it becomes a loss of carrier, there is a problem that light emission at a wavelength which does not essentially contribute to the laser oscillation occurs, will result in an increase in the threshold current I _th.

Accordingly, an object of the present invention is to provide a means for allowing a carrier to normally pass through a quantum dot portion.

[0023]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. FIG.
1A is a plan view of a semiconductor quantum dot using a tetrahedral groove (TSR groove), and FIG. 1B is a plan view of FIG.
FIG. 3 is a cross-sectional view taken along a dashed line connecting aa ′ in FIG. See FIG. 1. (1) In the present invention, in a method for manufacturing a semiconductor quantum dot device, a quantum dot 7 structure in which carriers are three-dimensionally confined in a narrow region is manufactured by self-organized growth of crystal, and then annealed. The quantum well associated with the quantum dot 7 is eliminated.

As described above, after the quantum dots 7 are produced by self-assembly growth, annealing is performed to eliminate the quantum wells associated with the quantum dots 7.
Only the characteristics of the quantum dots 7 can be obtained. In the specification of the present application, “a quantum dot manufactured by self-assembly growth” refers to a quantum dot 7 manufactured by a manufacturing method that does not involve a fine etching process that affects the shape of the quantum dot 7 in a process after crystal growth. 11 typically means the manufacturing method described with reference to FIGS.

(2) The present invention is characterized in that, in the above (1), in the annealing step, annealing is performed with a thermal protection film provided on the quantum dots 7.

As described above, in order to selectively eliminate the quantum wells associated with the quantum dots 7, it is desirable to anneal with a thermal protection film such as AlN provided so as to cover the quantum dots 7. By providing a thermal protection film,
Thermal diffusion of constituent atoms in the quantum dots 7 is suppressed, and only the quantum wells associated with the quantum dots 7 can be effectively eliminated.

(3) The present invention is characterized in that in the above (1) or (2), the quantum dots 7 are quantum dots 7 formed in grooves formed in the substrate 1. .

As described above, by forming grooves in the substrate 1 for self-assembled growth, the position and number of the quantum dots 7 can be arbitrarily controlled. This is a configuration suitable for a semiconductor quantum dot device.
The “substrate” in this case is a crystal growth substrate, and
It means an epitaxial layer grown on a crystal growth substrate.

(4) The present invention is characterized in that, in the above (3), the groove formed on the substrate 1 is a regular tetrahedral groove 3.

As described above, by appropriately selecting the crystal plane orientation and the etching solution, the regular tetrahedral groove 3 can be set at a predetermined position according to the position and size of the opening provided in the mask 2.
And it can be formed in a predetermined size with good reproducibility,
In particular, this is typical for III-V compound semiconductors such as GaAs.

(5) The present invention is characterized in that in (3), the groove formed in the substrate 1 is an inverted square pyramid groove.

As described above, by appropriately selecting the crystal plane orientation and the etching solution, the inverted square pyramid groove can be set at a predetermined position depending on the position and size of the opening provided in the mask 2.
And it can be formed in a predetermined size with good reproducibility,
In particular, this is typical for a group IV semiconductor such as Si.

(6) Further, the present invention is characterized in that, in the above (1) or (2), the quantum dots 7 are quantum dots that are self-organized and grown in a Stranky-Clusteroff mode.

As described above, as a self-organizing growth method, a Stransky-Kranov is used.
By using a self-forming mode of the stanov mode, quantum dots can be manufactured at a high density, and a structure suitable for an optical semiconductor device such as a quantum dot laser can be obtained.

(7) The present invention is characterized in that in the above (4) or (6), the quantum dots 7 are made of a III-V compound semiconductor.

(8) The present invention is characterized in that, in the above (7), the annealing is performed in an atmosphere containing a group V element constituting the quantum dots 7.

As described above, when the quantum dots 7 are made of a group III-V compound semiconductor, the annealing can be performed in an atmosphere containing a group V element having a high vapor pressure to prevent crystal roughness. it can.

(9) The present invention is characterized in that in the above (5) or (6), the quantum dots 7 are made of a group IV semiconductor.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, a first embodiment of the present invention will be described with reference to FIGS. Note that FIG.
FIG. 2A is a cross-sectional view taken along a dashed line connecting aa ′ in FIG. Referring to FIGS. 2A and 2B, first, MOVPE is formed on a GaAs substrate 11 having a main surface of a (111) B surface.
Method (organic metal vapor phase epitaxy), TM
By using Ga and AsH ₃ , using SiH ₄ as an impurity source, and setting the substrate temperature to, for example, 600 ° C., the thickness is, for example, 130 nm, and the impurity concentration is, for example, 1 × 10 ¹⁸ cm ^−3. After the n-type GaAs layer 12 is grown, a non-doped GaAs layer 13 having a thickness of, for example, 1.35 μm is sequentially grown thereon.

Next, an SiO ₂ film having a thickness of 100 nm is deposited on the non-doped GaAs layer 13 by using a CVD method, and a diameter of 1 μm is formed by using a usual photolithography technique.
An SiO ₂ mask 14 having an m-shaped circular opening is formed.

Next, anisotropic wet etching using a 1% Br ₂ ethanol solution is performed using the SiO ₂ mask 14 as an etching mask, thereby forming a square face surrounded by three equivalent {111} A planes. body-shaped grooves, i.e., TSR groove 15, its bottom surface is formed so as to constitute a substantially circumscribing an equilateral triangle with respect to the circular opening formed in the SiO ₂ mask 14, the depth of the groove, SiO ₂ Mask 14
The size of the opening formed in the hole is almost exactly defined. Although only one TSR groove 15 is shown in the drawing, when a plurality of TSR grooves 15 are formed at the same time, the direction of the {111} A plane with respect to the (111) B plane is determined. The TSR grooves 15 will be aligned in the same direction.

The three side wall surfaces of the TSR groove 15 are # 11
1｝ A surface, the inclination angle to the (111) B surface is about 70.5 °, and the ridge line is
It shows a crystalline state close to the 0 ° plane, and the (111)
The inclination angle with respect to the plane B is about 54.7 °.

The reason why such a TSR groove 15 is formed is that Br for GaAs having a zinc blende type crystal structure is formed.
₍₂₎ The etching rate of the {111} A surface of the ethanol solution is much smaller than the etching speed of the other surface, and the {111} A surface is formed around the circular opening formed in the SiO ₂ mask 14. If this occurs, the etching does not proceed any further, so it is considered that the bottom surface of the TSR groove 15 forms a circumscribed equilateral triangle with the circular opening.

Referring to FIG. 3C, again, in the MOVPE apparatus, with the SiO ₂ mask 14 remaining, TMGa and
Using TMIn and AsH ₃ at a substrate temperature of, for example, 600 ° C., a non-doped GaAs layer 16 having a thickness of, for example, 5 nm, and a thickness of, for example, 10 n
a non-doped InGaAs layer 17 serving as a m-well layer;
And a non-magnetic layer having a thickness of, for example, 5 nm.
A doped GaAs layer 18 is sequentially grown.

In this case, quantum dots 19 are formed at the apex of the TSR groove 15, and the # 1
A one-dimensional confinement quantum well 20 is formed on the 11 ° A plane, and a two-dimensional confinement quantum well (quantum fine wire) (not shown) is formed along the ridge. In this case, the thickness of each layer is the thickness on the {111} A plane and (11
1) The thickness of the plane B is three times the thickness of the plane {111} A.

Next, at 800 ° C. in an AsH ₃ gas atmosphere, as shown in FIG.
Annealing treatment is performed until the diffusion length of In becomes 3 nm to diffuse In forming the non-doped InGaAs layer 17 in the solid phase, thereby forming the quantum well 20 and the ridge formed on the side wall surface of the TSR groove 15. The quantum well that has been lost is eliminated to form a quantum well eliminated portion 22. In the above-described annealing step, the quantum dots 19 formed at the apex of the TSR groove 15 are relatively thick, so that they are slightly deformed but remain as the quantum dots 21.

4 (a) and 4 (b). FIG. 4 (a) shows cc 'of FIG. 3 (c) before annealing.
FIG. 4B is a diagram showing a potential distribution along a dash-dot line connecting cc 'in FIG. 3D after annealing, and FIG. 4B is a diagram showing a potential distribution along a dash-dot line connecting annealing. Yes, as is clear from FIG. 4B, the shape of the quantum dots is maintained even after the annealing process,
It is held as quantum dots 21 as shown in FIG.
In the figure, in order to make it easy to understand the deformation of the quantum dots, a non-doped GaAs layer 1 serving as a barrier layer is used.
6, 18 are shown as InGaAs layers on both sides.
The potential of aAs is set to 1, and the potential of InGaAs having a composition constituting a quantum dot is set to 0.

5 (a) and 5 (b). FIG. 5 (a) shows bb 'of FIG. 3 (c) before annealing.
FIG. 5B is a diagram showing a potential distribution along a dashed line connecting bb 'in FIG. 3D after annealing, and FIG. 5B is a diagram showing a potential distribution along a dashed line connecting the dashed line. is there. In this case also, in order to make it easy to understand the deformation of the quantum dots, the non-doped G
Both sides of the aAs layers 16 and 18 are shown as InGaAs layers, and the potential of GaAs is set to 1, and the potential of InGaAs of the composition constituting the quantum dot is set to 0.

In this quantum well 20, FIG.
As is clear from FIG. 5, since the thickness of the well layer is about 5 nm and the potential thereof is higher than that of InGaAs constituting the quantum dots 19, that is, the In composition ratio is smaller, and therefore, as shown in FIG. After the annealing process is performed for a time in which diffusion of 3 nm occurs, the quantum well 20 completely disappears, and becomes a quantum well disappearing portion 22 as shown in FIG.

Next, although not shown, the MOV
Using the PE method, an n-type GaAs layer and an n ⁺ -type InGaAs
An s-contact layer is sequentially grown to fill the TSR trench 15 and finally, electrodes are provided for the n ⁺ -type InGaAs contact layer and the n-type GaAs layer 12, thereby completing the basic structure of the semiconductor quantum dot device.

As described above, in the first embodiment of the present invention, the quantum dots 19 are formed by self-organizing growth using the TSR grooves 15 formed by anisotropic etching, and the quantum dots attached to the quantum dots 19 are formed. Since the wells 20 and the like are eliminated by the annealing treatment, the characteristics of the quantum dots themselves can be obtained when a voltage is applied between the electrodes.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6 and 7. The steps up to the annealing step for eliminating the quantum well are the same as those of the first embodiment. The illustration is partially omitted because it is the same. Referring to FIG. 6A, first, as in the first embodiment, the main surface is (11).
1) On the GaAs substrate 11 on the B side, by using MOVPE, TMGa and AsH ₃ are used as source gases, SiH ₄ is used as an impurity source, and the substrate temperature is set to, for example, 60.
By setting the temperature to 0 ° C., the thickness becomes, for example, 130 nm.
And an n-type G having an impurity concentration of, for example, 1 × 10 ¹⁸ cm ^−3.
After growing the aAs layer 12, a non-doped GaAs layer 13 having a thickness of, for example, 1.35 μm is sequentially grown thereon.

Next, an SiO ₂ film having a thickness of 100 nm is deposited on the non-doped GaAs layer 13 by using the CVD method, and the diameter of the SiO ₂ film is reduced to 1 μm by using ordinary photolithography.
After forming a SiO ₂ mask 14 having a circular opening of m, the TSR groove 15 is formed by performing anisotropic wet etching using a 1% Br ₂ ethanol solution using the SiO ₂ mask 14 as an etching mask. To form

Then, again in the MOVPE apparatus, while keeping the SiO ₂ mask 14, using TMGa, TMIn, and AsH ₃ as source gases, and setting the substrate temperature to, for example, 600 ° C., Is a non-doped GaAs layer 16 having a thickness of, for example, 5 nm, and a non-doped InGa layer having a thickness of, for example, a 10 nm well layer.
By sequentially growing an As layer 17 and a non-doped GaAs layer 18 serving as a barrier layer having a thickness of, for example, 5 nm, quantum dots 19 are formed at the apex of the TSR groove 15 and at the same time, the TSR is formed. # 1 which is the side wall surface of the groove 15
A one-dimensional confined quantum well 20 is placed on the 11｝ A plane,
A two-dimensional confined quantum well (quantum wire) along the ridge
(Not shown) is formed.

Next, as shown in FIG. 6B, an SiO ₂ film 23 having a thickness of, for example, 100 nm is deposited on the entire surface by a plasma CVD method, and then a photoresist 24 is applied, and a photolithography process and an etching process are performed. A smaller opening 25 is formed at the same pitch as the opening provided in the SiO ₂ mask 14, and an AlN film 26 serving as a thermal protection film is deposited on the entire surface using a sputter deposition method. Embed

Next, by removing the photoresist 24, as shown in FIG.
In a state where the AlN film 26 on the photoresist 24 is lifted off and the AlN film 26 is left only in the central portion of the TSR groove 15 under an AsH ₃ gas atmosphere at 800 ° C.
Annealing is performed until the diffusion length of In becomes 3 nm, so that In constituting the non-doped InGaAs layer 17 is solid-phase diffused.

Next, as shown in FIG. 7D, the AlN film 26 and the SiO ₂ film 23 are selectively removed, so that the quantum dots 21 remain at the apex of the TSR groove 15 and the side wall surface of the TSR groove 15 is formed. The quantum well 20 formed on the ridge line and the quantum well (quantum fine wire) formed on the ridge line disappear and become the quantum well disappearing portion 22.

This is because, in the above annealing step, S
Since the iO ₂ film 23 and O ₂ constituting the SiO ₂ mask 14 are easily bonded to Ga, a large amount of Ga vacancies are created in the annealing step, and as a result, diffusion of In is promoted and the sidewall surface of the TSR groove 15 is formed. Although the formed quantum well 20 and the quantum well (quantum fine wire) formed on the ridge line disappear, such a phenomenon does not occur in the AlN film 26.
At the apex of the TSR groove 15 where the AlN film 26 exists as a thermal protection film, the quantum dots 19 remain as the quantum dots 21 in a slightly deformed state.

Next, although not shown, the MOV
Using the PE method, an n-type GaAs layer and an n ⁺ -type InGaAs
An s-contact layer is sequentially grown to fill the TSR trench 15 and finally, electrodes are provided for the n ⁺ -type InGaAs contact layer and the n-type GaAs layer 12, thereby completing the basic structure of the semiconductor quantum dot device.

As described above, in the second embodiment of the present invention, the thermal protection film is provided so as to cover the quantum dots 19 in the annealing step for eliminating the quantum wells. Deformation can be minimized, thereby completely eliminating the quantum well,
The quantum dots 21 close to the design value can be formed with good reproducibility.

Next, a third embodiment of the present invention will be described with reference to FIG.
Form will be described. Referring to FIG. 8A, first, an n-type silicon layer 31 having a (100) main surface is etched.
SiO serving both as a etching mask and a selective growth mask_Twotrout
32, ethylenediamine [NH_Two(CH _Two)_TwoNH
_Two]: Pyrocatechol [C₆H_Four(OH)_Two]: H_TwoO = 4
6.4 mol%: 4 mol%: 49.6 mol% in water
Etching at about 100 ° C using liquid
The inverse normal four surrounded by four equivalent {111} planes
A pyramidal groove 33 is formed.

Next, a thickness of 20
{Si barrier layer 34}, Ge well layer 3 having a thickness of 50%
5, and by sequentially growing the Si barrier layer 36 having a thickness of 20 °, quantum dots 37 are formed at the tips of the inverted square pyramid grooves 33, and the inverted square pyramid grooves 33 are formed into four equivalents forming side walls. A quantum well 38 is formed along the {111} plane, and a two-dimensional confined quantum well (quantum fine wire) (not shown) is formed along the ridge.

Next, as shown in FIG. 8B, a SiN film is deposited on the entire surface by the CVD method, and is selectively removed to thereby form the quantum dots 37.
Annealing is performed while leaving a SiN film mask (not shown) serving as a thermal protection film only above the silicon substrate, thereby causing Ge and Si to diffuse in a solid phase, thereby forming quantum dots 37.
Using the difference in the thickness of the quantum well 38 and the inverse square pyramid groove 3
The quantum well 38 formed on the side wall surface and the quantum well (quantum fine wire) formed on the ridge are eliminated.

Next, although not shown, after removing the SiN film mask, an n-type silicon layer and an n ⁺ -type silicon contact layer are sequentially grown again to form an inverted square pyramid groove 33.
Is embedded, and finally, an electrode for applying a voltage is provided, thereby completing the basic configuration of the semiconductor quantum dot device.

In the case of the third embodiment, since an inexpensive silicon substrate is used, a semiconductor quantum dot device can be manufactured at a lower cost than in the first embodiment.

Next, referring to FIG. 9, a Transki-Krastanov according to a fourth embodiment of the present invention will be described.
A manufacturing process of a semiconductor quantum dot device using mode self-assembly growth will be described. It should be noted that only the vicinity of the quantum dot is shown for simplicity. Referring to FIG. 9A, first, as in the conventional case, the n-type GaAs is formed using the MOVPE method.
On a s substrate, an n-type GaAs buffer layer having a thickness of 500 nm, an n-type In _0.5 Ga _0.5 P cladding layer having a thickness of 1000 nm (both not shown), and an n-type GaAs buffer layer having a thickness of 100 nm
A GaAs buffer layer 41 of type GaAs is sequentially grown.

Next, by simultaneously supplying AsH ₃ , TMIn, and TMGa while keeping the substrate temperature at 500 ° C., since the InGaAs growth layer does not exceed the elastic limit based on the lattice mismatch at the beginning of the growth, 2 When the InGaAs wetting layer grows and continues to grow in a three-dimensional manner, when the thickness of the InGaAs wetting layer exceeds the elastic limit, quantum dots are formed on the surface of the InGaAs wetting layer. Angstrom-order three-dimensional nuclei serving as growth nuclei are discretely formed, and further growth is continued, so that the three-dimensional nuclei are used as growth nuclei and the In composition ratio in the nanometer order is relatively large.
s quantum dots 42 are formed, and the periphery of the InGaAs quantum dots 42 is InGaAs having a relatively small In composition ratio.
The s wetting layer 43 is formed.

Next, GaAs having a thickness of 100 nm was again formed by MOVPE while keeping the substrate temperature at 600 ° C.
After the s layer 44 is grown, the s layer 44 is grown under an AsH ₃ gas atmosphere.
By performing a heat treatment at a temperature of 00 ° C., In is diffused in the solid phase, whereby the InGaAs wet layer 43 constituting the one-dimensional confined quantum well disappears, and the quantum well disappearing part 46 disappears.
Becomes On the other hand, in this annealing step, InGaAs
Since the In composition ratio in the InGaAs quantum dots 42 is larger than the s wetting layer 43 and the thickness is larger, the In
The GaAs quantum dots 42 are retained as quantum dots 45 without disappearing.

Next, although not shown, the MOV
By a PE method, a p-type In _0.5 Ga having a thickness of 1000 nm is formed.
_0.5 P clad layer and 500 nm thick p-type GaAs
An s-contact layer is formed, and finally, an n-side electrode is provided on the back surface of the n-type GaAs substrate, and a p-side electrode is provided on the p-type GaAs contact layer, thereby completing the quantum dot semiconductor laser.

As described above, in the fourth embodiment of the present invention, the InG
Since the aAs wetting layer 43 is eliminated by annealing, recombination does not occur in the InGaAs wetting layer, and wasteful current consumption that does not contribute to laser oscillation is reduced. Therefore, the threshold current I _th of the quantum dot semiconductor laser is reduced. Can be reduced.

Next, referring to FIG. 10, similarly to the Transki-Kra according to the fifth embodiment of the present invention.
A manufacturing process of a semiconductor quantum dot device using the self-organizing growth in the stanov mode will be described. In order to simplify the explanation, only the manufacturing process of the quantum dots will be described. Referring to FIG. 10 (a), first, as in the conventional case, an LPCVD method using SiH ₄ is applied on a Si substrate (not shown), for example, to a thickness of 10 μm.
By sequentially growing a Si layer 51 serving as a 0 nm buffer layer and then supplying GeH ₄ , the Ge growth layer does not exceed the elastic limit based on lattice mismatch at the beginning of growth, so that growth is performed two-dimensionally. When the Ge wet layer 53 grows and continues to grow, it becomes a growth nucleus for forming quantum dots on the surface of the Ge wet layer 53 when the thickness of the Ge wet layer exceeds the elastic limit. Angstrom-order three-dimensional nuclei are discretely formed, and by continuing growth, Ge quantum dots 52 on the order of nanometers are formed with the three-dimensional nuclei as growth nuclei.

Next, the LPCV using SiH ₄ is again performed.
After a Si layer 54 having a thickness of, for example, 100 nm is grown by the D method, Si and Ge are interdiffused by heat treatment, whereby the Ge wetting layer 53 forming the one-dimensional confined quantum well is formed. It disappears and becomes the quantum dot disappearing portion 56. On the other hand, in this annealing step, the Ge quantum dots 52 thicker than the Ge wetted layer 53 are held as quantum dots 55 without disappearing.

Also in the fifth embodiment, since the Ge wet layer 53 attached to the Ge quantum dots 52 is eliminated by annealing, the characteristics of the quantum dots 55 alone can be obtained.

The embodiments of the present invention have been described above. However, the present invention is not limited to the configuration described in each embodiment, and various modifications are possible. For example, in the description of the first and second embodiments, InG
Although described as aAs / GaAs quantum dots,
The present invention is also applied to a GaAs / AlGaAs (AlAs) quantum dot or an InGaAsP / InP quantum dot.

In the above description of the third and fifth embodiments, Ge / Si quantum dots are described, but Si.Ge/Si quantum dots may be used. .

[0076]

According to the present invention, a one-dimensional confined quantum well or a two-dimensional confined quantum well (quantum wire) which is inevitably attached to a quantum dot formed by self-organizing growth is annihilated by a heat treatment step. Therefore, the characteristics of the quantum dot itself can be obtained, which greatly contributes to the practical use of a high-performance quantum dot semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through the first embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the first embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a change caused by heat treatment of a quantum dot according to the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a change caused by heat treatment of the quantum well according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process partway through a second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a manufacturing process of the second embodiment of the present invention after FIG. 6;

FIG. 8 is an explanatory diagram of a manufacturing process according to a third embodiment of the present invention.

FIG. 9 is an explanatory diagram of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram of a manufacturing process according to a fifth embodiment of the present invention.

FIG. 11 is an explanatory diagram of a quantum dot using a conventional TSR groove.

FIG. 12 is an explanatory diagram of a quantum dot using a conventional inverted square pyramid groove.

FIG. 13 shows a conventional Transki-Krastano.
It is explanatory drawing of the formation process of the semiconductor quantum dot by v mode.

[Explanation of symbols]

1 substrate 2 mask 3 tetrahedral groove 4 barrier layer 5 well layer 6 barrier layer 7 quantum dots 8 quantum well disappearance portion 11 GaAs substrate 12 n-type GaAs layer 13 non-doped GaAs layer 14 SiO ₂ mask 15 TSR groove 16 non- doped GaAs layer 17 non-doped InGaAs layer 18 non-doped GaAs layer 19 quantum dots 20 quantum wells 21 quantum dots 22 quantum well disappearance portion 23 SiO ₂ layer 24 photoresist 25 opening 26 AlN film 31 n-type silicon substrate 32 SiO ₂ Mask 33 Inverted square pyramid groove 34 Si barrier layer 35 Ge well layer 36 Si barrier layer 37 Quantum dot 38 Quantum well 39 Quantum dot 40 Quantum well disappearance part 41 GaAs buffer layer 42 InGaAs quantum dot 43 InGaAs wetting layer 44 GaAs layer 45 Child dots 46 quantum well disappear section 51 Si buffer layer 52 Ge quantum dots 53 Ge wetting layer 54 Si layer 55 quantum dots 56 quantum well disappearance portion 61 GaAs substrate 62 SiO ₂ mask 63 TSR groove 64 AlAs layer 65 GaAs layer 66 AlAs layer 67 Quantum dot 68 Quantum well 71 n-type silicon substrate 72 SiO ₂ mask 73 inverted square pyramid groove 74 SiC barrier layer 75 silicon well layer 76 SiC barrier layer 77 quantum dot 78 quantum well 81 GaAs buffer layer 82 As raw material 83 In raw material 84 Ga raw material 85 InGaAs wetting layer 86 Three-dimensional nucleus 87 InGaAs quantum dots 88 InGaAs wetting layer

Claims (9)

[Claims] 1. A quantum dot structure in which carriers are three-dimensionally confined in a narrow region is produced by self-assembled growth of a crystal, and then annealed to eliminate a quantum well attached to the quantum dot. Of manufacturing a semiconductor quantum dot device. 2. The method of manufacturing a semiconductor quantum dot device according to claim 1, wherein in the annealing step, annealing is performed with a thermal protection film provided on the quantum dots. 3. The method according to claim 1, wherein the quantum dots are quantum dots formed in grooves formed in the substrate. 4. The method according to claim 3, wherein the grooves formed on the substrate are tetrahedral grooves. 5. The method according to claim 3, wherein the groove formed on the substrate is an inverted square pyramid groove. 6. The method of manufacturing a semiconductor quantum dot device according to claim 1, wherein the quantum dots are quantum dots that are self-organized and grown in a Stranky-Clusteroff mode. 7. The method for manufacturing a semiconductor quantum dot device according to claim 4, wherein said quantum dots are made of a group III-V compound semiconductor. 8. The method according to claim 7, wherein the annealing is performed in an atmosphere containing a group V element constituting the quantum dots. 9. The method for manufacturing a semiconductor quantum dot device according to claim 5, wherein the quantum dots are made of a group IV semiconductor.