JPH10289908A - Semiconductor device and its manufacturing method and connection structure - Google Patents

Semiconductor device and its manufacturing method and connection structure

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Publication number
JPH10289908A
JPH10289908A JP9097170A JP9717097A JPH10289908A JP H10289908 A JPH10289908 A JP H10289908A JP 9097170 A JP9097170 A JP 9097170A JP 9717097 A JP9717097 A JP 9717097A JP H10289908 A JPH10289908 A JP H10289908A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
film
insulating film
peripheral portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9097170A
Other languages
Japanese (ja)
Inventor
Noboru Taguchi
昇 田口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP9097170A priority Critical patent/JPH10289908A/en
Publication of JPH10289908A publication Critical patent/JPH10289908A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
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    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
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Abstract

PROBLEM TO BE SOLVED: To avoid floating of the conductive material between a bump electrode and a circuit electrode by a method wherein, within an insulating film having an aperture part in the periphery on an electrode pad, a lower part electrode film provided on the electrode pad and a semiconductor device having a bump electrode, the central part of the crest of the bump electrode is made lower than the periphery. SOLUTION: An inorganic insulating film 17 and an organic insulating film 15 having aperture parts in an electrode pad 14 on the same plane as well as a lower part electrode 19 connecting to the electrode pad 14 and a protruding electrode 22 connecting to the lower part electrode 19 are provided on a semiconductor substrate 12. Furthermore, the plane shape of the bump electrode 22 is made larger than the aperture dimensions of the inorganic insulating film 17 and the organic insulating film as well as the central part of the crest of the bump electrode 22 is composed lower than the periphery. At this time, the periphery of the crest of the protruding electrode 22 is composed higher than the central part. In such a constitution, the floating conductive material 32 between the bump electrode 22 and the circuit electrode 28 on a circuit substrate 26 together with an anisotropical conductive adhesive 34 from connecting surface in the case of connection pressurization can be avoided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置を回路
基板に電気的および機械的な接続を行う突起電極の構造
およびその製造方法に関し、さらにこの突起電極を用い
た回路基板への接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a protruding electrode for electrically and mechanically connecting a semiconductor device to a circuit board and a method of manufacturing the same, and further relates to a connection structure to the circuit board using the protruding electrode. .

【０００２】[0002]

【従来の技術】従来の技術におけるストレートウォール
形状の突起電極の構造と、この構造を形成するための製
造方法を、図１１〜図１５の断面図をもちいて説明す
る。2. Description of the Related Art The structure of a conventional straight-wall-shaped projecting electrode and a manufacturing method for forming this structure will be described with reference to the sectional views of FIGS.

【０００３】〔突起電極構造：図１５〕はじめに図１５
をもちいて従来技術の突起電極構造を説明する。図１５
にしめすように、半導体基板１２上に電極パッド１４を
開口するように絶縁膜１６を形成し、その全面に共通電
極膜を形成する。さらに、突起電極２２をストレートウ
ォール形状に形成し、共通電極膜をエッチングして、突
起電極２２を有する半導体装置を形成する。[Protrusion electrode structure: FIG. 15] First, FIG.
With reference to FIG. FIG.
As shown, an insulating film 16 is formed on a semiconductor substrate 12 so as to open an electrode pad 14, and a common electrode film is formed on the entire surface. Further, the bump electrode 22 is formed in a straight wall shape, and the common electrode film is etched to form a semiconductor device having the bump electrode 22.

【０００４】この突起電極２２により半導体装置と、絶
縁性接着剤に導電性材料３２を混在させた異方性導電接
着剤３４により、回路基板２６に形成した回路電極２８
との接続を行う。突起電極２２と回路電極２８との電気
的接続は導電性材料３２によって行い、半導体装置と回
路基板との機械的な接続は絶縁性接着剤によって行う。The protruding electrodes 22 form a semiconductor device, and the circuit electrodes 28 formed on the circuit board 26 are formed by an anisotropic conductive adhesive 34 in which a conductive material 32 is mixed in an insulating adhesive.
Make a connection with The electrical connection between the protruding electrode 22 and the circuit electrode 28 is made by a conductive material 32, and the mechanical connection between the semiconductor device and the circuit board is made by an insulating adhesive.

【０００５】この従来技術におけるストレートウォール
形状の突起電極２２の製造方法を採用することにより、
断面形状が根元より頂部が大きなマッシュルーム形状に
ら比べ、突起電極の横方向への広がりがなく、突起電極
頂部が導電性材料３２で接続可能な平面形状に形成する
ことが可能である。このためストレートウォール形状の
突起電極２２では、接続ピッチを微細化できる利点があ
る。[0005] By adopting the method for manufacturing the straight wall-shaped protruding electrode 22 in the prior art,
Compared to a mushroom shape whose cross section is larger at the top than at the base, the protruding electrode does not spread in the horizontal direction, and the protruding electrode can be formed into a planar shape connectable with the conductive material 32. Therefore, the projection electrode 22 having the straight wall shape has an advantage that the connection pitch can be reduced.

【０００６】〔突起電極の製造方法造：図１１〜図１
５〕つぎにこの従来の技術におけるストレートウォール
突起電極の製造方法を、図１１〜図１５の断面図を用い
て説明する。[Method of Manufacturing Protruding Electrode: FIGS. 11 to 1
5] Next, a method of manufacturing a straight wall projection electrode according to this conventional technique will be described with reference to the sectional views of FIGS.

【０００７】はじめに図１１にしめすように、半導体基
板１２上の全面に、絶縁膜１６を形成し、フォトエッチ
ング技術により、電極パッド１４を露出するように開口
部を有する絶縁膜１６を形成する。First, as shown in FIG. 11, an insulating film 16 is formed on the entire surface of a semiconductor substrate 12, and an insulating film 16 having an opening so as to expose the electrode pad 14 is formed by a photo-etching technique.

【０００８】つぎに図１２にしめすように、共通電極膜
１８を全面にスパッタリング法により形成する。この共
通電極膜１８は、半導体基板１２側からアルミニュウム
を０．８μｍ、クロムを０．０１μｍ、銅を０．８μｍ
の厚さで順次形成する。この多層構造をもつ共通電極膜
１８は、電極パッド１４との接続層と相互拡散を防ぐバ
リヤ層の役割をもつとともに、突起電極をめっき法にて
形成するときの電極としての役割ももつ。Next, as shown in FIG. 12, a common electrode film 18 is formed on the entire surface by a sputtering method. The common electrode film 18 is formed of 0.8 μm of aluminum, 0.01 μm of chromium, and 0.8 μm of copper from the semiconductor substrate 12 side.
Are sequentially formed. The common electrode film 18 having this multilayer structure has a role of a connection layer with the electrode pad 14 and a barrier layer for preventing mutual diffusion, and also a role as an electrode when the protruding electrode is formed by plating.

【０００９】その後、感光性樹脂２０を回転塗布法によ
り１７μｍの厚さで全面に形成し、フォトリソグラフィ
ー技術により、突起電極２２形成部に開口を有するよう
に形成する。Thereafter, a photosensitive resin 20 is formed on the entire surface by a spin coating method to a thickness of 17 μm, and is formed by photolithography so as to have an opening in a protruding electrode 22 forming portion.

【００１０】つぎに図１３にしめすように、金メッキに
よりストレートウォール形状の突起電極２２を１０μｍ
〜１５μｍの厚さで形成する。Next, as shown in FIG. 13, a protruding electrode 22 in the form of a straight wall having a thickness of 10 μm is formed by gold plating.
It is formed with a thickness of １５15 μm.

【００１１】その後、図１４にしめすように、突起電極
２２をマスクにして共通電極膜１８を湿式エッチング法
によりエッチングし、下部電極１９を形成し突起電極を
有する半導体装置を形成する。Thereafter, as shown in FIG. 14, the common electrode film 18 is etched by a wet etching method using the bump electrode 22 as a mask to form a lower electrode 19 to form a semiconductor device having a bump electrode.

【００１２】ここで共通電極膜１８のエッチング処理と
して、湿式エッチングを採用する理由は、共通電極膜１
８は、半導体基板１２側からアルミニュウムを０．８μ
ｍ、クロムを０．０１μｍ、銅を０．８μｍの厚さで３
層構造で形成されるため乾式エッチング法では、被エッ
チング層と他層とのエッチング選択比を得るためにエッ
チングガスを複合エッチングガスを複雑に選択しなけれ
ばならない。Here, the reason why wet etching is employed as an etching process for the common electrode film 18 is that the common electrode film 1
8 is 0.8 μm of aluminum from the semiconductor substrate 12 side.
m, chromium 0.01 μm, copper 0.8 μm thick
In order to obtain an etching selectivity between a layer to be etched and another layer, in the dry etching method, a complex etching gas must be selected as a complex etching gas because it is formed in a layer structure.

【００１３】さらに工業生産的にエッチング加工するた
めの所要時間が非常に長くかかり、処理装置も高価なも
のとなってしまう欠点を有する。Further, it takes a very long time to carry out the etching process for industrial production, and the processing apparatus becomes expensive.

【００１４】しかしながら、湿式エッチング法ではエッ
チング選択比のとれるエッチング液を選択することで、
大がかりな設備を要さずに簡便にエッチング処理を行う
ことができる。However, in the wet etching method, by selecting an etching solution having a high etching selectivity,
The etching process can be easily performed without requiring large-scale equipment.

【００１５】その後、ダイシング工程により半導体基板
１２を単個の半導体チップに切断処理を行なう。Thereafter, the semiconductor substrate 12 is cut into single semiconductor chips by a dicing process.

【００１６】つぎに図１５にしめすように、絶縁性接着
剤に導電材料３２を混在させた異方性導電接着剤３４
を、複数の突起電極２２を有する半導体基板１２と対面
配置した複数の回路電極２８を有する回路基板２６との
間に介在させ、突起電極２２と回路電極２６間に加圧と
加熱を加える。Next, as shown in FIG. 15, an anisotropic conductive adhesive 34 in which a conductive material 32 is mixed in an insulating adhesive.
Is interposed between the semiconductor substrate 12 having the plurality of projecting electrodes 22 and the circuit board 26 having the plurality of circuit electrodes 28 disposed facing each other, and pressurization and heating are applied between the projecting electrodes 22 and the circuit electrodes 26.

【００１７】このことにより、突起電極２２と回路電極
２８との間に導電性材料３２が確保され、突起電極２２
と回路電極２８の電気的・機会的な接続を行う。As a result, the conductive material 32 is secured between the protruding electrode 22 and the circuit electrode 28, and
And the circuit electrode 28 are electrically and opportunistically connected.

【００１８】[0018]

【発明が解決しようとする課題】しかしながら従来の突
起電極２２の構造と製造方法およびその接続構造では、
突起電極２２と回路電極２８の間に導電性材料３２を混
在させた異方性導電接着剤３４を介在し、加熱加圧のと
きに、導電性材料３２が突起電極２２と回路電極２８間
から流れだし、突起電極２２と回路電極２８の間の導電
性材料３２の数が極端に減少してしまう。However, in the conventional structure, manufacturing method and connection structure of the protruding electrode 22,
An anisotropic conductive adhesive 34 in which a conductive material 32 is mixed is interposed between the protruding electrode 22 and the circuit electrode 28, and the conductive material 32 is removed from between the protruding electrode 22 and the circuit electrode 28 during heating and pressing. Then, the number of the conductive materials 32 between the protruding electrodes 22 and the circuit electrodes 28 is extremely reduced.

【００１９】充分な接続抵抗値（初期０．１Ω以下）と
高信頼性を確保するためには、突起電極２２と回路基板
２８との間に介在する導電性材料３２の数が１０個以上
必要である。In order to secure a sufficient connection resistance value (0.1 Ω or less at the beginning) and high reliability, the number of conductive materials 32 interposed between the projecting electrode 22 and the circuit board 28 is required to be 10 or more. It is.

【００２０】エポキシ系接着剤中に混在させた導電性材
料３２は、直径が５μｍのプラスチックビーズの表面に
ニッケルー金が形成されている。この導電性材料３２の
１個当たりの接続抵抗値は約１Ωであり、初期の接続抵
抗値を０．１Ωにすることで、温度８５℃／湿度８５％
雰囲気における高温高湿信頼性試験１０００時間後の接
続抵抗値を１Ω以下にすることができる。In the conductive material 32 mixed in the epoxy adhesive, nickel-gold is formed on the surface of plastic beads having a diameter of 5 μm. The connection resistance value of each of the conductive materials 32 is about 1Ω. By setting the initial connection resistance value to 0.1Ω, the temperature is 85 ° C./humidity 85%.
The connection resistance after 1000 hours of the high-temperature and high-humidity reliability test in the atmosphere can be reduced to 1Ω or less.

【００２１】このときの接続抵抗値が上昇する理由は、
突起電極２２と回路基板２８との間の絶縁性接着剤であ
るエポキシ系接着剤の劣化により接着力が低下し、突起
電極２２と回路電極２６間隔が広がることによって、導
電性材料３２の接続面積が低下するためである。The reason why the connection resistance value increases at this time is as follows.
Deterioration of the epoxy-based adhesive, which is an insulating adhesive between the protruding electrode 22 and the circuit board 28, reduces the adhesive force, and the distance between the protruding electrode 22 and the circuit electrode 26 is increased, thereby increasing the connection area of the conductive material 32. Is to be reduced.

【００２２】このため導電性材料３２の数を１０個以上
確保するためには、突起電極２２の面積を６０００μｍ
2 以上にしなければならない。そのため従来の技術で
は、低接続抵抗値でしかも高信頼性のある微細ピッチ接
続を行うことが非常に困難であった。Therefore, in order to secure 10 or more conductive materials 32, the area of the protruding electrode 22 must be 6000 μm.
Must be 2 or more. Therefore, it has been very difficult with the conventional technology to make a fine pitch connection having a low connection resistance value and high reliability.

【００２３】〔発明の目的〕本発明の目的は、上記課題
を解決し、接続加圧時に発生する突起電極と回路電極間
の導電性材料の流れだしを防止し突起電極と回路電極間
の導電性材料の数を充分に確保し、接続信頼性を向上さ
せさらに、接続面積を小さくして、接続ピッチの微細化
と高信頼性のある半導体装置および製造方法とその接続
構造を提供することである。[Object of the Invention] An object of the present invention is to solve the above-mentioned problems, to prevent the flow of a conductive material between a projecting electrode and a circuit electrode which occurs at the time of connection pressurization, and to prevent the conductive material from flowing between the projecting electrode and the circuit electrode. By ensuring a sufficient number of conductive materials, improving the connection reliability, and further reducing the connection area, providing a semiconductor device with a fine connection pitch and high reliability, a manufacturing method, and a connection structure thereof. is there.

【００２４】[0024]

【課題を解決するための手段】上記目的を達成するため
に本発明の半導体装置およびその製造方法およびその接
続構造においては、下記記載の手段を採用する。Means for Solving the Problems In order to achieve the above object, the following means are employed in a semiconductor device, a method of manufacturing the same, and a connection structure thereof according to the present invention.

【００２５】本発明の半導体装置の構造は、電極パッド
上の周縁部に開口部を有する絶縁膜と、電極パッド上に
設ける下部電極膜と、突起電極とを有する半導体装置で
あって、突起電極の頂部は中央部が周縁部より低いこと
を特徴とする。The structure of a semiconductor device according to the present invention is a semiconductor device having an insulating film having an opening at a peripheral portion on an electrode pad, a lower electrode film provided on the electrode pad, and a projecting electrode. Is characterized in that the central part is lower than the peripheral part.

【００２６】本発明の半導体装置の構造では、絶縁膜は
無機膜と有機膜との２層からなり突起電極の中央部と周
縁部の段差と、絶縁膜の膜厚とがほぼ同じであることを
特徴とする。In the structure of the semiconductor device of the present invention, the insulating film is composed of two layers, an inorganic film and an organic film, and the step between the central portion and the peripheral portion of the bump electrode and the film thickness of the insulating film are substantially the same. It is characterized by.

【００２７】本発明の半導体装置の構造では、電極パッ
ド周縁部の絶縁膜の形状はほぼ同一形状であり、突起電
極の中央部と周縁部の段差と、絶縁膜の膜厚とが同じで
あることを特徴とする。In the structure of the semiconductor device of the present invention, the shape of the insulating film at the peripheral portion of the electrode pad is substantially the same, and the step between the central portion and the peripheral portion of the protruding electrode has the same thickness as the insulating film. It is characterized by the following.

【００２８】本発明の半導体装置の構造では、絶縁膜は
無機膜と有機膜との２層からなり有機膜の電極パッド周
縁部の形状は、無機膜より外周部に配置し、突起電極の
中央部と周縁部の段差と、有機膜の膜厚とがほぼ同じで
あることを特徴とする。In the structure of the semiconductor device according to the present invention, the insulating film is composed of two layers, an inorganic film and an organic film, and the periphery of the electrode pad of the organic film is arranged on the outer periphery of the inorganic film, and the center of the protruding electrode is formed. It is characterized in that the step between the portion and the peripheral portion and the thickness of the organic film are substantially the same.

【００２９】本発明の半導体装置の構造では、絶縁膜は
無機膜からなり、突起電極の中央部と周縁部の段差と、
無機膜の膜厚とがほぼ同じであることを特徴とする。In the structure of the semiconductor device according to the present invention, the insulating film is made of an inorganic film, and the step between the central portion and the peripheral portion of the bump electrode is
It is characterized in that the thickness of the inorganic film is substantially the same.

【００３０】本発明の半導体装置の構造では、絶縁膜は
有機膜からなり、突起電極の中央部と周縁部の段差と、
有機膜の膜厚とが同じであることを特徴とする。In the structure of the semiconductor device according to the present invention, the insulating film is made of an organic film, and has a step between the center and the periphery of the bump electrode;
It is characterized in that the thickness of the organic film is the same.

【００３１】本発明の半導体装置の製造方法において
は、電極パッド上に突起電極の中央部と周縁部の段差
と、絶縁膜の膜厚とが同じ膜厚をもつ絶縁膜の開口を有
する半導体装置上に共通電極膜を全面に形成する工程
と、感光性樹脂をパターンニングする工程と、感光性樹
脂表面を親水化処理する工程と、感光性樹脂開口部に突
起電極を形成する工程と、感光性樹脂を除去する工程
と、共通電極膜を突起電極をマスクにしてパターンニン
グする工程を有することを特徴とする。In the method of manufacturing a semiconductor device according to the present invention, a semiconductor device having a step on a central portion and a peripheral portion of a protruding electrode and an opening in an insulating film having the same thickness as the insulating film on an electrode pad. Forming a common electrode film on the entire surface, patterning the photosensitive resin, hydrophilizing the photosensitive resin surface, forming a protruding electrode in the photosensitive resin opening, A step of removing the conductive resin and a step of patterning the common electrode film using the protruding electrodes as a mask.

【００３２】本発明の半導体装置の接続構造において
は、電極パッド上の周縁部に開口部を有する絶縁膜と、
電極パッド上に設ける下部電極膜と、突起電極とを有す
る半導体装置であって、突起電極の頂部は中央部が周辺
部より低く、導電性材料が突起電極の凹部に確保され対
面する回路電極と接続することを特徴とする。In the connection structure for a semiconductor device according to the present invention, an insulating film having an opening at a peripheral portion on an electrode pad;
A semiconductor device having a lower electrode film provided on an electrode pad and a protruding electrode, wherein a top portion of the protruding electrode has a central portion lower than a peripheral portion, and a conductive material is secured in a concave portion of the protruding electrode and a circuit electrode facing the same. It is characterized by connecting.

【００３３】本発明の半導体装置の接続構造では、導電
性材料の粒径は、突起電極頂部の段差寸法より大きいこ
とを特徴とする。The connection structure of the semiconductor device according to the present invention is characterized in that the particle size of the conductive material is larger than the step size at the top of the bump electrode.

【００３４】本発明の半導体装置の接続構造では、導電
性材料の粒径は、突起電極頂部の段差寸法とほぼ同じか
小さいことを特徴とする。In the connection structure for a semiconductor device according to the present invention, the particle size of the conductive material is substantially equal to or smaller than the step size at the top of the bump electrode.

【００３５】〔作用〕本発明による半導体装置の構造と
製造方法および接続構造は、突起電極頂部の中央部が周
縁部よりも低くしている。このことによって、突起電極
と回路電極との間の導電性材料が接続加圧されたとき
に、異方性導電接着剤の流動とともに流れ出すのを抑
え、突起電極と回路電極との間の導電性材料を充分な数
が確保できる。[Operation] In the structure, manufacturing method and connection structure of the semiconductor device according to the present invention, the center of the top of the protruding electrode is lower than the periphery. This prevents the conductive material between the protruding electrode and the circuit electrode from flowing out together with the flow of the anisotropic conductive adhesive when the connection material is pressurized. A sufficient number of materials can be secured.

【００３６】さらに充分な数の導電性材料を確保するこ
とができることによって、突起電極面積を小さくするこ
とができ、微細ピッチでしかも高信頼性の接続を提供す
ることが可能となる。Since a sufficient number of conductive materials can be secured, the area of the protruding electrodes can be reduced, and a highly reliable connection with a fine pitch can be provided.

【００３７】[0037]

【発明の実施の形態】以下図面を用いて本発明を実施す
るための最良の形態における半導体装置の構造および製
造方法および接続構造を説明する。図１〜図１０は本発
明の半導体装置の構造と製造方法をおよび接続構造をし
めす断面図および平面図である。まずはじめに図５を用
いて本発明の半導体装置の構造および接続構造を説明す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure, manufacturing method and connection structure of a semiconductor device in the best mode for carrying out the present invention will be described below with reference to the drawings. 1 to 10 are a sectional view and a plan view showing a structure and a manufacturing method of a semiconductor device according to the present invention, and a connection structure. First, the structure and connection structure of the semiconductor device of the present invention will be described with reference to FIG.

【００３８】〔本発明の半導体装置の構造および接続構
造説明：図５および図６〕半導体基板１２上に電極パッ
ド１４に開口部を有する無機絶縁膜１７と、有機絶縁膜
１５を同一平面形状で設け、電極パッド１４と接続する
下部電極１９と、下部電極１９と接続する突起電極２２
とを設ける。さらに、突起電極２２の平面形状は、図６
に示すように下部電極１９のエッチング余裕度を考慮し
無機絶縁膜１７および有機絶縁膜１５の開口寸法より５
μｍ〜１０μｍ大きく形成して、突起電極２２の頂部は
中央部が周縁部より低い形状で構成する。[Description of Structure and Connection Structure of Semiconductor Device of the Present Invention: FIGS. 5 and 6] On a semiconductor substrate 12, an inorganic insulating film 17 having an opening in an electrode pad 14 and an organic insulating film 15 are formed in the same plane. A lower electrode 19 connected to the electrode pad 14 and a protruding electrode 22 connected to the lower electrode 19
Are provided. Further, the planar shape of the bump electrode 22 is shown in FIG.
As shown in FIG. 5, the opening size of the inorganic insulating film 17 and the organic insulating film 15 is 5
The protrusions 22 are formed to be larger by 10 μm to 10 μm.

【００３９】このときの突起電極２２の頂部の周縁部は
中央部より２〜５μｍ高くなるように構成する。このよ
うに突起電極２２頂部の周縁部を中央部より高くするこ
とによって、突起電極２２と、回路基板２６上の回路電
極２８との間の導電性材料３２が接続加圧の際に異方性
導電接着剤３４とともに接続面からの流動するのを防止
し、接続面に充分な数の導電性材料３２が確保され、半
導体装置の品質を向上する。At this time, the periphery of the top of the protruding electrode 22 is configured to be 2 to 5 μm higher than the center. By making the peripheral edge of the top of the protruding electrode 22 higher than the center in this way, the conductive material 32 between the protruding electrode 22 and the circuit electrode 28 on the circuit board 26 becomes anisotropic during connection pressurization. It prevents flow from the connection surface together with the conductive adhesive 34, and secures a sufficient number of conductive materials 32 on the connection surface, thereby improving the quality of the semiconductor device.

【００４０】〔本発明の半導体装置の製造方法説明：図
１〜図１０〕つぎにこの図５にしめす構造の半導体装置
の製造方法を説明する、また図６、図８および図１０は
本発明による半導体装置の電極パッド部をしめす平面図
であり断面図と平面図をもちいて説明する。[Description of Manufacturing Method of Semiconductor Device of the Present Invention: FIGS. 1 to 10] Next, a method of manufacturing a semiconductor device having a structure shown in FIG. 5 will be described. FIGS. 6, 8 and 10 show the present invention. Is a plan view showing an electrode pad portion of a semiconductor device according to the present invention, and a description will be given with reference to a sectional view and a plan view.

【００４１】図１にしめすように、所定の素子を形成し
た半導体基板１２上のアルミニウムからなる電極パッド
１４を開口するように無機絶縁膜１７と有機絶縁膜１５
とを同一形状で形成する。As shown in FIG. 1, an inorganic insulating film 17 and an organic insulating film 15 are formed so as to open an electrode pad 14 made of aluminum on a semiconductor substrate 12 on which a predetermined element is formed.
Are formed in the same shape.

【００４２】この無機絶縁膜１７は、窒化珪素をプラズ
マ化学的気相成長法により、全面に１μｍの厚さで形成
する。This inorganic insulating film 17 is formed with a thickness of 1 μm on the entire surface by plasma chemical vapor deposition of silicon nitride.

【００４３】この無機絶縁膜１７は、窒化珪素以外に、
二酸化珪素や、酸化タンタルや、酸化アルミニュウムな
どの無機膜でも有効である。さらに膜形成方法として
は、プラズマ化学的気相成長法以外に、スパッタリング
法でも形成可能である。The inorganic insulating film 17 is made of a material other than silicon nitride.
Inorganic films such as silicon dioxide, tantalum oxide, and aluminum oxide are also effective. Further, as a film forming method, a sputtering method can be used in addition to the plasma chemical vapor deposition method.

【００４４】つぎに、有機絶縁膜１５としてたとえば感
光性ポリイミドを回転塗布法によって、２μｍ〜３μｍ
の厚さで全面に形成する。Next, for example, photosensitive polyimide is applied as the organic insulating film 15 by a spin coating method to a thickness of 2 μm to 3 μm.
It is formed over the entire surface with a thickness of

【００４５】その後、フォトエッチング工程により電極
パッド１４を開口させ、しかも電極パッド１４の周縁部
で重なるように有機絶縁膜１５のパターンニングを行
う。After that, the electrode pad 14 is opened by a photo-etching process, and the organic insulating film 15 is patterned so as to overlap the peripheral portion of the electrode pad 14.

【００４６】その後、有機絶縁膜１５をマスクにして無
機絶縁膜１７を乾式エッチング法により、四フッ化炭素
あるいは六フッ化イオウのエッチングガスをもちいて、
エッチングを行い有機絶縁膜１５と同一パターン形状で
無機絶縁膜１７を形成する。このときの平面形状パター
ン形状を、図６平面図の一点鎖線にしめす。Thereafter, the inorganic insulating film 17 is dry-etched using the organic insulating film 15 as a mask, using an etching gas of carbon tetrafluoride or sulfur hexafluoride.
Etching is performed to form the inorganic insulating film 17 in the same pattern shape as the organic insulating film 15. The planar shape pattern shape at this time is shown by a dashed line in FIG.

【００４７】無機絶縁膜１７上に有機絶縁膜１５を形成
する理由は、突起電極２２の応力緩和効果と、電極パッ
ドの周縁部に３μｍ〜５μｍの段差を簡便に形成するこ
とが可能であるためである。The reason for forming the organic insulating film 15 on the inorganic insulating film 17 is that the effect of relaxing the stress of the protruding electrode 22 and the step of 3 μm to 5 μm at the peripheral portion of the electrode pad can be easily formed. It is.

【００４８】その後、図２にしめすように有機絶縁膜１
５上全面にスパッタリング法によりアルミニウムを０．
８μｍ、クロムを０．０１μｍ、銅を０．８μｍ順次膜
形成し、共通電極膜１８を３層構造で形成する。Thereafter, as shown in FIG.
Aluminum was sputtered on the entire surface on the top surface.
8 μm, chromium 0.01 μm and copper 0.8 μm are sequentially formed, and the common electrode film 18 is formed in a three-layer structure.

【００４９】この共通電極膜１８は電極パッド１４およ
び突起電極２２で形成される電極材料との電気的、機械
的接続性が良好で電極材料相互の拡散が無く安定な電極
材料の選定が必要である。The common electrode film 18 has good electrical and mechanical connectivity with the electrode material formed by the electrode pads 14 and the protruding electrodes 22, and it is necessary to select a stable electrode material without diffusion between the electrode materials. is there.

【００５０】共通電極１８はチタン−パラジウムや、チ
タン−金や、チタン−白金や、チタン・タングステン合
金−パラジウムや、チタン・タングステン合金−金や、
チタン・タングステン合金−白金などの２層膜構造や、
アルミニウム−チタン−銅の３層構造でも有効である。The common electrode 18 is made of titanium-palladium, titanium-gold, titanium-platinum, titanium-tungsten alloy-palladium, titanium-tungsten alloy-gold,
Titanium-tungsten alloy-platinum two-layer film structure,
An aluminum-titanium-copper three-layer structure is also effective.

【００５１】その後、図３にしめすように、感光性樹脂
を回転塗布法により共通電極膜１８上の全面に１７μｍ
の厚さで形成し、フォトマスクを用いて露光、現像処理
を行い、感光性樹脂のパターンニングを行い感光性樹脂
２０を形成する。Thereafter, as shown in FIG. 3, a photosensitive resin is applied over the entire surface of the common electrode film 18 by a spin coating method to a thickness of 17 μm.
The photosensitive resin 20 is formed by performing exposure and development processing using a photomask, and patterning the photosensitive resin.

【００５２】つぎに感光性樹脂２０をメッキマスクにし
て、金めっきを１０μｍ〜１５μｍの厚さで形成し突起
電極２２を形成する。このときの平面パターン形状を図
６の破線にしめす。Next, using the photosensitive resin 20 as a plating mask, gold plating is formed to a thickness of 10 μm to 15 μm to form the protruding electrodes 22. The flat pattern shape at this time is shown by a broken line in FIG.

【００５３】その後、図４にしめすように、湿式剥離液
をもちいて感光性樹脂２０の除去を行う。さらに、突起
電極２２をエッチングマスクにして、共通電極膜１８の
最上層被膜である銅を、メルテックス製の銅エッチング
液エンストリップＣ（商品名）によりエッチングを行
う。なおこのエッチング処理は、ジャストエッチングか
ら３０％のオバーエッチング時間でエッチングを行う。Thereafter, as shown in FIG. 4, the photosensitive resin 20 is removed using a wet stripper. Further, using the protruding electrode 22 as an etching mask, copper, which is the uppermost layer coating of the common electrode film 18, is etched with a copper etchant Enstrip C (trade name) manufactured by Meltex. In this etching process, etching is performed in just over etching time of 30%.

【００５４】つぎに硝酸セリウムアンモニウムとフェリ
シアン化カリウムと水酸化ナトリウムとの混合液によ
り、共通電極膜１８のバリヤ層および密着層であるクロ
ム（中層）、およびアルミニュウム（最下層）のエッチ
ングを行う。なおこのエッチング処理は、ジャストエッ
チングから３０％のオバーエッチング時間でエッチング
を行う。この結果、下部電極１９を形成して突起電極２
２の頂部の中央部が周縁部に比べて３μｍ〜５μｍ低い
半導体装置を形成する。このときの平面パターン形状を
図６の点線にしめす。Next, chromium (middle layer) and aluminum (lowest layer), which are a barrier layer and an adhesion layer, of the common electrode film 18 are etched with a mixed solution of cerium ammonium nitrate, potassium ferricyanide, and sodium hydroxide. In this etching process, etching is performed in just over etching time of 30%. As a result, the lower electrode 19 is formed and the bump electrode 2 is formed.
2 forms a semiconductor device whose central part at the top is lower by 3 μm to 5 μm than the peripheral part. The planar pattern shape at this time is shown by a dotted line in FIG.

【００５５】突起電極２２頂部の中央部と周縁部の高さ
の差は、無機絶縁膜１７と有機絶縁膜１５の形成膜厚に
よって制御する。The difference in height between the central portion and the peripheral portion at the top of the bump electrode 22 is controlled by the thickness of the inorganic insulating film 17 and the organic insulating film 15 formed.

【００５６】つぎに、ダイシング工程により半導体基板
１２を単個の半導体チップに切断を行う。Next, the semiconductor substrate 12 is cut into single semiconductor chips by a dicing process.

【００５７】その後、図５にしめすように、絶縁性接着
剤としてたとえば熱硬化型エポキシ系接着剤に、球状プ
ラスチックの表面にニッケル−金の２層メッキされた、
外径４μｍ〜６μｍのビーズ状の導電性材料３２を、体
積比で約４０％混在させた異方性導電接着剤３４を複数
の突起電極２２を有する半導体基板１２と対面配置した
複数の回路電極２８を有する回路基板２６との間に介在
させる。その後、突起電極２２と回路電極２６間に４０
０Ｋｇ／ｃｍ2 の圧力で加圧しながら、１８０℃〜２２
０℃の温度で加熱を加える。Thereafter, as shown in FIG. 5, two layers of nickel-gold were plated on the surface of the spherical plastic by, for example, a thermosetting epoxy adhesive as an insulating adhesive.
A plurality of circuit electrodes in which an anisotropic conductive adhesive 34 in which bead-shaped conductive material 32 having an outer diameter of 4 μm to 6 μm is mixed at a volume ratio of about 40% faces semiconductor substrate 12 having a plurality of bump electrodes 22. 28 and a circuit board 26 having the same. Then, 40 between the protruding electrode 22 and the circuit electrode 26.
180 ° C. to 22 while pressing at a pressure of 0 kg / cm 2.
Heat is applied at a temperature of 0 ° C.

【００５８】このことにより、突起電極２２と回路電極
２８の間に導電材料３２が確保されて、突起電極２２と
回路電極２８の機械的電気的な接続を行う。As a result, the conductive material 32 is secured between the protruding electrode 22 and the circuit electrode 28, and the protruding electrode 22 and the circuit electrode 28 are mechanically and electrically connected.

【００５９】〔別の実施形態の半導体装置説明：図７お
よび図８〕つぎに、第２の発明の実施の形態における製
造方法と構造および接続構造を、図７の断面図と図８の
平面図をもちいて説明する。[Explanation of Semiconductor Device of Another Embodiment: FIGS. 7 and 8] Next, a manufacturing method, a structure and a connection structure according to the second embodiment of the present invention will be described with reference to a cross-sectional view of FIG. 7 and a plan view of FIG. This will be described with reference to the drawings.

【００６０】図７にしめすように、所定の素子を形成し
た半導体基板１２上のアルミニウムからなる電極パッド
１４を開口するように無機絶縁膜１７を形成する。As shown in FIG. 7, an inorganic insulating film 17 is formed so as to open an electrode pad 14 made of aluminum on a semiconductor substrate 12 on which a predetermined element is formed.

【００６１】この無機絶縁膜１７は、窒化珪素をプラズ
マ化学的気相成長法によって、全面に２μｍ〜３μｍの
厚さで形成する。The inorganic insulating film 17 is formed on the entire surface of silicon nitride to a thickness of 2 μm to 3 μm by a plasma chemical vapor deposition method.

【００６２】またこの無機絶縁膜は、窒化珪素以外に二
酸化珪素や、酸化タンタルや、酸化アルミニュウムなど
の無機膜でも適用である。さらに、膜形成方法もプラズ
マ化学的気相成長法以外に、スパッタリング法でも適用
可能である。The inorganic insulating film may be an inorganic film such as silicon dioxide, tantalum oxide, or aluminum oxide, other than silicon nitride. Further, the film formation method can be applied by a sputtering method other than the plasma chemical vapor deposition method.

【００６３】つぎに、フォトリソ工程とエッチング工程
を行い無機絶縁膜１７を形成する。このときの平面パタ
ーン形状は、図８の一点鎖線にしめす。Next, a photolithography step and an etching step are performed to form an inorganic insulating film 17. The shape of the plane pattern at this time is shown by a dashed line in FIG.

【００６４】その後、無機絶縁膜１７上の全面にスパッ
タリング法によって、アルミニウムを０．８μｍ、クロ
ムを０．０１μｍ、銅を０．８μｍの膜厚で順次膜形成
し、共通電極膜１８を３層構造で形成する。Thereafter, aluminum is sequentially formed to a thickness of 0.8 μm, chromium is formed to a thickness of 0.01 μm, and copper is formed to a thickness of 0.8 μm on the entire surface of the inorganic insulating film 17 by sputtering. Formed with a structure.

【００６５】この共通電極膜１８は、電極パッド１４お
よび突起電極２２で形成される電極材料との電気的、機
械的接続性が良好で、電極材料相互の拡散がなく安定な
電極材料の選定が必要である。The common electrode film 18 has good electrical and mechanical connectivity with the electrode material formed by the electrode pads 14 and the protruding electrodes 22, and allows selection of a stable electrode material without diffusion between the electrode materials. is necessary.

【００６６】共通電極１８はチタン−パラジウムや、チ
タン−金や、チタン−白金や、チタン・タングステン合
金−パラジウムや、チタン・タングステン合金−金や、
チタン・タングステン合金−白金などの２層膜構造や、
アルミニウム−チタン−銅の３層構造でも適用可能であ
る。The common electrode 18 is made of titanium-palladium, titanium-gold, titanium-platinum, titanium-tungsten alloy-palladium, titanium-tungsten alloy-gold,
Titanium-tungsten alloy-platinum two-layer film structure,
A three-layer structure of aluminum-titanium-copper is also applicable.

【００６７】その後、感光性樹脂を回転塗布法により、
共通電極膜１８上の全面に１７μｍの厚さで形成する。
その後、フォトマスクを用いて露光、現像を行い感光性
樹脂のパターンニングを行い感光性樹脂２０を形成す
る。Thereafter, a photosensitive resin is applied by a spin coating method.
It is formed on the entire surface of the common electrode film 18 with a thickness of 17 μm.
After that, exposure and development are performed using a photomask, and patterning of the photosensitive resin is performed to form the photosensitive resin 20.

【００６８】つぎに感光性樹脂２０をメッキマスクにし
て、金めっきを１０μｍ〜１５μｍの厚さで形成し突起
電極２２を形成する。このときの平面パターン形状を図
８の破線にしめす。Next, using the photosensitive resin 20 as a plating mask, gold plating is formed to a thickness of 10 μm to 15 μm to form the protruding electrodes 22. The flat pattern shape at this time is shown by a broken line in FIG.

【００６９】その後、湿式剥離液をもちいて感光性樹脂
２０の除去を行い、突起電極２２をエッチングマスクに
して共通電極膜１８の最上層被膜である銅を、メルテッ
クス製の銅エッチング液エンストリップＣ（商品名）を
使用してエッチングを行う。なおこのエッチング処理
は、ジャストエッチングから３０％のオバーエッチング
時間でエッチングを行う。Thereafter, the photosensitive resin 20 is removed by using a wet stripper, and copper, which is the uppermost layer of the common electrode film 18, is removed using a bump electrode 22 as an etching mask. Etching is performed using C (trade name). In this etching process, etching is performed in just over etching time of 30%.

【００７０】つぎに硝酸セリウムアンモニウムとフェリ
シアン化カリウムと水酸化ナトリウムとの混合液によ
り、共通電極膜１８のバリヤ層および密着層であるクロ
ム（中層）、およびアルミニュウム（最下層）のエッチ
ングを行う。なおこのエッチング処理は、ジャストエッ
チングから３０％のオバーエッチング時間でエッチング
を行う。この結果、下部電極１９を形成して、突起電極
２２の頂部の中央部が周縁部に比べて２〜３μｍ低い半
導体装置を無機絶縁膜１７をもちいて形成する。このと
きの下部電極１９の平面パターン形状を図８の点線にし
めす。Next, chromium (middle layer), which is a barrier layer and an adhesion layer, and aluminum (lowest layer) of the common electrode film 18 are etched with a mixed solution of cerium ammonium nitrate, potassium ferricyanide, and sodium hydroxide. In this etching process, etching is performed in just over etching time of 30%. As a result, the lower electrode 19 is formed, and a semiconductor device in which the center of the top of the protruding electrode 22 is lower by 2 to 3 μm than the periphery is formed using the inorganic insulating film 17. The planar pattern shape of the lower electrode 19 at this time is shown by a dotted line in FIG.

【００７１】つぎに、ダイシング工程により半導体基板
１２を単個の半導体チップに切断を行う。Next, the semiconductor substrate 12 is cut into single semiconductor chips by a dicing process.

【００７２】その後、図７にしめすように、導電性材料
３２を混在させた異方性導電接着剤３４を、複数の突起
電極２２を有する半導体基板１２と対面配置した複数の
回路電極２８を有する回路基板２６との間に介在させる
ように形成する。その後、突起電極２２と回路電極２６
間に４００Ｋｇ／ｃｍ2 の圧力で加圧しながら１８０〜
２２０℃の温度で加熱を加える。Thereafter, as shown in FIG. 7, a plurality of circuit electrodes 28 having an anisotropic conductive adhesive 34 mixed with a conductive material 32 facing the semiconductor substrate 12 having a plurality of projecting electrodes 22 are provided. It is formed so as to be interposed between the circuit board 26. After that, the projecting electrode 22 and the circuit electrode 26
Pressurizing at a pressure of 400 Kg / cm 2 during 180-
Heat is applied at a temperature of 220 ° C.

【００７３】第２の実施の形態においては突起電極２２
頂部の中央部と周縁部との高さの差は無機絶縁膜１７の
形成膜厚によって制御する。このように無機絶縁膜１７
単層のみで突起電極２２の段差構造をもつ頂部形状を形
成することが簡便に行うことができる。さらに無機絶縁
膜１７上の共通電極膜１８は、その界面で相互拡散層を
形成して、付着力は有機絶縁膜に比較して高く、突起電
極２２の機械的強度が向上する利点がある。In the second embodiment, the projection electrode 22
The difference in height between the central portion and the peripheral portion of the top is controlled by the thickness of the inorganic insulating film 17 formed. Thus, the inorganic insulating film 17
It is easy to form the top shape having the step structure of the bump electrode 22 with only a single layer. Further, the common electrode film 18 on the inorganic insulating film 17 forms an interdiffusion layer at its interface, has an adhesive force higher than that of the organic insulating film, and has an advantage that the mechanical strength of the bump electrode 22 is improved.

【００７４】〔さらに別の実施形態の半導体装置説明：
図９および図１０〕つぎに、第３の発明の実施の形態に
おける構造と製造方法および接続構造を、図９の断面図
と図１０の平面図をもちいて説明する。[Description of Semiconductor Device of Still Another Embodiment:
9 and 10] Next, a structure, a manufacturing method, and a connection structure according to the third embodiment of the present invention will be described with reference to a cross-sectional view of FIG. 9 and a plan view of FIG.

【００７５】図９にしめすように、所定の素子を形成し
た半導体基板１２上のアルミニウムからなる電極パッド
１４を開口するように無機絶縁膜１７を形成する。As shown in FIG. 9, an inorganic insulating film 17 is formed so as to open an electrode pad 14 made of aluminum on a semiconductor substrate 12 on which a predetermined element is formed.

【００７６】この無機絶縁膜１７は、窒化珪素をプラズ
マ化学的気相成長法によって、全面に１μｍの厚さで形
成する。The inorganic insulating film 17 is formed of silicon nitride to a thickness of 1 μm over the entire surface by plasma chemical vapor deposition.

【００７７】この無機絶縁膜は窒化珪素以外に、二酸化
珪素や、酸化タンタルや、酸化アルミニュウムなどの無
機膜も適用できる。さらに被膜形成方法として、プラズ
マ化学的気相成長法以外に、スパッタリング法でも形成
可能である。As the inorganic insulating film, other than silicon nitride, an inorganic film such as silicon dioxide, tantalum oxide, or aluminum oxide can be used. Further, as a film forming method, a sputtering method can be used in addition to the plasma chemical vapor deposition method.

【００７８】つぎに、フォトリソ工程とエッチング工程
を行い無機絶縁膜１７を形成する。このときの平面パタ
ーン形状は、図１０の一点鎖線にしめす。Next, a photolithography step and an etching step are performed to form an inorganic insulating film 17. The shape of the plane pattern at this time is shown by a dashed line in FIG.

【００７９】その後、無機絶縁膜１７上の全面に、有機
絶縁膜１５としてたとえば感光性ポリイミドを回転塗布
法により２μｍ〜３μｍの厚さで形成する。Thereafter, photosensitive polyimide, for example, is formed on the entire surface of the inorganic insulating film 17 as the organic insulating film 15 to a thickness of 2 μm to 3 μm by spin coating.

【００８０】その後、露光処理と現像処理を行い、有機
絶縁膜１５を形成する。この有機絶縁膜１５の平面パタ
ーン形状は、図１０の二点鎖線にしめすように無機絶縁
膜１７の外周部に開口をもつように形成する。このとき
の無機絶縁膜１７の開口端と有機絶縁膜１５の開口端と
の寸法差は、３μｍ〜５μｍで形成する。Thereafter, an exposure process and a development process are performed to form an organic insulating film 15. The organic insulating film 15 is formed so as to have an opening in the outer peripheral portion of the inorganic insulating film 17 as shown by a two-dot chain line in FIG. At this time, the dimensional difference between the opening end of the inorganic insulating film 17 and the opening end of the organic insulating film 15 is 3 μm to 5 μm.

【００８１】その後、無機絶縁膜１７上の全面にスパッ
タリング法により、アルミニウムを０．８μｍ、クロム
を０．０１μｍ、銅を０．８μｍの膜厚で順次膜形成
し、共通電極膜１８を３層構造で形成する。Thereafter, aluminum is sequentially formed to a thickness of 0.8 μm, chromium to a thickness of 0.01 μm, and copper to a thickness of 0.8 μm on the entire surface of the inorganic insulating film 17 by a sputtering method. Formed with a structure.

【００８２】この共通電極膜１８は、電極パッド１４お
よび突起電極２２で形成される電極材料との電気的、機
械的接続性が良好で、電極材料相互の拡散がなく安定な
電極材料の選定が必要である。The common electrode film 18 has good electrical and mechanical connectivity with the electrode material formed by the electrode pads 14 and the protruding electrodes 22, and allows the selection of a stable electrode material without diffusion between the electrode materials. is necessary.

【００８３】共通電極膜１８は、チタン−パラジウム
や、チタン−金や、チタン−白金や、チタン・タングス
テン合金−パラジウムや、チタン・タングステン合金−
金や、チタン・タングステン合金−白金などの２層構造
や、アルミニウム−チタン−銅の３層構造も適用でき
る。The common electrode film 18 is made of titanium-palladium, titanium-gold, titanium-platinum, titanium-tungsten alloy-palladium, titanium-tungsten alloy-
A two-layer structure of gold, titanium / tungsten alloy-platinum, or a three-layer structure of aluminum-titanium-copper can also be applied.

【００８４】その後、感光性樹脂を回転塗布法により共
通電極膜１８上の全面に１７μｍの厚さで形成する。そ
の後、フォトマスクを用いて露光、現像を行い感光性樹
脂のパターンニングを行い感光性樹脂２０を形成する。Thereafter, a photosensitive resin is formed on the entire surface of the common electrode film 18 to a thickness of 17 μm by spin coating. After that, exposure and development are performed using a photomask, and patterning of the photosensitive resin is performed to form the photosensitive resin 20.

【００８５】つぎに感光性樹脂２０をメッキマスクにし
て、金めっきを１０μｍ〜１５μｍの厚さで形成し突起
電極２２を形成する。このときの平面パターン形状を図
１０の破線にしめす。Next, using the photosensitive resin 20 as a plating mask, gold plating is formed to a thickness of 10 μm to 15 μm to form the protruding electrodes 22. The flat pattern shape at this time is shown by a broken line in FIG.

【００８６】その後、湿式剥離液をもちいて感光性樹脂
２０の除去する。さらにその後、突起電極２２をエッチ
ングマスクにして共通電極膜１８の最上層メタルである
銅をメルテックス製の銅エッチング液エンストリップＣ
（商品名）によりエッチングする。なおこのエッチング
処理は、ジャストエッチングから３０％のオバーエッチ
ング時間でエッチングを行う。Thereafter, the photosensitive resin 20 is removed using a wet stripper. Thereafter, copper, which is the uppermost metal of the common electrode film 18, is etched using the protruding electrode 22 as an etching mask, and a copper etchant Enstrip C made of Meltex is used.
(Product name) etching. In this etching process, etching is performed in just over etching time of 30%.

【００８７】つぎに硝酸セリウムアンモニウムとフェリ
シアン化カリウムと水酸化ナトリウムとの混合液によっ
て共通電極膜１８のバリヤ層および密着層であるクロム
（中層）、およびアルミニュウム（最下層）のエッチン
グをする。なおこのエッチング処理は、ジャストエッチ
ングから３０％のオバーエッチング時間でエッチングを
行う。この結果、下部電極１９を形成して突起電極２２
の頂部の中央部が周縁部に比べて２μｍ〜３μｍ低い半
導体装置を無機絶縁膜１７をもちいて形成する。このと
きの下部電極１９の平面パターン形状を図１０の点線に
しめす。Next, chromium (middle layer), which is a barrier layer and an adhesion layer, and aluminum (lowest layer) of the common electrode film 18 are etched with a mixed solution of cerium ammonium nitrate, potassium ferricyanide, and sodium hydroxide. In this etching process, etching is performed in just over etching time of 30%. As a result, the lower electrode 19 is formed and the projection electrode 22 is formed.
A semiconductor device whose central portion at the top is lower by 2 μm to 3 μm than the peripheral portion is formed using the inorganic insulating film 17. The planar pattern shape of the lower electrode 19 at this time is shown by a dotted line in FIG.

【００８８】つぎに、ダイシング工程により半導体基板
１２を単個の半導体チップに切断を行う。Next, the semiconductor substrate 12 is cut into single semiconductor chips by a dicing process.

【００８９】その後、図９にしめすように、導電性材料
３２を混在させた異方性導電接着剤３４を複数の突起電
極２２を有する半導体基板１２と対面配置した複数の回
路電極２８を有する回路基板２６との間に介在させる。
その後、突起電極２２と回路電極２６間に４００Ｋｇ／
ｃｍ 2の圧力で加圧しながら１８０〜２２０℃の温度で
加熱を加える。Thereafter, as shown in FIG. 9, a circuit having a plurality of circuit electrodes 28 in which an anisotropic conductive adhesive 34 in which a conductive material 32 is mixed is arranged facing the semiconductor substrate 12 having a plurality of projecting electrodes 22. It is interposed between the substrate 26.
Then, 400 kg / g between the protruding electrode 22 and the circuit electrode 26.
Heating is applied at a temperature of 180 to 220 ° C. while applying a pressure of cm 2 .

【００９０】このように第３の実施の形態では、無機絶
縁膜１７の外側に有機絶縁膜１５を形成する。突起電極
２２の頂部の中央部と周縁部の段差は有機絶縁膜１５で
制御する。このように本発明では、有機絶縁膜１７の膜
厚を制御する簡便な工程により、半導体装置を提供する
ことが可能である。As described above, in the third embodiment, the organic insulating film 15 is formed outside the inorganic insulating film 17. The step between the central portion and the peripheral portion of the top of the bump electrode 22 is controlled by the organic insulating film 15. As described above, according to the present invention, a semiconductor device can be provided by a simple process of controlling the thickness of the organic insulating film 17.

【００９１】なお以上の説明では、突起電極２２の平面
パターン形状は四角形で説明したが四角形以外に突起電
極２２平面形状は、六角形や、八角形や、円形状でも有
効である。このような平面パターン形状の半導体装置で
も、突起電極２２頂部の中央部が周縁部より低い構造に
することによって、異方性導電接着剤３４の接続加圧時
に発生する突起電極と回路電極間の導電性材料３２の流
れだしを防止、し突起電極２２と回路電極２８間の導電
性材料３２の数を充分に確保し、接続信頼性を向上させ
ることができる。In the above description, the planar pattern shape of the projecting electrode 22 has been described as a square, but other than the square, the planar shape of the projecting electrode 22 may be a hexagon, an octagon, or a circle. Even in a semiconductor device having such a flat pattern shape, by forming a structure in which the central portion of the top of the protruding electrode 22 is lower than the peripheral portion, the distance between the protruding electrode generated when the anisotropic conductive adhesive 34 is connected and pressed and the circuit electrode is reduced. The flow of the conductive material 32 can be prevented, the number of the conductive materials 32 between the protruding electrode 22 and the circuit electrode 28 can be sufficiently ensured, and the connection reliability can be improved.

【００９２】このようにして本発明により形成した半導
体装置は接続面積を小さくして、接続ピッチの微細化と
高信頼性のある半導体装置および製造方法とその接続構
造を提供することが可能となる。The semiconductor device formed according to the present invention as described above can reduce the connection area and provide a semiconductor device having a fine connection pitch and high reliability, a manufacturing method, and a connection structure thereof. .

【００９３】さらに本発明は工程上大きな変更すること
なく突起電極２２頂部の中央部分が周辺部に比べて低い
構造を簡便に形成することができ、工業生産上非常に有
効な半導体装置と製造方法および接続構造を提供でき
る。Further, according to the present invention, it is possible to easily form a structure in which the central portion of the top of the protruding electrode 22 is lower than the peripheral portion without any major change in the process. And connection structure can be provided.

【００９４】[0094]

【発明の効果】以上の説明で明らかなように、本発明の
半導体装置の構造と製造方法およびその接続構造におい
ては突起電極頂部の中央部が周縁部よりも低くする。こ
のことによって、突起電極と回路電極間の導電性材料が
接続加圧されたときに、異方性導電接着剤の流動ととも
に流れ出すのを抑え、突起電極と回路電極との間の導電
性材料を充分な数が確保できる。As is apparent from the above description, in the structure, the manufacturing method, and the connection structure of the semiconductor device of the present invention, the center of the top of the protruding electrode is lower than the periphery. This suppresses the conductive material between the protruding electrode and the circuit electrode from flowing out together with the flow of the anisotropic conductive adhesive when the connection material is pressurized, and reduces the conductive material between the protruding electrode and the circuit electrode. A sufficient number can be secured.

【００９５】さらに本発明の半導体装置においては、充
分な導電性材料を確保することができるため突起電極面
積を小さくすることができ、微細ピッチでしかも高信頼
性の接続を提供する。Further, in the semiconductor device of the present invention, since a sufficient conductive material can be secured, the area of the protruding electrode can be reduced, and a highly reliable connection with a fine pitch can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態における半導体装置および製
造方法を示す断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device and a manufacturing method according to an embodiment of the present invention.

【図２】本発明の実施形態における半導体装置および製
造方法を示す断面図である。FIG. 2 is a cross-sectional view illustrating a semiconductor device and a manufacturing method according to an embodiment of the present invention.

【図３】本発明の実施形態における半導体装置および製
造方法を示す断面図である。FIG. 3 is a cross-sectional view showing a semiconductor device and a manufacturing method according to the embodiment of the present invention.

【図４】本発明の実施形態における半導体装置および製
造方法を示す断面図である。FIG. 4 is a cross-sectional view showing a semiconductor device and a manufacturing method according to the embodiment of the present invention.

【図５】本発明の実施形態における半導体装置と、製造
方法およびその接続構造を示す断面図である。FIG. 5 is a cross-sectional view illustrating a semiconductor device, a manufacturing method, and a connection structure thereof according to an embodiment of the present invention.

【図６】本発明の実施形態における半導体装置および製
造方法を示す平面図である。FIG. 6 is a plan view showing the semiconductor device and the manufacturing method according to the embodiment of the present invention.

【図７】本発明の第２の実施形態における半導体装置と
その接続構造を示す断面図である。FIG. 7 is a cross-sectional view illustrating a semiconductor device and a connection structure thereof according to a second embodiment of the present invention.

【図８】本発明の第２の実施形態における半導体装置お
よび製造方法を示す平面図である。FIG. 8 is a plan view illustrating a semiconductor device and a manufacturing method according to a second embodiment of the present invention.

【図９】本発明の第３の実施形態における半導体装置と
その接続構造を示す断面図である。FIG. 9 is a cross-sectional view illustrating a semiconductor device and a connection structure thereof according to a third embodiment of the present invention.

【図１０】本発明の第３の実施形態における半導体装置
および製造方法を示す平面図である。FIG. 10 is a plan view illustrating a semiconductor device and a manufacturing method according to a third embodiment of the present invention.

【図１１】従来の技術における半導体装置および製造方
法を示す断面図である。FIG. 11 is a cross-sectional view showing a semiconductor device and a manufacturing method according to a conventional technique.

【図１２】従来の技術における半導体装置および製造方
法を示す断面図である。FIG. 12 is a cross-sectional view showing a semiconductor device and a manufacturing method according to a conventional technique.

【図１３】従来の技術における半導体装置および製造方
法を示す断面図である。FIG. 13 is a cross-sectional view showing a semiconductor device and a manufacturing method according to a conventional technique.

【図１４】従来の技術における半導体装置および製造方
法を示す断面図である。FIG. 14 is a cross-sectional view showing a semiconductor device and a manufacturing method according to a conventional technique.

【図１５】従来の技術における半導体装置とその製造方
法およびその接続構造を示す断面図である。FIG. 15 is a cross-sectional view showing a conventional semiconductor device, a method of manufacturing the same, and a connection structure thereof.

【符号の説明】[Explanation of symbols]

１２ 半導体基板 １４ 電極パッド １５ 有機絶縁膜 １６ 絶縁膜 １７ 無機絶縁膜 １８ 共通電極膜 １９ 下部電極 ２０ 感光性樹脂 ２２ 突起電極 ２６ 回路基板 ２８ 回路電極 ３２ 導電性材料 ３４ 異方性導電接着剤 Reference Signs List 12 semiconductor substrate 14 electrode pad 15 organic insulating film 16 insulating film 17 inorganic insulating film 18 common electrode film 19 lower electrode 20 photosensitive resin 22 projecting electrode 26 circuit board 28 circuit electrode 32 conductive material 34 anisotropic conductive adhesive

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 電極パッド上の周縁部に開口部を有する
絶縁膜と、電極パッド上に設ける下部電極膜と、突起電
極とを有する半導体装置であって、 突起電極の頂部は中央部が周縁部より低いことを特徴と
する半導体装置。1. A semiconductor device comprising: an insulating film having an opening at a peripheral portion on an electrode pad; a lower electrode film provided on the electrode pad; and a protruding electrode, wherein a top portion of the protruding electrode has a peripheral portion at the center. A semiconductor device characterized by being lower than a part. 【請求項２】 請求項１記載の半導体装置であって、 絶縁膜は無機膜と有機膜との２層からなり、 突起電極の中央部と周縁部の段差と絶縁膜の膜厚とがほ
ぼ同じであることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the insulating film comprises two layers of an inorganic film and an organic film, and a step between a central portion and a peripheral portion of the projecting electrode and a film thickness of the insulating film are substantially equal. A semiconductor device, which is the same. 【請求項３】 請求項２記載の半導体装置であって、 電極パッド周縁部の無機絶縁膜と有機絶縁膜との形状は
ほぼ同一形状であり、 突起電極の中央部と周縁部の段差と絶縁膜の膜厚とがほ
ぼ同じであることを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the shape of the inorganic insulating film and the shape of the organic insulating film at the peripheral portion of the electrode pad are substantially the same, and the step between the central portion and the peripheral portion of the protruding electrode is insulated. A semiconductor device, wherein the thickness of the film is substantially the same. 【請求項４】 請求項２記載の半導体装置であって、 絶縁膜は無機膜と有機膜との２層からなり、 有機膜の電極パッド周縁部の形状は無機膜より外周部に
配置し、 突起電極の中央部と周縁部の段差と有機膜の膜厚とがほ
ぼ同じであることを特徴とする半導体装置。4. The semiconductor device according to claim 2, wherein the insulating film is composed of two layers, an inorganic film and an organic film, and the shape of the peripheral portion of the electrode pad of the organic film is arranged on the outer peripheral portion of the inorganic film. A semiconductor device, wherein a step between a central part and a peripheral part of a protruding electrode and a film thickness of an organic film are substantially equal. 【請求項５】 請求項１記載の半導体装置であって、 絶縁膜は無機膜からなり、 突起電極の中央部と周縁部の段差と無機膜の膜厚とがほ
ぼ同じであることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the insulating film is made of an inorganic film, and a step between a central portion and a peripheral portion of the projecting electrode and a film thickness of the inorganic film are substantially the same. Semiconductor device. 【請求項６】 請求項１記載の半導体装置であって、 絶縁膜は有機膜からなり、 突起電極の中央部と周縁部の段差と有機膜の膜厚とがほ
ぼ同じであることを特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the insulating film is made of an organic film, and a step between a central portion and a peripheral portion of the bump electrode and a film thickness of the organic film are substantially the same. Semiconductor device. 【請求項７】 電極パッド上に突起電極の中央部と周縁
部の段差と絶縁膜の膜厚とが同じ膜厚をもつ絶縁膜の開
口を有する半導体装置上に共通電極膜を全面に形成する
工程と、 感光性樹脂をパターンニングする工程と、 感光性樹脂表面を親水化処理する工程と、 感光性樹脂開口部に突起電極を形成する工程と、 感光性樹脂を除去する工程と、 共通電極膜を突起電極をマスクにしてパターンニングす
る工程とを有することを特徴とする半導体装置の製造方
法。7. A common electrode film is formed on the entire surface of a semiconductor device having an insulating film opening having the same thickness as the insulating film with a step between the central portion and the peripheral portion of the projecting electrode on the electrode pad. A step of patterning the photosensitive resin, a step of hydrophilizing the surface of the photosensitive resin, a step of forming a protruding electrode in the opening of the photosensitive resin, a step of removing the photosensitive resin, and a common electrode. Patterning the film using the protruding electrode as a mask. 【請求項８】 電極パッド上の周縁部に開口部を有する
絶縁膜と電極パッド上に設ける下部電極膜と突起電極と
を有する半導体装置の接続構造であって、 突起電極の頂部は中央部が周辺部より低く、導電性材料
が突起電極の凹部に確保され対面する回路電極と接続す
ることを特徴とする半導体装置の接続構造。8. A connection structure of a semiconductor device having an insulating film having an opening at a peripheral portion on an electrode pad, a lower electrode film provided on the electrode pad, and a protruding electrode, wherein the top of the protruding electrode has a central portion. A connection structure for a semiconductor device, which is lower than a peripheral portion, wherein a conductive material is secured in a concave portion of a protruding electrode and is connected to a facing circuit electrode. 【請求項９】 請求項８の半導体装置の接続構造であっ
て、 導電性材料の粒径は、突起電極頂部の段差寸法より大き
いことを特徴とする半導体装置の接続構造。9. The connection structure for a semiconductor device according to claim 8, wherein a particle size of the conductive material is larger than a step size at a top of the protruding electrode. 【請求項１０】 請求項８の半導体装置の接続構造であ
って、 導電性材料の粒径は、突起電極頂部の段差寸法とほぼ同
じか小さいことを特徴とする半導体装置の接続構造。10. The connection structure for a semiconductor device according to claim 8, wherein a particle size of the conductive material is substantially the same as or smaller than a step size at the top of the bump electrode.
JP9097170A 1997-04-15 1997-04-15 Semiconductor device and its manufacturing method and connection structure Pending JPH10289908A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9097170A JPH10289908A (en) 1997-04-15 1997-04-15 Semiconductor device and its manufacturing method and connection structure

Publications (1)

Publication Number Publication Date
JPH10289908A true JPH10289908A (en) 1998-10-27

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ID=14185116

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818539B1 (en) 1999-06-30 2004-11-16 Seiko Epson Corporation Semiconductor devices and methods of fabricating the same
JP2007242761A (en) * 2006-03-07 2007-09-20 Seiko Epson Corp Method for manufacturing semiconductor device
JP2008004966A (en) * 2007-09-25 2008-01-10 Seiko Epson Corp Terminal electrode, semiconductor device, module and electronic apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818539B1 (en) 1999-06-30 2004-11-16 Seiko Epson Corporation Semiconductor devices and methods of fabricating the same
US7285863B2 (en) 1999-06-30 2007-10-23 Seiko Epson Corporation Pad structures including insulating layers having a tapered surface
JP2007242761A (en) * 2006-03-07 2007-09-20 Seiko Epson Corp Method for manufacturing semiconductor device
JP2008004966A (en) * 2007-09-25 2008-01-10 Seiko Epson Corp Terminal electrode, semiconductor device, module and electronic apparatus

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