JPH10285461A - Video signal processing unit for prompter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a processing unit at a low cost by using a microcomputer whose processing speed is not fast. SOLUTION: An up-counter 21 as an address counter is used for an original memory 12 that stores original image data, and a CPU 20 is connected to the up-counter 21. Then a head address of a horizontal line is set to the up-counter 21 from input output ports of the CPU 20 for a horizontal blanking period and the head address is incremented by the up-counter 21 with a clock signal for an image data valid period. Thus, the CPU 20 has only to set the head address of the horizontal line and then the address is controlled with the inexpensive CPU at a low speed, without the use of a high speed CPU that has been required for a conventional processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus of a prompter for displaying a manuscript to be read by a newscaster or the like, and to a structure for controlling an address required for writing / reading image data of a manuscript memory. .

[0002]

2. Description of the Related Art A prompter stores original image data photographed by an original camera or the like in a memory, and allows an original read from this memory to be displayed on a display during broadcasting. Control of writing / reading of the memory is performed by designating an address of the memory via an address bus.

FIG. 4 shows a conventional configuration for address control, for example, an SRAM (Static Ran).
A high-speed CPU (microcomputer) 2 is connected to a document memory 1 composed of a dom access memory via an address bus. According to the high-speed CPU 2, an address signal for each pixel is output at a high speed via the address bus, and the image memory 1 is output.
Write image data to the specified address of
The image data at the specified address is read. In this manner, a predetermined number of document images can be stored in the document memory 1, output as needed, and displayed on the display.

[0004]

However, the above-mentioned high-speed CPU 2 is expensive, and the use of this high-speed CPU 2 to construct a video signal processing apparatus has a problem that the cost of the prompter apparatus is high. That is, if the address can be set using a CPU (microcomputer) that does not operate at high speed, the device can be manufactured at low cost.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a video signal processing device of a prompter which can be manufactured at low cost by using a microcomputer which is not high speed.

[0006]

In order to achieve the above object, the present invention writes image data in a document memory,
A video signal processing device of a prompter for reading image data from the original memory; a microcomputer for outputting a head address of horizontal line data from an input / output port during a horizontal blanking period of the video signal; An address counter which is connected via an address bus, sets the head address output from the microcomputer, and increases or decreases (increments or decrements) the address of a horizontal line by a clock signal during the image data valid period of the video signal. And a logic circuit as above.

According to the above configuration, an up counter (or a down counter) is provided as the logic circuit, and the microcomputer sets the head address (value) of the horizontal line to the up counter during the horizontal blanking period. Thereafter, in the up counter, the value is incremented from the head address by the input clock signal, and the address data is output to the image memory via the address bus. Therefore, writing and reading to and from the memory are performed by the address set / designated by the clock signal in the up counter, and the microcomputer does not need to directly set the address at a high speed.

[0008]

FIG. 1 shows a circuit configuration of a video signal processing apparatus of a prompter according to an embodiment, and FIG.
FIG. 3 shows an operation of signal processing, and FIG. 3 shows a setting state of an address in the memory. First, in FIG. 1, a video input terminal 10 inputs a composite video signal of a document photographed by a document camera. A document memory such as an SRAM or the like is connected to the video input terminal 10 via an A / D converter 11. 12 is connected to this memory 12
Is stored with the document image data. This original memory 12
Is connected to a video amplifier 14 via a D / A converter 13, and a video signal amplified by the video amplifier 14 is output from a video output terminal 15 to a display.

On the other hand, the video input terminal 10 is connected to a sync separation circuit 17 for separating a synchronizing signal from a composite video signal, and a timing generator 18 for forming various timing signals is connected to the sync separating circuit 17. The timing signal from the timing generator 18 is supplied to each circuit as shown. In this example, a CPU 20 constituted by, for example, an 8-bit one-chip microcomputer is provided.
An up-counter (logic IC circuit) 21 as an address counter is connected to an input / output (I / O) port of the device. The up-counter 21 is connected to the document memory 12 via an address bus.

In this example, the composite video signal input to the video input terminal 10 is a signal including a synchronizing signal as shown in FIG. 2 (A). At 17, the synchronizing signal is separated and the timing signal is output from the timing generator 18 as shown in FIG.
The horizontal blanking signal shown in FIG. As shown in the horizontal blanking signal, the composite video signal has a blanking period H1 of about 10.9 μs.
And an image data valid period (period for substantially forming an image) H2 of about 51.1 μs.

In the timing generator 18, a timing signal in which a clock signal exists during the image data valid period H2 of the horizontal blanking signal is formed.
As shown in FIG. 3, if one image in the memory 12 has an address width (value) of 365 in the horizontal direction as shown in FIG. 3, 51.1 μs / 365 =
The signal has a cycle of 0.14 μs (which is a cycle of the subcarrier frequency 2fsc).

As shown in FIG. 3, on the display screen of the prompter, for example, the 21st horizontal line to the 262nd horizontal line are set as data of one screen. Therefore, in this case, addresses (values) 1 to 1 are stored in 21 lines.
Addresses 366 to 730 are allocated to 365 and 22 lines, and addresses are sequentially set up to 262 lines.

From the CPU 20, the head address of the horizontal line is set in the up counter 21 via the I / O port. For example, an address (value) = 1 is set for the 21 lines. Then, the up counter 21 changes the address value to 2, 3, 4... 36 by the clock signal shown in FIG.
Since it is incremented as 5, the addresses of the document memory 12 are sequentially specified via the address bus. Similarly, for the above 22 lines, 366, 3
.. 730 are designated, and thus the addresses are designated sequentially up to 262 lines.

In addition, at the same time as the above-mentioned address designation, the A / D converter 11
The image data of the effective period H2 of (A) is sequentially input, and each pixel data is sequentially written to the designated address. On the other hand, even when displaying the original, if the CPU 20 sets the top address in the up counter 21, the addresses of the horizontal lines are sequentially specified based on the clock signal, and the pixel data of the specified address is sequentially read. Thus, the document image is displayed on the display.

As described above, according to the embodiment, the CPU 20 only needs to set the start address of the horizontal line, and the address can be controlled by a low-speed CPU without using a conventional high-speed CPU. Becomes

In the above example, the case where the address is incremented by the up counter 21 has been described. However, in the case where the setting of the address number is reversed, the same operation as described above is performed by decrementing using the down counter. There is also a way to make it work.

[0017]

As described above, according to the present invention,
A microcomputer that outputs the head address of the horizontal line from the input / output port during the horizontal blanking period, and sets the head address output from the microcomputer, and then increases or decreases the address of the horizontal line by a clock signal during the image data valid period. Since a logic circuit is provided, address control can be performed by a microcomputer that is not high-speed, and a video signal processing device of a prompter can be manufactured at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a video signal processing device of a prompter according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a processing operation in the circuit of FIG.

FIG. 3 is an explanatory diagram illustrating an address setting state of one image according to the embodiment.

FIG. 4 is a block diagram showing a configuration of an address control circuit of a conventional prompter video signal processing device.

[Explanation of symbols]

 1, 12: Document memory, 2: High-speed CPU, 18: Timing generator, 20: CPU, 21: Up counter (address counter).

Claims (1)

[Claims] An image data is written in a document memory,
A video signal processing device of a prompter for reading image data from the original memory; a microcomputer for outputting a head address of horizontal line data from an input / output port during a horizontal blanking period of the video signal; And a logic circuit as an address counter that sets the top address output from the microcomputer, sets the top address output from the microcomputer, and increases or decreases the address of a horizontal line by a clock signal during the image data valid period of the video signal. And a video signal processing device for a prompter.