JPH10285387A - Image-processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image-processing unit by which rotation processing of image data is attained, without the need for numerous times of area designation. SOLUTION: A scanner 101 is used to read a prescribed original, a display/ coordinate instruction section 104 displays data of the read original and designates an area for the read original. A storage section 105 stores the area data whose area is designated, an image-processing section 102 generates an area signal from the designated area data, and applies image-processing to the area signal. Since the area signal is generated by rotating it, a line buffer having a bit number by number of area processing kinds is provided and the area signal is rotated. Since the area signal is generated by taking rotation into account, even when area data designated before the rotation are stored, the area signal rotated in matching with the rotation of image data is generated, and only the area data are generated through arbitrary rotation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus for designating an area with a digital copying machine or the like and performing image processing on the area with respect to rotation of the area.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus generally converts region data into rotated data before writing the data in a memory when the region data is rotated.

[0003]

However, in the above conventional example, when image data is rotated, data in which an area is specified for the image data before rotation needs to be specified again. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus capable of performing rotation processing of image data without repeatedly specifying an area.

[0005]

In order to achieve the above object, an image processing apparatus according to the present invention comprises: reading means for reading a predetermined document; display means for displaying data of the read document; Means for designating an area by specifying an area, a memory for holding area data designating the area, an area signal generating means for generating an area signal from the designated area data, and an image processing apparatus for performing image processing on the area signal Is characterized in that a means for rotating and generating an area signal is provided with a line buffer having the number of bits corresponding to the number of types of area processing, and generating the area signal by rotating it.

The above-mentioned area generating means includes a plurality of areas to be subjected to the same image processing, and when the overlapping area is also an area, the area generating means is used as a rotating means when the overlapping is also an area. 1 line length in the main scanning direction x
A line buffer having the number of area types × the number of overlaps (bits) is provided, and the area signal is generated by rotating the area signal.
It is preferable to provide a line buffer for lines and a means for deleting unnecessary data of area data, and delete unnecessary data before rotating to generate an area signal.

In the above-mentioned rotating means, there is provided means for designating a part of the area designated before the rotation by a square.
It is preferable to provide means for performing a rotation area signal on the area data of only the designated part.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of an image processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings. FIG.
32 to 32 show an embodiment of the image processing apparatus according to the present invention.

<First Embodiment> An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the image processing apparatus. The image processing apparatus according to the present embodiment includes a scanner 101 that reads an image of a document as digital data of R, G, and B, an image processing unit 102 that performs processing such as processing on the read image data, and a processing of image data. An operation unit 103 for instructing a processing procedure and the like; a display / coordinate instructing unit 104 for displaying image data and a processing result and an area for performing a processing on a specific area; and an image processing unit 102 A storage unit 105 for storing area data for performing processing such as processing, a CPU 106 for controlling the entire apparatus, and a ROM 10 for storing parameters and control procedures for performing the control.
7 and a printer 108 for outputting a processing result.

FIG. 2 is an explanatory diagram for providing a detailed description of the image processing unit 102 of FIG. 2 corresponds to the image processing unit 102 in FIG. In this embodiment, R (red), G (green), and B (blue)
This is an example of a configuration in which four types of signals of Y (yellow), M (magenta), C (cyan), and K (black) are recorded and output on a transfer sheet by a printer by inputting different types of signals. is there.

In FIG. 2, reference numeral 201 denotes a scaling unit for performing main scanning magnification independently for R, G, and B; 202, an RGB γ correction unit for performing γ correction such as gray balance of R, G, and B; and 203, a lens system. An RGB filter 204 for performing MTF correction (sharpening) independently for R, G, and B in order to correct blur, etc. 204 is a create unit for performing image processing such as mirror, italic, shadowing, hollowing, painting, moving, and the like 205 Is a color correction unit that converts a data system from R, G, B to Y, M, C, K by a primary masking equation, 206 is a CMYK filter that performs film processing according to the MTF of the printer, and 207 is a printer. A CMYK γ correction unit 208 for performing γ correction in accordance with the γ characteristic of the gray scale processing unit 208 for performing halftone processing by dither processing or a density pattern method, wherein C, M, Y, and K are C ′,
M ', Y', K '(where the number of bits is C>C',M>
M ′, Y> Y ′, K> K ′).

Reference numeral 209 denotes an area signal generator for generating a signal for switching processing for each area; 210, a memory for storing information for generating an area signal; 211, a CPU;
It is. In the figure, only the connection with the area signal generation unit is illustrated to explain a portion related to the area signal. The connection of each process of the image processing unit is performed by the scaling unit 201 and the RGBγ correction 2
02, RGB filter 203, create 204, color correction 205, CMYK filter 206, CMYKγ correction 2
07 and the gradation processing 208.

The area signal generator 209 includes a scaling unit 201,
The memory 210 is connected to the CPU 211. The scaling unit 201 generates an area signal in synchronization with the image data from the scanner 101. CPU 211 performs control for writing data in the area specified by display / coordinate instructing section 104, and stores the area data in memory 210.

The switching of the processing by the area signal can be arbitrarily defined as, for example, the area signal No. 0 is a normal processing, the area signal No. 1 is a mirror, and the area signal No. 2 is an inversion.

The memory 210 is a bitmap memory for storing information of an area for performing image processing on a specific area of the document image. The area information has n bits of information for one dot of the document image. n
The information amount of the bit is a value that allows the regions to be distinguished when a plurality of specific regions perform respective processes. That is, 2
Is the value that can be distinguished. When the eight types of processing are distinguished, the area data from 0 to 7 can be represented by 2 to the third power (3 bits). The more processing areas to be distinguished, the more memory capacity is required. For example, the original image size A3 (297 mm × 420 mm), density 16 pixels /
In order to perform 8 types of processing with a designated area in mm, the memory is set to 32 × 3 Mbit.

The case where a region signal is generated will be described. Original image data from the scanner 101 is displayed on the display / coordinate instruction unit 104. When processing is performed on a specific range of the document image data, the display / coordinate indicating unit 1
From 04, an area within the range is designated as an area 1 (302) shown in FIG. In order to perform various image processing on the inside and outside 301 and 302 of the designated area,
It is necessary to generate an area signal for discrimination. Therefore, the designated area is stored in the bitmap memory with a number different from the outside area 301. As a storage method, as shown in FIG. 3B, only the edge 303 in the main scanning direction of the area is written in the memory, and a signal for distinguishing the area from the outside is generated by hardware processing.

For example, when data having information of "1" is stored in a bit map memory as an area, only the edge in the main scanning direction of the area is used as area data as shown in FIG. It is memorized. Here one grid is 1
It has the capacity to distinguish the area corresponding to the dot. Although not shown in the figure, blanks are "0" data.

The stored area data is sequentially read in the main scanning direction at the time of processing, and when one line has been read, it is shifted by one in the sub-scanning direction, and is sequentially read in the main scanning direction.

When the read data is other than "0", it is area data, and the area number represented by the area data is changed. When the area signal is Hi, L
ow, and if Low, it is changed to Hi ((b) in FIG. 4). A signal is generated for each area number. Outside the area is “0”. However, this process is not performed on the “0” data.

However, the area signal of each number generated as described above is any one of the area numbers. If there is an overlap in the area signal (broken line portion in FIG. 5), the state of the bit map memory is as shown in FIG. In the signal generated from the data stored in this way, a signal is generated at the position of the overlapping portion 502 as indicated by 504 in FIG. At the position of the non-overlapping portion 501, a signal 503 is generated.

When different numbers overlap, processing is performed in accordance with a preset priority. In the priority order processing, as shown in FIG. 7, it is assumed that two areas have different area numbers, and the area 1 and the area 2 are designated to overlap (601). The designated area is stored in the bitmap memory as shown in FIG. The areas 1 and 2 indicated by the arrows are output from the area signal generation as information such as 602 and 603, respectively. The output signal of FIG. 8A generates a signal in accordance with the priority processing. Here, an example in which the value of the region number having a large value is given a higher priority. The signal of the overlapped portion 602 in the area output is the output result of 603 because the area 2 is given priority over the area 1 and output.

When the image data is rotated by 90 ° and 270 ° in the system for generating such an area, the held area data is rotated accordingly. Alternatively, a method of arbitrarily rotating only the region data will be described.

The memory access method will be described. As shown in FIG. 9, the connection configuration between the area generation processing unit and the memory (DRAM) includes four memory banks 701, 702, 703, 7
04, two 16-bit data buses 705 and 706, the address control signal line 707 is common, and the control signal line 70
8, 709, 710, and 711 are the configurations that each has.

As shown in FIG. 10, the four memory banks are mapped for each line, and are controlled by switching the banks for each line. Line 0 uses bank 0, line 1 is bank 2, line 2 is banks 1, 3,
The line is a form using bank 3.

When the memory bank 0 on the 0th line is accessed, the data bus 705 is used, so that the data bus 706 on the banks 1 and 3 is not accessed. The bank 2 uses the data bus 705 by the memory access of the bank 0, so that data is controlled so as not to collide. The access is sequentially performed for each line in the order of bank 0 → bank 2 → bank 1 → bank 3 → bank 0.

FIG. 11 is a simplified block diagram of the address generation circuit. An address is obtained by adding 903 the value of the count 901 in the main scanning direction by clk (clock) and the value of the sub-scanning direction adder 902 that adds the length of the main scanning for every four Lsyncs (line synchronization). Lsync4
Each count is performed by a 4-line counter (2-bit counter) 904, and the CR (carriage return) is input to the adder 902 in the sub-scanning direction. However, the count in the main scanning direction is increased by one for several clks in control.

The shift signal line sets a read start address. The switching control of the memory bank is performed by a 4-line count (904). That is, when the value of the 4-line counter is 0, the bank 0 is decoded. When the value is 1, the bank 2 is decoded.
In the case of, bank 3 is set.

A memory access method during rotation will be described.
Although a block diagram of address generation for each rotation angle is not shown, an access procedure will be briefly described. When the normal access accesses the memory in the order shown by the arrow in FIG. 12A, FIG.
(C) of FIG. 2 is a readout of 180 ° rotation, and (d) of FIG.
Is readout at 270 ° rotation.

When reading with the memory configuration of FIG.
The memory access at the time of rotation may be performed by adding the value counted down by Lsync in the order of clk in the arrow direction 1001 in FIG.
That is, Lsyn to the 4-line counter in FIG.
c input becomes clk, and clk to main scanning direction counter
The input becomes Lsync and counts down.

Similarly, at the time of 180 ° rotation, FIG.
Count down with clk in the arrow direction 1002 of,
The addition of the value counted down by Lsync is used as an address. That is, the main scanning direction counter in FIG. 11 counts down.

At the time of 270 ° rotation, the countdown is performed by clk in the arrow direction 1003 in FIG. 12D, and the addition of the value counted up by Lsync is used as an address. That is, L to the 4-line counter in FIG.
The sync input becomes clk. Main scanning direction counter c
The lk input becomes Lsync and counts down. Naturally, the read address of the memory is set from the shift signal line in accordance with each rotation. Controlling the address in this way enables rotation.

A method of rotating area data when performing memory control as described above will be described. As described above, the area data includes only edges in the main scanning direction as data in consideration of sequentially reading out the bit map memory in the main scanning direction.

When the image data is rotated or the region data is arbitrarily rotated, the region signal generated by rotating the region data shown in FIG.
3. As shown in FIG. 14, the area is not rotated. However, if you know that it will rotate in advance,
Data may be written in consideration of rotation. That is, in this case, the data is only the edge in the sub-scanning direction. Here, it is assumed that the written area data is rotated. Therefore, it is necessary to generate the area data in consideration of the rotation.

As a means for generating the area data in consideration of the rotation, a line memory having a capacity equal to the length in the main scanning direction after rotation × the number of bit widths of the area type is provided. For example,
When the area type is 8 with 3400 dots length in the main scanning direction after rotation, a line memory of 3400 × 8 bits is provided. Bit width of line memory (Fig. 15
Each bit 1202 of 1201) is used as an area number flag, and 1203 corresponds to each dot.

The area data written as shown in FIG. 16 is rotated and read. The flag is changed according to the value 1303 of the bit corresponding to the data 1302 of the line memory corresponding to the read data 1301. Flag is 0
1 (H) for (L) and 0 (L) for 1 (H). However, the area number 0 is not changed.

When data such as 1305 is read out, the value of 1304 is already stored as a flag in the line memory.
Write the value to memory as follows. At the same time, a signal of each area number is generated with this change as it is as a signal (130).
7). Although the data of the next line at the position of 1305 is all “0”, the same signal as 1307 is generated because the line memory is held in a state like 1306. When processing is performed in this manner, all data changes to "0" at the position of 1308 (1309). With this processing method, rotated area data can be generated.

<Second Embodiment> In the area generating method according to the first embodiment, when the area data of the same number does not overlap, it is not generated as an area signal as shown in FIG. 6B. As a method of coping with the overlapping of the areas, there is a method of writing data in a state where the inside of the area is filled, instead of writing only the edge portion of the area data as data. This method has a drawback that the data amount is increased every time a region is designated, so that the data amount increases and processing time is required. As another method, the data of the edge portion is provided with a flag, and the flag is counted. FIGS. 17 to 19 show examples of the area data description when the data flag is provided. When the area type is 8, 3 bits (14
01) and the flag 1 bit (1402), for a total of 1
This is equivalent to a dot. The start data of the area data “1” has a value as indicated by 1403.

The flag distinguishes between start and end. The start flag counts up, and the end flag counts down. By generating a region signal when the count value is not 0, it is possible to cope with the overlap.

As shown in FIG. 19, one line of data 1501 is described as start (s), start (s), end (e), and end (e). The start and end are always one set of two data. Thus, in the case of the data of (s) (s) (e) (e), the value of the counter becomes 1 → 2 → 1 → 0 (1502). By generating a region in a portion other than 0, a region signal can be generated as shown by 1503, and the overlapping portion is also within the region.

A method of rotating area data corresponding to such area data overlap will be described.

As a configuration, a line buffer as a rotation process is provided with a buffer which is the same as that of the first invention and further has a capacity corresponding to the number of lines. That is, the buffer has a capacity of the length in the sub-scanning direction after rotation × the number of areas × the number of overlaps as a buffer. For example, when the sub-scanning direction is 3400 dots, the number of areas is 8, and the overlap is 3, a capacity of 3400 × 8 × 2 bits is required.

The processing in this configuration is described in FIGS.
As described above, the area data written in the bit map is rotated and read. The counter value corresponding to the read area data is read from the line buffer. The counter value corresponding to the data 1601 read from the bit map is the position 1602 where the area data of 1602 where the data relating to the area data “1” of the line buffer is held is read.
The value of 1604 is the same position as 3.

The processing from 1605 to 1609 will be specifically described. The data read from the bitmap is 1
The line 605 is the state shown in FIG. 1
At the position where the region data "1s" exists in the line 606, the counter value is written as 1 in the buffer of the region data 1 as shown in FIG. At the same time, if the counter value is not "0", an area signal is output. Area 1
Signal becomes like 1701. The value is held before the line of 1607, and in the line of 1607,
Since there is area data of "1s", the count is incremented at each position to "2" ((c) in FIG. 22).

The signal in the area 1 is as shown by 1702. Similarly, the value of the counter is held up to the position before the line 1608, and since there is the area data “1e” in the line 1608, it is counted down at each position (FIG. 2).
2 (d)). The signal in the area 1 is as shown by 1703.
Until the line before 1609, the count value is held as it is, and since there is the area data of "1e" in 1609, it is counted down at each position to "0" ((e) in FIG. 22). The signal in the area 1 is as shown by 1704.

Looking at 1610 and 1611, the change in the counter value is 0 → 0 → 1 → 1 → 0, 0 → 1
→ 2 → 1 → 0. Here, the case where the signal of only the area 1 changes has been described, but other area signals also change with data. As described above, a region signal is generated according to the priority order. However, data 0 is not changed. By such processing, rotation of the area data corresponding to the overlap can be performed.

<Third Embodiment> As in the second embodiment, as a method for coping with overlapping of areas, a method of rotating area data after deleting unnecessary area data will be described. The configuration is such that a line memory having a capacity of the length in the main scanning direction before rotation × 2 lines × the number of bit widths of the area type is provided in place of the line buffer of the present invention.

For example, the length 480 in the main scanning direction after rotation
When there are eight types of areas with 0 dots, 4800 × 2
It will have a × 8-bit line memory.

For data having a distinction between start and end as area data, rotation is performed after data is developed once and unnecessary data is deleted. After the rotation, the same processing as in the first invention may be performed. At this time, the line buffer used before rotation is common.

In order to expand the data before rotation, the memory access is made in the above-mentioned alternative method. The memory access method for generating the area data when the rotation is not performed has been performed line by line. Here, it is performed every two lines. In the bit map shown in FIG. 23, the memory banks corresponding to lines 0 and 1 are 0 and 2. The banks 0 and 2 are accessed simultaneously to read data. Simultaneous access is possible with the above-described connection configuration between the area generating unit and the memory. The read data is written to the line buffer each time.

With this access method, processing of two lines can be performed by accessing one line. Naturally, two circuits for generating the area signal from the area data for the area generating unit are required, and the processing is performed in parallel. FIG. 24 shows the processing flow. The processing described below is for two lines simultaneously. In step 1, data is read from the bitmap data. s
In step 2, the read data includes start / end information. An area signal is generated as the area overlap. The area signal is converted into only edge data.

In the conversion method using only edge data, for example, a signal of an edge portion shown in FIG. 25B is created for a region signal shown in FIG. Data other than the edge portion is deleted (201). The signal at the edge is
It is created from the circuit of FIG. Area data 210 in FIG. 26
2 is decoded by the decoder 2103 into data for each area number. Here, the case of the area 1 is taken as an example. An AND signal of the decoded data and the start (s) / end (e) flag data 2101 becomes an UP signal, and an AND signal 2105 of the inverted signal of the decoded data and the s / e flag data 2101 becomes a DOWN signal.

The UP / DOWN signal indicates that the U of each area number is
The P / DOWN counter 2106 counts the flag of the area signal. The 2107 comparator compares whether the output of the UP / DOWN counter 2106 is 0 or not. If the comparison result is not "0", it becomes a Hi signal. For example, the data of the line indicated by the arrow in FIG.
The result is as follows. This data is input as data (D) of the flip-flop 2108.

The inverted output / Q of 2108 is input to the data (D) of the flip-flop of 2109. The output Q from the flip-flop 2108, the inverted output / Q of the flip-flop 2109 and the output of the AND 2110,
Inverted output / Q from flip-flop 08 and 2109
The output of the AND 2111 of the output Q of the flip-flop is OR data, and the OR 2112 is edge data as shown in FIG. The inversion of the edge data and the AND of the area data become an unnecessary data portion 2001 in the area. The data at this timing (Hi signal) is “0”.

In step 3, since the data generated in step 2 is the area data of only the edge portion, it is written into the line buffer as it is. In step 4, the data written to the line buffer is written to the bitmap memory. In terms of time, two lines are processed at one time, so steps 1 to 3 are the processing time for one line in the main scanning direction, and step 4 is the processing time for one line in the main scanning direction.

The area data from which unnecessary data has been deleted by such processing is held in the bit map. By performing the same processing on this data as in the first invention, it is possible to cope with the case where the areas overlap.

<Fourth Embodiment> When an output result obtained by partially rotating the image data shown in FIG. 27A as shown in FIG. 27B is obtained, the area data is also adjusted accordingly. A method of partially rotating will be described. As shown in FIG. 28, the user specifies the range of the region to be rotated. For the specified area, position information of a diagonal point of the range 2301 is obtained. The position information is obtained as (Xs, Ys) and (Xe, Ye) as coordinate values with the origin (0, 0) at the upper left. From this position information, a gate signal (Xgate) in the range from Xs to Xe is created in the main scanning direction.

As this signal is generated for each line, position information (Xs, Ys) and (Xe, Ye) are stored and held (2401 in FIG. 29). Similarly, in the sub-scanning direction, a gate signal (Ygate) in the range of Ys to Ye is created and generated (2402 in FIG. 29). The signal in the effective range of gate is Hi.

The procedure for reading from a bitmap will be described. FIG. 30 shows the order of reading from the bitmap, and reading is performed in the direction of the arrow. As shown in FIG.
The selector 2604 selects an address in the order of reading according to the result of the AND 2601 between Xgate and Ygate. The address to be selected is the normal address generation 2
602 and address generation 2603 during rotation. The generation of addresses during rotation is the same as described above, and a description thereof will be omitted. Reference numeral 2603 has 90 °, 180 °, and 270 ° circuits.

The timing of the generation of the address of the rotating part is adjusted by making the object of the rotating area a square. Also,
As shown in FIG. 32, the start of the rotation address generation is performed at a timing 2701 at which Xgate changes from low to high. For example, 2501 in FIG.
When reading from the bit map of the area data in the line of 回 転 か の 信号 信号 信号 信号 信号 回 転 信号 信号 信号 信号 信号 信号 回 転 信号 信号 信号 信号 信号 信号 信号 信号 信号. Is selected.

At the position 2503, the signal 2601 selects the data of the address generation during rotation. At this time, the address generation 2603 during rotation includes 2701 in FIG.
Is input. This signal starts address generation. To generate an address, the rotation direction (90
°, 180 °, 270 °) as a signal 2606
And the read start address 2607 are input. The read start address 2607 is, for example, 2 in the case of 90 ° rotation.
504. This address can be calculated from the rotation direction and (Xs, Ys), (Xe, Ye). The rotated and read data is converted into area data by the same method as in the first and second inventions. By such a procedure, rotation of a part of the region becomes possible.

In each of the above-described embodiments, when data for which an area is specified is stored and held for image data before rotation, the area data is also made rotatable. When the areas overlap, there are cases where the overlapped part is not an area and cases where the overlapped part is also an area. Even in the case where the overlapped portion is a region, a rotated region signal can be generated from the region data designated before the rotation. Further, it is possible to generate an area signal obtained by rotating a part of the area data with respect to the area data designated before the rotation.

[0062]

As is clear from the above description, claim 1
The image processing apparatus of the invention reads a predetermined document, displays data of the read document, specifies an area for the read document, and retains the area data specifying the area.
An area signal is generated from the specified area data, and image processing is performed on the area signal. A line buffer having a number of bits equal to the number of types of area processing, generated by rotating the area signal, is provided, and the area signal is generated by rotation. Therefore, since the area signal is generated in consideration of the rotation, the area signal rotated in accordance with the rotation of the image data can be generated even when the area data specified before the rotation is stored and held. . Further, it can be generated by arbitrarily rotating only the area data.

In the second or third aspect of the present invention, the area generating means includes a plurality of areas to be subjected to the same image processing. A line buffer having a length of one line in the main scanning direction × the number of types of areas × the number of overlapping correspondences (bits) is provided. An area signal is generated by providing a line buffer of two lines, deleting unnecessary data of area data, deleting unnecessary data, and rotating the area data. Therefore, since the area signal is rotated in consideration of the area where the area overlaps also as the area, the area data specified before rotation is stored and held, and when the rotated area signal is generated, the overlap area is also reduced. The region data can be rotated in consideration of the region.

In the rotating means according to the fourth aspect of the present invention, a part of the area designated before rotation is designated by a square, and a rotated area signal is performed on the area data of only the designated part. Therefore, partial rotation is enabled.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration example of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a more detailed configuration example of an image processing unit.

3A is a conceptual diagram for explaining an example of an area designation procedure, and FIG. 3B is a conceptual diagram for explaining area data.

4A is a diagram illustrating a state of region data written in a bit map, and FIG. 4B is a diagram illustrating generation of a region signal.

FIG. 5 is an explanatory diagram in the case where areas of the same number overlap.

6A is a diagram illustrating a state of region data written in a bit map, and FIG. 6B is a diagram illustrating generation of a region signal.

FIG. 7 is an explanatory diagram in the case where areas of different numbers overlap.

8A is a diagram illustrating a state of area data written in a bit map, and FIG. 8B is an explanatory view of generating a region signal.

FIG. 9 is a diagram illustrating a configuration of an area generating unit and a memory.

FIG. 10 is a diagram illustrating an access relationship between a bitmap and a memory bank.

FIG. 11 is a diagram illustrating address calculation of a memory.

12A is a diagram illustrating a normal memory access sequence, FIG. 12B is a diagram illustrating a memory access sequence at 90 ° rotation, and FIG. 12C is a diagram illustrating a memory access sequence at 180 ° rotation. d) A diagram for explaining a memory access order at the time of 270 ° rotation.

FIG. 13 is an explanatory diagram of a region in a main scanning direction.

FIG. 14 is an explanatory diagram when the area data held in the memory is rotated as it is.

FIG. 15 is an explanatory diagram of a line memory.

FIG. 16 is an explanatory diagram when rotating area data.

FIG. 17 is a diagram illustrating an area for overlapping correspondence.

FIG. 18 is a diagram illustrating generation of an area signal of area data when overlapping is performed.

FIG. 19 is a diagram illustrating a method of describing area data for overlapping correspondence.

FIG. 20 is a diagram illustrating area data when overlapping is performed.

FIG. 21 is a diagram illustrating a method of rotating area data when overlapping is performed.

FIG. 22 is a diagram illustrating a processing process of a method of rotating area data when overlapping is performed.

FIG. 23 is a diagram illustrating a memory access procedure when unnecessary data is deleted.

FIG. 24 is a diagram illustrating a processing procedure of performing rotation after deleting unnecessary data.

FIG. 25A is an explanatory diagram of generation of an area signal, and FIG. 25B is an explanatory diagram of an edge portion of the area signal.

FIG. 26 is an explanatory diagram of a circuit that deletes positions that become unnecessary data.

FIG. 27 (a) is a diagram illustrating region data before rotation,
(B) It is explanatory drawing at the time of rotating partially.

FIG. 28 is a diagram illustrating a method of specifying a part.

FIG. 29 is an explanatory diagram of gate signal generation in a partial area.

FIG. 30 is a diagram illustrating an access order of a memory including a partial rotation.

FIG. 31 is a diagram illustrating a signal of a timing of rotating and reading in memory reading.

FIG. 32 is a diagram illustrating an address generation circuit at the time of memory access including partial rotation.

[Explanation of symbols]

101 scanner 102 image processing unit 103 operation unit 104 display / coordinate instruction unit 105 storage unit 106 CPU 107 ROM 108 printer 201 scaling 202 RGBγ correction 203 RGB filter 204 create 205 color correction 206 CMYK filter 207 CMYKγ correction 208 gradation processing 209 Area signal generation 210 memory 211 CPU 301 outside area 302 inside area 303 area data 503, 504 area signal 601 overlapping area 602, 603 area signal 604 area signal data 701 memory bank 0 702 memory bank 1 703 memory bank 2 704 memory bank 3 705, 706 Data bus 707, 708, 709, 710 Control signal bus 711 Address bus 901 Main scanning direction counter 902 Sub scanning method Directional adder 903 Adder 904 4-line counter 1001, 1002, 1003 Direction of memory access order 1201 Bit width of line memory 1202 Each bit 1203 Corresponding to dot 1301 Read data 1302 Area number 1303 Bit value 1307 Generated signal 1401 Area data 1402 flag data 2101 start / end code signal 2102 area data signal 2103 area data signal decoder 2106 UP / DOWN counter 2401 main scanning direction gate signal 2402 sub scanning direction gate signal 2602 address generation for normal access 2603 address generation during rotation 2605 address setting Signal 2606 Rotation direction setting signal 2701 Rotation read timing signal

Claims (4)

[Claims] A reading unit that reads data of the read original; a display unit that displays data of the read original; a specifying unit that specifies an area for the read original; and an area data that specifies the area. A memory for holding, an area signal generating means for generating an area signal from the specified area data, and an area processing means for rotating and generating the area signal in an image processing apparatus for performing image processing on the area signal. An image processing apparatus comprising: a line buffer having a number of bits corresponding to the number of types, wherein the line signal is generated by rotating the area signal. 2. The area generating means according to claim 1, wherein when there are a plurality of areas on which the same image processing is to be performed and a part where the areas overlap is also an area, the area generating means is used as a rotation means when the overlap is also an area. An image processing apparatus, comprising: a line buffer having a length of one line in the main scanning direction after rotation × the number of area types × the number of overlapping correspondences (bits), and generating the area signal by rotating the area signal. 3. The area generating means according to claim 1, wherein when there are a plurality of areas on which the same image processing is to be performed and the overlapping area is also an area, the area generating means is used as a rotating means when the overlapping is also an area. Image processing comprising a line buffer having a length of two lines in the main scanning direction before rotation, means for deleting unnecessary data of area data, and generating the area signal by rotating after deleting unnecessary data. apparatus. 4. The rotating means according to claim 2, wherein
An image processing apparatus comprising: means for designating a part of an area designated before rotation by a square; and means for applying the rotated area signal to area data of only the designated part.