JP3004995B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing apparatus that performs predetermined thinning processing and thickening processing on an input image.

[Conventional technology]

Conventionally, for example, in a digital color copying machine, an original is irradiated with a halogen lamp or the like, and the reflected light is decomposed into, for example, R (red), G (green), and B (blue) by optical means such as an optical filter or a prism. And CCD it
After photoelectric conversion using a charge-coupled device such as the above, it is converted into a digital signal, and after performing predetermined processing, an image is formed using a recording device such as a laser beam printer, a liquid crystal printer, a thermal printer, an ink jet printer, and the like. I have.

In such digital color copying machines, there has been an extremely high demand for smooth images and sharp characters, lines, and the like, and various companies have studied variously.

[Problems to be solved by the invention]

However, in the area gradation method in which the gradation of the image is secured by the dot area, the gradation of the output image and the height of the resolution are contradictory, and different processing is performed in the image part and the character part. Is required. Many methods have been announced so far, but only those that perform complicated processing in software, and methods that perform processing in real time are very expensive due to the circuit scale, and products It was impossible to use it.

In order to perform different processing on the image part and the character part, a high-precision image area separation technique is required. However, high-precision separation cannot always be performed on a noisy image.

Therefore, when there is an isolated point such as noise in the processing target data corresponding to the image, a method for effectively removing the isolated point has been desired.

Therefore, the present invention has been made in view of such a drawback, and an object of the present invention is to provide an image processing apparatus that effectively removes isolated points included in data to be processed and realizes accurate image tone determination. I do.

[Means for solving the problem]

In order to solve the above problems, the present invention provides an input unit for inputting image data, a first processing unit for performing a thinning process for thinning an image represented by the image data on the image data, A second processing unit for performing a fattening process for thickening an image represented by the image data on the image data output by the first processing unit, and using an output of the second processing unit. Identification means for identifying the image tone of the image represented by the image data input by the input means.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. This system is equipped with a digital color image reader (hereinafter, referred to as
A color reader 1 is provided, and a digital color image printing apparatus (hereinafter, referred to as a color printer) 2 is provided below. This color reader 1 is provided with a color separation unit described later.
The color image information of the original is read for each color by a photoelectric conversion element such as a CCD, and is converted into an electric digital image signal. The color printer 2 is an electrophotographic laser beam color printer that reproduces a color image for each color in accordance with the digital image signal, and transfers the color image onto a recording sheet a plurality of times in a digital dot form and records the image.

 First, an outline of the color reader 1 will be described.

Reference numeral 3 denotes a document, 4 denotes a platen glass on which the document is placed, and 5 denotes a rod door for condensing a reflected light image from the document scanned and exposed by a halogen exposure lamp 10 and inputting the image to a 1: 1 full-color sensor 6. Ray lenses, 5, 6, 7, and 10 are integrally scanned as an original scanning unit 11 to perform exposure scanning in the direction of arrow A1. The color-separated image signal read line by line during exposure scanning is output to a sensor output signal amplifying circuit 7.
After that, the signal is amplified to a predetermined voltage by a signal line 501 and input to a later-described video processing unit for signal processing. Details will be described later. 501 is a coaxial cable for ensuring a faithful transmission of a signal. A signal 502 is a signal line for supplying a drive pulse for the 1: 1 full-color sensor 6, and all necessary drive pulses are generated in the video processing unit 12.
Reference numerals 8 and 9 denote a white plate and a black plate for white level correction and black level correction of an image signal described later, respectively.
By irradiating at 10, a signal level of a predetermined density can be obtained, and is used for white level correction and black level correction of a video signal. Reference numeral 13 denotes a control unit having a microcomputer, which controls the display, key input control and video processing unit 12 on the operation panel 20 by the bus 508, and the position of the original scanning unit 11 by the position sensors S1 and S2 to signal lines 509 and 510. Control via a signal line 503 to control the stepping motor drive circuit for pulse driving the stepping motor 14 for moving the scanning body 11, and turning on / off the halogen exposure lamp 10 by the exposure lamp driver via the signal line 504. OFF control,
All controls of the color reader unit 1 such as light amount control, the digitizer 16 via the signal line 505, internal keys, and control of the display unit are performed. A color image signal read by the above-described exposure scanning unit 11 at the time of document exposure scanning is input to the video processing unit 12 via the amplifier circuit 7 and the signal line 501, and subjected to various processes described later in the main unit 12. Is transmitted to the printer unit 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be described. Reference numeral 711 denotes a scanner, which is a laser output unit that converts an image signal from the color reader 1 into an optical signal, a polyhedron (for example, an octahedron)
, A motor (not shown) for rotating the mirror 712, an f / θ lens (imaging lens) 713, and the like. 714 is a reflection mirror that changes the optical path of laser light, 7
Reference numeral 15 denotes a photosensitive drum. The laser beam emitted from the laser output unit is reflected by the polygon mirror 712, passes through the lens 713 and the mirror 714, scans the surface of the photosensitive drum 715 linearly (raster scan), and forms a latent image corresponding to the original image. .

Also, 711 is a primary charger, 718 is an overall exposure lamp, 723
Is a cleaner section for collecting the residual toner not transferred,
724 is a pre-transfer charger, and these members are the photosensitive drum 7
It is located around 15.

A developing unit 726 develops an electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure.
1Y, 731M, 731C, and 731Bk are development sleeves that perform direct development in contact with the photosensitive drum 715, 730Y, 730M, 730C, and 730Bk are toner hoppers that hold spare toner, and 732 is a screw that transfers developer. , These sleeves 731Y-73
1Bk, toner hopper 730Y ~ 730Bk and screw 732
Constitutes a developing unit 726, and these members are disposed around the rotation axis P of the developing unit. For example, when a yellow toner image is formed, yellow toner development is performed at the position shown in the figure, and when a magenta toner image is formed, the developing unit 726 is rotated about the axis P in the figure to expose the photosensitive element. The developing sleeve 731M in the magenta developing device is disposed at a position in contact with the body 715. The development of cyan and black operates in the same manner.

Reference numeral 716 denotes a transfer drum that transfers the toner image formed on the photosensitive drum 715 to paper, and 719 denotes a transfer drum 716.
An actuator plate 720 for detecting the movement position of the actuator, a position sensor 720 for detecting that the transfer drum 716 has moved to the home position by approaching the actuator plate 719, a transfer drum cleaner 725, a transfer drum cleaner 727
Is a paper pressing roller, 728 is a static eliminator, and 729 is a transfer charger. These members 719, 720, 725, 727, 729 are transfer rollers 7
It is located around 16.

On the other hand, 735,736 is a paper feed cassette for storing paper (sheets), 737,738 is a paper feed roller for feeding paper from the cassette 735,736, and 739,740,741 are timing rollers for timing of paper feed and conveyance, and via these. The paper fed and conveyed is guided by a paper guide 749 and wrapped around the transfer drum 716 while the leading end is held by a gripper described later,
The process proceeds to the image forming process.

Reference numeral 550 denotes a drum rotation motor, and the photosensitive drum 715
750 rotates the transfer drum 716 synchronously. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed.
Is a transport belt that transports the removed paper, 743 is an image fixing unit that fixes the paper that has been transported by the transport belt 742, and the image fixing unit 743 has a pair of thermal pressure rollers 744 and
745.

The image processing circuit according to the present invention will be described in detail with reference to FIG. This circuit exposes a full-color original with an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and converts the obtained analog image signal into an A / D converter. A color image copying apparatus that processes and processes the digitized full-color image signal, outputs it to a thermal transfer type color printer, an ink jet color printer, a laser beam color printer, etc. (not shown) to obtain a color image, or A color image signal is input from a computer, another color image reading device, or a color image transmitting device, and is subjected to processing such as synthesis, and is applied to a color image output device for outputting to the aforementioned color printer. Things.

The original is first irradiated by an exposure lamp (not shown),
The reflected light is color-separated for each image by the color reading sensor 500a and read, and is amplified to a predetermined level by the amplifier circuit 501a. 533a is a CCD driver that supplies a pulse signal for driving a color reading sensor, and the necessary pulse source is a system control pulse generator 53.
Generated in 4a.

FIG. 3 shows a color reading sensor and a driving pulse. FIG. 3A shows a color reading sensor used in the present example.
μm as one pixel (4dot / inch (hereinafter referred to as dpi))
1024 pixels, that is, one pixel in the main scanning direction as shown in FIG.
Since the image is divided into three by R, the total number of effective pixels is 1024 × 3 = 3072. On the other hand, the chips 58 to 62 are formed on the same ceramic substrate, and the first, third and fifth sensors (58a, 60a,
2a) is arranged on the same line LA, and the second and fourth are arranged on a line LB which is four lines away from LA (63.5 μm × 4 = 254 μm), and scans in the direction of arrow AL when reading a document.

The driving pulse group ODRV118a is the first, third, and fifth of each of the five CCDs.
The second and fourth are driven independently and synchronously by the EDRV 119a. O01A, O02A, ORS included in ODRV118a
And E01A, E02A, and ERS included in EDRV119a are the charge transfer clock and charge reset pulse in each sensor, respectively. It is generated completely synchronously so as not to be in the jitter. For this reason, these pulses are generated by one reference oscillation source OSC558.
a (FIG. 2).

FIG. 4 (a) is a circuit block for generating ODRV 118a and EDRV 119a, and FIG. 4 (b) is a timing chart, which is included in the system control pulse generator 534a in FIG. Original clock CLK0 generated from a single OSC558a
Clock K0135a is a clock for generating reference signals SYNC2, SYNC3 for determining the timing of ODRV and EDRV generation, and SYNC2, SYNC3 are presettable counters 64a, set by the signal line 22 connected to the CPU bus. The output timing is determined according to the set value of 65a, and SYNC2 and SYNC3 initialize frequency dividers 66a and 67a and drive pulse generators 68a and 69a. That is, based on the HSYNC 118 input to this block as a reference, all the pulses are generated by the CLK0 output from one oscillation source OSC558a and the frequency-divided clocks generated in synchronization with each other, so that the respective pulses of the ODRV118a and the EDRV119a The groups are obtained as synchronized signals without any jitter, and signal disturbance due to interference between sensors can be prevented.

Here, the sensor drive pulses obtained in synchronization with each other
ODRV118a is connected to the first, third and fifth sensors 58a, 60a and 62a, and the EDRV119a
Is supplied to the second and fourth sensors 59a and 61a, and the respective sensors 58a and 59a
a, 60a, 61a, 62a
1 to V5 are output independently, amplified to a predetermined voltage value by independent amplifier circuits 501-1 to 501-5 for each channel shown in FIG. 2, and passed through a coaxial cable 101a as shown in FIG.
The signals V1, V3, and V5 are transmitted at the timing of OOS 129a, and the signals of V2 and V4 are transmitted at the timing of EOS 134a, and input to the video image processing circuit.

A color image signal obtained by reading the original input to the video image processing circuit by dividing it into five divisions is G (green), B (blue), and R by the sample / hold circuit S / H502a.
(Red) are separated into three colors. Therefore, after S / H, signal processing of 3 × 5 = 15 systems is performed.

The analog color image signal sampled and held for each color R, G, B by the S / H circuit 502a is converted to a next-stage A / D conversion circuit 503.
In a, each 1-5 channel is digitized, and each 1-channel
The data is output to the next stage in parallel for 5 channels independently.

In this embodiment, as described above, four lines (63.5
(μm × 4 = 254 μm) in the sub-scanning direction, and the original is read by five staggered sensors divided into five regions in the main scanning direction. At 1, 3, and 5, the reading position is shifted. Therefore, in order to connect these correctly, the misalignment is corrected by a misalignment correction circuit 504a having memories for a plurality of lines.

Next, a black correction / white correction circuit 506a will be described with reference to FIG.
Will be described. As shown in FIG. 5B, the black level outputs of the channels 1 to 5 have large variations between chips and between pixels when the amount of light input to the sensor is small.
If this is output as it is to output an image, streaks and unevenness occur in the data portion of the image. Therefore, it is necessary to correct the output variation of the black portion, and the correction is performed by a circuit as shown in FIG. Prior to the original reading operation, the original scanning unit is moved to a position of a black plate having a uniform density arranged in the non-image area at the leading end of the original platen to turn on the halogen and to input a black level image signal to this circuit. As for the blue signal B _IN , one line of this image data is stored in the black level RAM 78a.
A is selected by the selector 82a to store it in the
Close 0a () and open 81a. That is, the data line is 151
a → 152a → 153a, while RAM78a address input 1
55a is initialized by ▲ ▼, and the output to the selector 83a is output so that the output 154a of the address counter 84a that counts VCLK is input, and a black level signal for one line is stored in the RAM 78a (the above is referred to as black). This is called a reference value acquisition mode).

At the time of image reading, the RAM 78a is in the data reading mode, and is read and input for each line and one pixel to the B input of the subtractor 79a via the data line 153a → 157a. That is, at this time, the gate 81a closes () and the gate 80a opens (). The selector 86a has an A output. Therefore,
The black correction circuit output 156a is, for example, B _IN (i) −DK (i) = B in the case of a blue signal with respect to the black level data DK (i).
_OUT (i) (referred to as black correction mode). Similarly, the green G _IN and the red R _IN are similarly controlled by 77aG and 77aR. The control lines of each selector gate for this control are connected to the I / O of the CPU 22 (FIG. 2).
This is performed under CPU control by the latch 85a assigned as / O. The RAM 78a can be accessed by the CPU 22 by selecting the selectors 82a, 83a, 86a by B.

Next, white level correction (shading correction) in the black correction / white correction circuit 506a will be described with reference to FIG. In the white level correction, the sensitivity variation of the illumination system, the optical system, and the sensor is corrected based on the white data when the original scanning unit is moved to the position of the uniform white plate and irradiated. FIG. 6 (a) shows a basic circuit configuration. The basic circuit configuration is the same as that shown in FIG. 5 (a), except that the black correction is performed by the subtractor 79a, whereas the white correction uses a multiplier 79'a. Therefore, the description of the same part is omitted.

At the time of color correction, when the CCD (500a) for reading the original is at the reading position (home position) of the uniform white plate, that is, before the copying operation or the reading operation,
An unillustrated exposure lamp is turned on, and image data of a uniform white level is stored in the correction RAM 78'a for one line. For example, if it has a width in the main scanning direction A4 longitudinal direction, 16pe
16/297 mm = 4752 pixels at l / mm, that is, at least the capacity of the RAM is 4752 bytes. As shown in FIG. 6 (b), if the white plate data Wi (i = 1 to 4752) of the i-th pixel is RAM7
As shown in FIG. 6 (c), 8'a stores data on the white plate for each pixel.

On the other hand, for Wi, the data Do corrected to the read value Di of the normal image of the i-th pixel should be Do = Di × FF _H / Wi. Then, the CPU 85 sends the latches 85'a ',',
Gates 80'a and 81'a are opened for 'and', and selectors 82'a, 83'a and 86'a output so that B is selected, and the RAM 78'a can be accessed by the CPU. Next, according to the procedure shown in FIG. 6 (d), the CPU 22 applies FF _H / Wo, W _{1 to the first} pixel Wo.
FF / W ₁ ... Are sequentially operated to replace data. When the process is completed for the blue component of the color component image (FIG. 6D)
Step B) Similarly, the green component (Step G) and the red component (St
epR), and thereafter, the gate 80'a so that Do = Di × FF _H / Wi is output for the input original image data Di.
Is open ('), 81'a is closed ('), and selectors 83'a, 8
A is selected for 6'a, and the coefficient data FF _H / Wi read from the RAM 78'a passes through the signal line 153a → 157a, is multiplied by the original image data 151a input from one, and is output. .

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the variation of the sensitivity between each sensor, the variation of the light intensity of the optical system, and the sensitivity of the white level. Over the scanning direction,
Image data B _OUT uniformly corrected for each color for both white and black
101, G _OUT 102 and R _OUT 103 are obtained. The obtained color-separated image data of which the white and black levels have been corrected are obtained by detecting pixels on an image having a specific color density or a specific color ratio according to an instruction from an operation unit (not shown), and performing the same operation. The data is sent to a color conversion circuit B for performing data conversion to another color density or a color ratio specified by the unit.

<Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit of FIG. 7 is an 8-bit color separation signal R _IN , G
_IN , B _IN (1b to 3b), a color detection unit 5b for determining an arbitrary color set in the register 6b by the CPU 20, an area signal Ar4b for performing color detection and color conversion for a plurality of locations, A signal (hereinafter referred to as a hit signal) output from the color detection unit and indicating that the color is a specific color is referred to as a “hit signal” in the main scanning direction and the sub scanning direction (the
In the example of the figure, only the line memories 10b to 11b for performing the process of expanding in the sub-scanning direction, the OR gate 12b, and the expanded hit signal 3
4b and non-rectangular signal (including square) color is generated from BHi27b conversion enable signal 33b, the input color separation data enable signal _{33b (R IN, G IN,} B IN 1b~3b), the synchronization of the area signal Ar4 Line memories 13b to 16b for the delay circuit 17
b to 20b, enable signal 33b, synchronized color separation data (R _IN ', G _IN ', B _IN '21b to 23b), area signal A
The color conversion unit 25 that performs color conversion based on the color data after the color conversion set in the register 26b by the r ′ 24b and the CPU 20.
b, Color conversion processed color separation data (R _OUT , G _OUT , B _OUT 28b
-30b), and a hit signal H _OUT 31b output in synchronization with R _OUT , G _OUT , and B _OUT .

Next, an outline of an algorithm for gradation color determination and gradation color conversion will be described. Here, the gradation color determination and the gradation color conversion are the same hue color determination and the same hue color for performing the color conversion while preserving the density value for the color having the same hue in performing the color determination and the color conversion. To do the conversion.

Same color (there hue), for example the ratio between-intensity signal R ₁ and the green signal G ₁ and Blue signal B ₁ is possible is known equal.

Therefore, one of the colors to be converted (here, the maximum value color,
Select data M ₁ below referred to as primary colors), therewith obtaining the ratio of the other two colors data. For example, when the main color is R, M ₁ = R ₁
And G ₁ / M ₁ and B ₁ / M ₁ are obtained.

Then, for the input data R _i , G _i , B _i , However, a pixel that satisfies α ₁ , β ₁ , γ ₁ ≦ 1 α ₂ , β ₂ , γ ₂ ≧ 1 is determined as a pixel to be color-converted.

Further, also for the data (R ₂ , G ₂ , B ₂ ) after the color conversion, the ratio between the data M ₂ of the primary color (here, the maximum value color) and the data of the other two colors is obtained.

For example, when G ₂ is the main color, M ₂ = G _2, and R ₂ / M ₂ and B ₂ / M ₂ are obtained.

Then, the input data to the main color M _1, Ask for.

If the data is a color conversion pixel, If the pixel is not a color conversion pixel, (R _i , G _i , B _i ) is output.

As a result, it is possible to detect all portions of the same hue having a gradation and output color conversion data corresponding to the gradation.

FIG. 8 is a block diagram showing an example of the color judgment circuit.
This part is a part for detecting a pixel to be color-converted.

In this figure, 50b is a smoothing unit for smoothing the input data of R _IN b1, G _IN b2, and B _IN b3, and 51b is a selector 52b _R , 5 for selecting one of the outputs (primary colors) of the smoothing unit.
2b _G and 52b _B are selectors for selecting the output of the selector 51b and one of the fixed values R ₀ , G ₀ and B ₀ , 54b _R , 54b _G and 54b _B are OR gates, 63b and
64b _R , 64b _G , 64b _B are selectors for setting select signals to selectors 51b, 52b _R , 52b _G , 52b _B based on the area signals Ar10, Ar20, respectively, 56b _R , 56b _G , 56b _B and 57b _R , 57b _G ,
57b _B is a multiplier for calculating the upper and lower limits of each.

Also, each upper limit ratio register 5 set by CPU 20
8b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B can set data for color detection for a plurality of areas based on the area signal Ar30.

Here, Ar10, Ar20, and Ar30 are signals generated based on Ar4b in FIG. 7, and each has a required number of DF / Fs. Also
61b is an AND gate, 62b is an OR gate, and 67b is a register.

Next, the actual movement will be described. R _IN b1, G _IN b2, B _IN b3
The data R obtained by smoothing each ', G', one of the B ', CPU 20 is to select the selector 51b by the select signals S ₁ to excisional primary color data is selected. Here, the CPU 20 stores different data A, respectively in the registers 65b, 66b.
And excisional a B, the selector 63b is input A, the selector 51b either a B as the select and S ₁ signal in response to Ar10 signal.

In this way, two registers 65b and 66b are prepared, and different data are input to A and B of the selector 63b, and the area signal Ar10
By selecting one of them, separate color detection can be performed for a plurality of areas. This area signal Ar10 may be a signal for a non-rectangular area as well as a rectangular area.

In the next selectors 52b _R , 52b _G , 52b _B , either the R ₀ , G ₀ , B _{0 set} by the CPU 20 or the main color data selected by the selector 51b is output to the outputs 53ba to 53bc of the decoder 53b and fixed colors. is select by a select signal generated by the mode signal S _2. The selectors 64b _R , 64b _G , and 64b _B output the area signal
By selecting either A or B according to Ar20, it is possible to detect different colors for a plurality of areas as in the case of the selector 63b. here,
R ₀ , G ₀ , and B ₀ are selected for the main color in the conventional color conversion (identified color mode) and gradation color determination, and the main color data is selected for a color other than the main color in the gradation color conversion. .

The operator can freely select the fixed color determination and the gradation color determination from the operation unit. Alternatively, for example, it is also possible to change by software according to color data (color data before color conversion) input from an input device such as a digitizer.

From the outputs of these selectors 52b _R , 52b _G , 52b _B and the upper limit ratio registers 58b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B set by the CPU 20, R ′,
The upper and lower limit values of G ′ and B ′ are multipliers 56b _R , 56b _G and 56b _B
And 57b _R, 57b _G, is calculated by 57 b _B, the window comparator 60b _R, 60b _G, is set as the upper and lower limit values in 60b _B.

In the window comparators 60b _R , 60b _G , and 60b _B , it is determined by the AND gate 61b whether or not the main color data falls within a certain range and two colors other than the main color fall within a certain range. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination unit. In that case, the part to which "1" is set has a color to be converted.

With the above configuration, the fixed color determination or the gradation color determination can be performed for a plurality of areas.

FIG. 9 is a block diagram of an example of the color conversion circuit. This circuit selects a signal that has undergone color conversion or an original signal based on the output 7b of the color determination unit 5b.

In FIG. 9, the color conversion unit 25b includes a selector 111b and registers 112b _R1 , 112b _R2 , 112b _G1 , 112b _G2 , 112b for setting respective ratios of the converted color to the main color data (here, the maximum value).
_B1 , 112b _B2 , multipliers 113b _R , 113b _G , 113b _B , selector 114b _R ,
114b _G , 114b _B , selector 115b _R , 115b _G , 115b _B , AND gate 3
2b, Ar5 generated based on area signal Ar'24 in FIG. 7
0, Ar60, Ar70 the data selector 111b to be excisional by CPU 20, the multiplier _{113b R, 113b G, 113b B} , the selector 114
b _R , 114b _G , 114b Selectors 117b, 112b _R , 112 set to _B
b _G , 112b _B , 116b _R , 116b _G , 116b _B and a delay circuit 118b.

 Next, the actual movement will be described.

The selector 111b receives the input signals R _IN '21b, G _IN ' 22b, B _IN '2
One of 3b (primary colors) is selected according to the select signal S5. Here, the signal S5 is generated when the area signal Ar40 selects the selector 117b to either A or B for the two data set by the CPU 20. In this way,
Color conversion processing can be performed on a plurality of areas.

The signal selected by the selector 111b is applied to multipliers 113b _R , 11
In 3b _G and 113b _B , multiplication with the register value set by the CPU 20 is performed. Again, the area signal Ar50 has two register values 112b _R1 , 112b _R2 , 112b _G1 , 112b _G2 , 112b _B1 , 112b
By selecting _B2 by the selectors 112b _R , 112b _G , and 112b _B , different color conversion processes can be performed on a plurality of areas.

Next, the results of the multiplication by the selectors 114b _R , 114b _G and 114b _B and the CPU
Two fixed values Ro '/ Ro ", Go'-Go", Bo' set by 20
Selectors 116b _R , 116b _G ,
One of the fixed values selected in 116b _B is selected by the mode signal S6. Here, as the mode signal S6, a signal selected by the area signal Ar60 in the same manner as in S5 is used.

Finally selector 115b _R, 115b _G, 'with _{R IN ", G IN",} B IN "(R IN' select signal S _B in 115b _B, G _IN ',
_BIN 'delayed and timing adjusted) and selector 1
Either 14b _R , 114b _G or 114b _B output is selected,
Output as R _OUT , G _OUT , B _OUT . Hit signal H _OUT
Are also output in synchronization with R _OUT , G _OUT , and B _OUT .

Here, the selector signal S _B ′ is obtained by delaying the AND of the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on the non-rectangular area. In this case, the area signal is a region such as a one-dot chain line, that is, the uppermost left position (FIG. 10a), the uppermost right position (FIG. 10b), the lowermost left position (FIG. 10c), and the lower left position obtained from the dotted line. It is generated by the coordinates (Fig. 10d). The non-rectangular area signal BHi is input from an input device such as a digitizer. When color conversion is performed using this non-rectangular enable signal, the enable area can be specified along the boundary of the area to be converted.
Compared with the conventional color conversion using a rectangle, the threshold for color detection can be expanded. Therefore, it is possible to obtain an output image in which the detection capability is improved and the gradation color conversion is performed with high accuracy.

From the above, color conversion having lightness according to the main color of the color determination unit 5b (for example, when converting red to blue gradation color, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion Can be freely performed on a plurality of regions.

Further mosaic only specific color area (non-rectangular or square) based on Hitsuto signal H _OUT as described later, Tekusuchiya process, trimming process may be subjected to a masking process or the like.

Then, as shown in FIG.
Reference numeral 4,105 denotes a logarithmic conversion circuit C for converting image data proportional to the reflectance into density data, a character image area separation circuit I for determining a character area and a halftone area, a halftone area on a document, and the present system. The data is transmitted to the external device interface M for exchanging data with the external device via the cables 135, 136, and 137.

Next, the color image data proportional to the input light quantity is input to a logarithmic conversion circuit C (FIG. 2) which performs processing for matching the human eyes with the relative luminous efficiency characteristics.

Here, white = 00 _H, is as much as possible converted black = FF _H, further image source input to the image reading sensor, such as a conventional reflective originals, transmission original such as a film Puroji EKTAR and negative film in the same transparent original Since the sensitivity of the positive film or the film and the gamma characteristics input in the exposure state are different, as shown in FIGS. 11 (a) and 11 (b), there are a plurality of LUTs (lookup tables) for logarithmic conversion. And use them according to the purpose. The switching is performed by the signal lines lg0, lg1, lg2, and is performed by inputting an instruction from an operation unit or the like as an I / O port of the CPU 22 (FIG. 2). Here, the data output for each B, G, R is
It corresponds to the density value of the output image. For each signal of B (blue), G (green) and R (red), Y
(Yellow), M (magenta), and C (cyan) correspond to the toner amounts, so that the subsequent image data is associated with yellow, magenta, and cyan.

Next, each color component image data from the original image obtained by the logarithmic conversion, that is, a yellow component, a magenta component,
The color correction circuit D performs color correction on the cyan component as described below. As shown in FIG. 13, the spectral characteristics of the color separation filter arranged for each pixel in the color reading sensor have an unnecessary transmission region such as a hatched portion, while, for example, a color transferred to a transfer paper. Toner (Y, M, C) is also first
It is well known that it has an unnecessary absorption component as shown in FIG. Therefore, for each color component image data Yi, Mi, Ci, Masking correction for calculating a linear expression of each color and performing color correction is well known. Furthermore, by Yi, Mi, Ci, Min (Yi, M
i, Ci) (the minimum value of Yi, Mi, Ci) is calculated as a mistake (black), and the operation of adding black toner (smearing) later and the operation of each color material according to the added black component are performed. Undercolor removal (UCR) operations, which reduce the amount added, are also common. Fig. 12 (a)
2 shows a circuit configuration of a color correction circuit D that performs masking, darkening, and UCR. The feature of this configuration is that it has two masking matrices and can be switched at high speed with "1/0" of one signal line. "0" enables high-speed switching, and has two circuits for determining the amount of blemishes, and "1/0" enables high-speed switching.

First, prior to image reading, a desired first matrix coefficient Second matrix coefficient From the bus connected to the CPU 22. In this example And Are in registers 87d to 95d, Are set in registers 96d to 104d.

Reference numerals 111d to 122d, 135d, 131d, and 136d denote selectors, respectively, which select A when the S terminal is "1" and select B when the S terminal is "0". So the matrix The switching signal MAREA364 = "1" When selecting, and "0" for selecting the matrix M _2.

Also, 123d is a selector, and the selection signals C ₀ and C ₁ (366
Output based on the truth table of Fig. 12 (b) by d) and 367d)
a, b, c are obtained. The selection signals C ₀ , C ₁ and C ₂ correspond to the color signals to be output, for example, in the order of Y, M, C, Bk (C ₂ , C ₁ ,
C ₀ ) = (0,0,0), (0,0,1), (0,1,0), (1,0,0),
Further, by setting (0, 1, 1) as a monochrome signal, a desired color-corrected color signal is obtained. Now (C ₀ , C ₁ , C ₂ ) =
If (0,0,0) and MAREA = "1", the output (a, b, c) of the selector 123d will have the contents of the registers 87d, 88d, 89d and therefore (a _Y1 , −b _M1 , − C _C1 ) is output. On the other hand, the input signal Y
The black component signal 374d calculated as Min (Yi, Mi, Ci) = k from i, Mi, Ci undergoes a primary conversion at 137d such that Y = ax−b (a, b are constants), and a subtractor 124d, It is input to the B input of 125d and 126d. In each of the subtracters 124d to 126d, Y = Yi
− (Ak−b), M = Mi− (ak−b), and C = Ci− (ak−b) are calculated, and the multipliers 127d and 127d for the masking operation are provided via the signal lines 377d, 378d and 379d. Input to 128d and 129d.

The multipliers 127d, 128d, and 129d have (A)
_Y1 , −b _M1 , −C _C1 ) and B input as described above [Yi− (ak−
b), Mi− (ak−b), Ci− (ak−b)] = [Yi, Mi, Ci]
As shown in the figure, the output D
_{For OUT} , under the condition of C ₂ = 0 (YorMorC), Y _OUT = Yi × (a _Y1 )
+ Mi × (−b _M1 ) + Ci × (−C _C1 ) is obtained, and yellow image data subjected to masking color correction and undercolor removal processing is obtained. Similarly, M _OUT = Yi × (−a _Y2 ) + Mi × (−b _M2 ) + Ci × (−C _C2 ) C _OUT = Yi × (−a _Y3 ) + Mi × (−b _M3 ) + Ci × (−C _C3 ) is output to D _OUT . The color selection is controlled by the CPU 22 according to the order of output to the color printer to be output (C ₀ , C ₁ , C ₂ ) according to the table of FIG. 12 (b). Register 1
05d to 107d and 108d to 110d are registers for forming a monochrome image, based on the same principle as the masking color correction described above.
MONO = k ₁ Y _i + l ₁ Mi + m ₁ Ci is obtained by weighting and adding each color.

Also, at the time of Bk output, C ₂ = 1 due to C ₂ (368) inputted as a switching signal of the selector 131d. Therefore, the primary converter 133d receives a primary conversion of Y = cx−d and selects the selector.
Output from 131d. BkMJ110 is a black component signal to be output to the outline of a black character based on the output of a character image area separation circuit I described later. Color switching signals C ₀ ′, C ₁ ′, C ₂ ′
366 to 368 are set from the output port 501 connected to the CPU bus 22, and the MAREA 364 is output from the area signal generation circuit 364. The gate circuit 150d~153d, when the DHi = "1" by later-described binary memory circuit (bit Matsupu memory) L537 non-rectangular area signal DHi122 read from, the signal C ₀ ',
This is a circuit for controlling so that C ₁ ′, C ₂ ′ = “ ₁ , ₁ , 0”, and data for a mono image is automatically output.

<Character Image Area Separation Circuit> Next, the character image area separation circuit I uses the read image data and determines whether the image data is a character, an image, a chromatic color, or an achromatic color. Circuit. The flow of the processing will be described with reference to FIG.

Red (R) 103, green (G) 104, blue (B) 105 input to the character image area separating circuit I from the color conversion B
Is input to the minimum value detection circuit M _IN (R, G, B) 101I and the maximum value detection circuit Max (R, G, B) 102I. In each block, a maximum value and a minimum value are selected from three types of input luminance signals of R, G, and B. The subtraction circuit 104I calculates the difference between the selected signals. If the difference is not large, that is, if the input R, G, and B are not uniform, it indicates that the signal is not achromatic and indicates a black and white but is a chromatic color depending on some color. Of course, if this value is small,
R, G, B signals are about the same level,
It can be seen that the signal is an achromatic signal that is not a signal that has a certain color. This difference signal is output to the delay circuit Q as a gray signal GR124. The difference is compared with a threshold value arbitrarily set in the register 111I by the CPU by the comparator 112I, and the comparison result is output to the delay circuit Q as a gray determination signal GRBi126. These GR125, GRBi126
The signal of (1) is input to a character image correction circuit E, which will be described later, after being matched in phase with other signals by the delay circuit Q, and used as a processing determination signal.

The minimum value signal obtained by M _IN (R, G, B) 101I is further processed by the edge enhancement circuit input to the edge enhancement circuit 103I using the following pixel data in the main scanning direction. Edge highlighting has been done.

D _OUT : Image data after edge enhancement Di: i-th pixel data Edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal that has been edge-emphasized in the main scanning direction is then subjected to 5 × 5 and 3 × 3 window average value calculation to obtain a 5 × 5 average 109I and a 3 × 3 average 110I.
Done in The line memories 105I to 108I are delay memories in the sub-scanning direction for performing the averaging process. 5x5 average
The 5 × 5 average value calculated in 109I is then added to offset values independently set in an offset section also connected to a CPU BUS (not shown) by adders 115I, 119I, and 124I. The added 5 × 5 average value is input to a limiter 1 113I, a limiter 2 118I, and a limiter 3 123I. Each limiter is connected by a CPU BUS (not shown), and is configured so that limiter values can be set independently.
If the average value is greater than the set limiter value, the output is clipped at the limiter value. The output signal from each limiter is
These are input to the comparator 1116I, the comparator 2121I, and the comparator 3126I, respectively. First, comparator 1
In 116I, the output signal of limiter 1 113I and 3 × 3 average 110I
Is compared with the output from Comparator 1 compared
The output of 116I is input to a delay circuit 117I so as to match the phase of an output signal from a dot area determination circuit 122I described later. This binarized signal has an average value of 2 in order to prevent collapse and skip by MTF at an arbitrary density or higher.
In order to cut the high frequency components of the halftone dot image so that the halftone dots of the halftone dot image are not detected by binarization,
Through a 3 × 3 low-pass filter. Next, the output signal of the comparator 2 (121I) is binarized with through image data so as to detect a high-frequency component of the image so that the dot area determination circuit 122I at the subsequent stage can determine the output signal. Since the halftone dot image is composed of a group of dots, the halftone dot region discriminating circuit 122I confirms that the dot is a dot from the edge direction, and detects the dot by counting the number of dots around the dot. The detailed description of the halftone dot region discriminating circuit 122I is not included in the gist of the present patent, and thus is omitted.

An OR gate 129I is obtained from the result of the determination by the halftone dot region determination circuit and the signal from the delay circuit 117, and the erroneous determination is removed by the erroneous determination removal circuit 130I, which is then output to the AND gate 132I. In the erroneous determination elimination circuit 130I, an image area is narrowed first for a binarized signal by making use of the characteristic that a character or the like is thin and an image has a large area, and the image area is an isolated image area. Specifically, when at least one pixel other than the image exists in the peripheral 1 mm square area with respect to the center pixel xij, the center pixel is determined to be the outer area of the image. After removing the image area of the isolated point as described above, a fattening process is performed to restore the thin image area. Similarly, the dot discrimination circuit
The output of 122I is directly input to the erroneous determination and elimination circuit 131I, and the thinning processing and the fattening processing are performed. Here, the mask size of the thickening process is the same as the mask size of the thickening process, or the thickening process is made larger, so that the determination result at the time of thickening crosses. Specifically, both the erroneous determination removal circuits 130I and 131I are thinned by a mask of 17 × 17 pixels, further thinned by a mask of 5 × 5,
Thickening processing is performed with a mask of 34 × 34 pixels. The output signal SCRN signal 127 from the erroneous determination elimination circuit 131I is a determination signal for preventing a moiré of a read image by performing smooth zinc processing only on a halftone dot determination unit in a character image correction circuit E described later.

Next, the contour of the input image signal is extracted from the output signal from the comparator 3126I in order to process the character in a later stage. As an extraction method, a binarized comparator 3
The output of 126I is subjected to a thinning process and a thickening process using a 5 × 5 block, and a difference area between the thickened signal and the thinned signal is defined as an outline. The contour signal extracted by such a method is passed through the delay circuit 128I to match the phase with the mask signal output from the erroneous determination removal circuit 130I,
The outline signal is masked by the AND gate 132I at the portion determined to be an image by the mask signal, and only the outline signal in the original character portion is output. The output from the AND gate 132I is then output to the contour regeneration unit 133I.

<Contour Regenerating Unit> The contour regenerating unit 133I performs a process of setting a pixel not determined as a character contour to a character contour based on information on surrounding pixels. As a result, the MjAr124 is used as a character image correcting circuit E To perform the processing described below.

Specifically, as shown in FIG. 16, bold characters (FIG. 16A)
As for the character, the dotted line portion in FIG. 2B is determined as a character as a character determination unit, and the processing described later is performed. For the thin character (FIG. 3C), the character portion is indicated by the dotted line in FIG. If the processing described later is performed, it may be difficult to see due to an erroneous determination. In order to prevent this, processing is performed for a portion that is not determined to be a character based on surrounding information for a character portion. Specifically, by changing the hatched portion to a character portion, the character portion becomes as shown by a dotted line in FIG. 11E, and erroneous determination can be reduced even for a character that is too thin to be detected, which leads to an improvement in image quality. .

FIG. 17 is a diagram illustrating how surrounding information is used to regenerate a pixel of interest in a character portion. (A) to (d)
Intended to be the 3 × 3 both vertical and horizontal and diagonal around the pixel of interest in block letters section (S _1, S ₂ are "1") character unit pixel of interest regardless of the information of the pixel of interest when the is there. On the other hand, (e) to (h) are 5 × 5 blocks, and 1
Both vertical and horizontal and diagonal is one which a character portion of the pixel of interest regardless of the character portion (S _1, S ₂ both "1") information of the target pixel in the pixel. In this way, by having the two-stage (plural types of blocks) structure, it is possible to cope with a wide range of errors.

FIGS. 18 and 19 are circuit diagrams for realizing the processing of FIG. 18 and 19 are line memories 164i to
167i, DF / F104i to 12 for obtaining information around the target pixel
6i, AND gate 1 for realizing FIGS. 17 (a) to 17 (h)
46i to 153i and an OR gate 153i. From the four line memories and the 23 DF / Fs, FIGS.
The information of S ₁ and S ₂ is extracted. Furthermore, registers 146i to 153i can be independently enabled and controlled by registers 155i to 162i corresponding to the respective processes (a) to (h).

The opposing relationship between the AND circuits 146i to 153i and FIGS. 17 (a) to (h) is as follows.

FIG. 20 shows ▲ ▼ of the line memories 164i to 167i (EN
These are timing charts for 1) and ▲ ▼ (EN2). This is done so that EN1 and EN2 are at the same timing at the time of equal magnification, or at the time of enlargement (for example, 200% to 300%), ▲ is thinned once in two lines. As a result, FIG.
The size of (h) expands. This is because when the information is input at the time of enlargement, the information comes in an image enlarged only in the sub-scanning direction. Is going.

<Character image correction circuit> The character image correction circuit E is the character image area separation circuit I described above.
The following processing is performed on each of black characters, color characters, halftone images, and halftone images based on the determination signal generated in step (1).

[Processing 1] Processing related to black characters [1-1] Signal BkMj obtained as a video by Sumi extraction
[1-2] Y, M and C data are subtracted according to the multi-valued achromatic signal GR125 or the set value. On the other hand, the Bk data is added according to the multi-valued achromatic signal GR125 or the set value. [1-3] Edge enhancement is performed. [1-4] Black characters are printed out at 400 lines (400 dpi). 5) Perform residual color removal processing [Process 2] Process on color characters [2-1] Perform edge enhancement [2-2] Color characters are printed out at 400 lines (400 dpi) [Process 3] Halftone dots Processing related to image [3-1] Smoothing to prevent moire (2 in main scanning)
[Process 4] Process relating to halftone image [4-1] Smoothing (two pixels in the main scanning direction) or through can be selected.

 Next, a circuit for performing the above processing will be described.

 FIG. 21 is a block diagram of the character image correcting section E.

The circuit of FIG.
6e 'for generating a signal for controlling the selector, a block 16e for performing a color residual removal process described later, and an AND for generating an enable signal for the process.
The gate 16e ', the multiplier 9e' for multiplying the GR signal 125 by the set value 10e of the I / O port, the selector 11e for selecting the multiplication result 10e or the set value 7e of the I / O port, and the outputs 13e and 11e of the selector 6e
Multiplier 15e, XOR gate 20e, AND gate 22e, adder / subtractor 24e, line memories 26e and 28e for delaying one line data, edge emphasis block 30e, smoothing block 31e, through data or smoothing data. The selector 33e to be selected, the delay circuit 32e for synchronizing the control signals of the selector, the selector 42e for selecting the result of edge enhancement or the result of smoothing, the delay circuits 36e and O for synchronizing the control signals of the selector.
R gate 39e, AND gate 41e, 400 lines (d
pi) Inverter circuit for outputting a signal (“L” output)
44e, AND circuit 46e, OR circuit 48e, video output 113 and LCHG4
It is composed of a delay circuit 43e for synchronizing 9e. The character image correction unit E is connected to the CPU bus 22 via the I / O port 1e.

Hereinafter, [1] color residual removal processing for removing a color signal remaining around the edge of the black character portion and subtraction at a certain ratio from the Y, M, and C data of the black character portion determination portion, and a certain ratio from the Bk data , [2] Edge enhancement for character part, smoothing for halftone determination part, other gradation image to select through data, [3] LCHG for character part
The signal is set to "L" (printing at 400 dpi) and divided into three parts.

[1] Color Residual Removal Processing and Addition / Subtraction Processing Here, both the signal GRBi126 indicating an achromatic color and the signal MjAR124 indicating a character portion are active,
In other words, the processing is for the edge portion of the black character and its peripheral portion, in which the Y, M, and C components protruding from the edge portion of the black character are removed, and the edge portion is smeared.

 Next, a specific operation will be described.

This process is performed only when the character portion is determined (MjAR124 = "1"), the character is a black character (GRBi126 = "1"), and the color mode is set (DHi122 = "0"). Therefore, ND
(Black and white) mode (DHi = "1"), color characters (GRBi = "0")
It is not done at the time of.

When the original is scanned for any of the recording colors Y, M, and C, the video input 111 is selected by the selector 6e ("0" is set to I / O-6 (5e)). In 15e, 20e, 22e, and 17e, data to be subtracted from the video 8e is generated.

For example, if "0" is set in the I / O-3 12e, the multiplier 15e multiplies the selector output data 13e by the value set in the I / O-17e. Here, data 18e that is 0 to 1 times that of 13e is generated. By setting 1 to the registers 9e and 25e, the 2's complement data of 18e becomes 17e and 20e.
e, 22e. Finally, 8e and 23e by the adder / subtractor 24e
23e is a two's complement number, so 17e-8e is actually subtracted and output from 25e.

When "1" is set in I / O-3 12e, selector 11e
Selects B data.

At this time, the multi-valued achromatic signal GR125 (a signal having a large value if the color is close to achromatic) generated by the character image area separating circuit I is multiplied by 9e by the value set by I / O-210e. Is used as a multiplier of 13e. When using this mode
The coefficient can be changed independently for each of the colors Y, M, and C, and the subtraction amount can be changed according to the achromaticity.

During the recording color Bk scan, the selector 6e selects BkMj112 (set "1" in I / O-65e). 15e, 20e, 22e, 17e
Generates data to be added to the video 17e. Y above
The difference from M and C is that "0" is set in I / O-4,9e, whereby 23e = 8e, Ci = 0, and 17e + 8e is output from 25e. The way of generating the coefficient 14e is the same as in the case of Y, M, C. In the mode in which "1" is set in the I / O-3 12e, the coefficient changes according to the achromaticity. Specifically, when the achromaticity is large, the addition amount is large, and when the achromaticity is small, the addition amount is small.

FIG. 22 shows this processing in which the shaded portions of the black characters N shown in FIG. 22 are enlarged (a) and (c). Where the character signal portion is "1" for Y, M, and C data, the subtraction from the video is performed ((b) in the figure), and for the Bk data, the character signal portion is "1". Is added to the video ((d) in the figure). In this figure, 13e = 18e,
This is an example in which the Y, M, and C data are 0, and the Bk data is twice as large as the video.

By this processing, the outline portion of the black character is almost entirely black, but the * mark shown in FIG. 22 (b) outside the outline signal remains around the character as a color remaining. It is unsightly.

What removes the remaining color is a color removal removal process. This processing is performed when the video data 13e falls within the range where the character area is expanded and the video data 13e is smaller than the comparison value set by the CPU, that is, a pixel having a possibility of color remaining outside the character area. Is a process for taking the minimum value of 3 or 5 pixels before and after.

 Next, the explanation will be supplemented by using a circuit.

FIG. 23 shows a character area enlarging circuit which moves so as to expand the character area, and includes DF / Fs 65e to 68e and AND gates 69e and 71.
e, 73e, 75e and an OR gate 77e.

Mj when all "1" are set to I / O ports 70e, 72e, 74e, 76e
When the signal expanded by two pixels in the main scanning direction compared to the signal in which Ar124 is “1”, the signal is expanded by one pixel in the main scanning direction when I / O ports 70e, 75e “0” and 71e, 73e “1”. The output signal is output from Sig218e.

 Next, the remaining color removal processing circuit 16e will be described.

 FIG. 24 is a circuit diagram of the residual color removal processing.

In FIG. 24, 57e is a 3 pixel for selecting a minimum value of a total of 3 pixels of the pixel of interest and 1 pixel before and after the pixel of interest for the input signal 13e.
The min select circuit 58e selects a maximum value of a total of five pixels, that is, a target pixel and two pixels before and after the target pixel, for the input signal 13e. 5 pixel min select circuit, 55e is input signal 13e and I / O-18 (54
When 54e is larger than the comparator e), 1 is output. 61e and 62e are selectors, 53eD53'e
Is an OR gate and 63e is a NAND gate.

In the above configuration, the selector 60e is connected to the I / O from the CPU bus.
Based on the value of −19, select between 3 pixel min and 5 pixel min. The effect of removing the residual color is greater for 5 pixels min. This can be selected by manual setting of the operator or automatic setting of the CPU.

When the output of the NAND gate 63e is "0", that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and the selector 62e is in the range where the signal of the character portion is expanded, and 17'e is 1 In this case, the A side is selected; otherwise, the B side is selected. (However, at this time, the registers 52e and 64e are "1" and the register 52'e is "0".) When the B side is selected, the through data is output as 8e.

The EXCON 50e can be used instead of the comparator 55e when, for example, a binary signal of the luminance signal is input.

FIG. 25 shows the place where the above two processes have been performed. FIG. 25 (a) shows a black character N, and FIG. 25 (b) shows an area determined as a character in the Y, M, C data which is the shaded density data, that is, a character determination section (* 2, * 3, * 6, * 7)
Is set to 0 by subtraction processing, and * 1 and * 4 are set to * 1 ← * 0, * 4 ← * 5 by residual color removal processing.
Figure 25 (c) is required.

On the other hand, for B and data as shown in FIG.
Only the addition processing is performed on the character determination units (* 8, * 9, * 10, * 11), and an output with a black contour as shown in FIG. 25 is obtained.

Note that no change is made to the color characters as shown in FIG. 25 (f).

[2] Edge Enhancement or Smoothing Process Here, edge enhancement is performed for the character determination unit, smoothing is performed for the halftone dot portion, and a through output is performed for the others.

Character part → 3 of 25e, 27e, 29e since MjAR124 is “1”
The output of the 3 × 3 edge emphasis 30e generated from the line signal is selected by the selector 42e, and output from the 43e. Here, the edge enhancement is obtained from a matrix and a calculation formula as shown in FIG.

Halftone part → 27 because SCRN35e is “1” and MjAR21e is “0”
The result of the smoothing 31e applied to e is output by the selectors 33e and 42e. Here, smoothing as shown in Fig. 27, when the target pixel is a _{V N (V N + V N} + 1)
/ 2 process to V _N of data, that is, smoothing of the main scanning two pixels. This prevents moire that may occur in the halftone dots.

Other → Other part is a part other than a character part (character outline) or a halftone part, specifically, a process for a halftone part. At this time, since both the MjAR 124 and the SCRN 35e are "0", the data of 27e is output from the video output 43e as it is.

If the character is a colored character, the character
No processing is performed.

In the embodiment, the example in which the residual color is removed only in the main scanning direction is described. However, the residual color removal processing may be performed in both the main scanning and the sub-scanning.

[3] Character part 400 line (dpi) output processing The LCHG 140 is output from 48e in synchronization with the video output 113. Specifically, the inverted signal of MjAR124 is output in synchronization with 43e. LCHG = 0 for text part, 200/40 for other parts
0 = “1”.

As a result, the character portion determination unit, specifically, the outline portion of the character
At 400 lines (dbi), others are shot at 200 lines with a printer.

Next, the character image synthesizing circuit F will be described. FIG. 28 (a) shows processing of an image by a binary signal in the present apparatus,
It is a block diagram of a decoration circuit. The color image data 138 input from the image data input unit is input to the V input of the 3to1 selector 45. The other two inputs A and B of the 3to1 selector 45f are connected to the lower part (A _n ,
A _n is the A of B _n) 555f is, the B B _n is latched by VCLK117 in latch 44f, is input. Therefore, the output Y of the selector 45f includes the select inputs X ₀ , X ₁ , J1,
One of V, A, and B is output based on J2 (114). The data _Xn is the upper 2 bits of the data in the memory in this embodiment, and is a mode signal for determining processing and modification. 139
Are controlled so as to be switched in synchronization with the VCLK 117 under the control of the CPU 20 in FIG. 1 which is a code signal output from the area signal generating circuit, and are input as addresses of the memory 43f. That is, for example, (X ₁₀ , A ₁₀ , B ₁₀ ) = (01, A ₁₀ , B ₁₀ ) is written in advance at address 10 of the memory 43f,
As shown in FIG. 29 (b), if "10" is given to the code signal 139 from point P to point Q and "0" is given from point Q to point R in synchronization with the scanning of the main scanning direction line 1, Data between P and Q
X _n = (0,1) is read out, and at the same time, (A _n , B _n ) contains (A ₁₀ ,
Data that B ₁₀₎ is a latch output. As shown in FIG. 28 (c), the truth table of the 3to1 selector 45f is (X ₁ ,
X ₀₎ = (0,1) is the case of (B), J1 is a if A input it is "1" to Y, therefore, the constant A ₁₀ to Y, if J1 is "0" , V input to Y, that is, the input color image data is output to the output 114 as it is. Thus, for example, a so-called hair-cut character combination of a character portion having a value of (A ₁₀ ) is realized for a color image of an apple as shown in FIG. 29 (b). Similarly, (X ₁ ,
X ₀ ) = (1,0), and when a signal like J1 in FIG. 29 (C) is input to the binary input, the FIFOs 47f-49f and the circuit 46
f (details in FIG. 28 (b)) generates a signal as shown in J2 of FIG. 28, and according to the truth table of FIG. 28 (c), characters are set in the apple image as shown in FIG. (Contour or bag character). Similarly, in FIG. 28 (D), the rectangular area in the apple is output at the density of (B _n ), and the characters inside the apple are output at the density of (A _n ). Figure (A)
Is (X ₁ , X ₀ ) = (0,0), ie, any J1, J
Even for the change of 2, there is a control that does nothing depending on the binary signal.

According to FIG. 28 (b), the expanded signal input to J2 is an extension of 3 × 3 pixels, but it is easy to further increase the size by adding a hardware circuit.

Also, C0, C1 (366, 3) output from the I / O port 501 in FIG. 2 in association with the output color (Y, M, C, Bk) to be printed.
67) is input to the lower 2 bits of the address of the memory 43f, and therefore corresponds to “0, 0”, “Y”, “M”, “C”, and “Bk”.
Since it changes to “0,1”, “1,0”, “1,1”, for example, when outputting yellow (Y), addresses 0, 4, 8, 12, 16,..., Magenta (M)
Are 1,5,9,13,17 ... addresses, cyan (C) is 2,6,10,14,18 ...
For the address, black (Bk), addresses 3, 7, 11, 15, 19 ... are selected.
Therefore, in accordance with an operation instruction on the operation panel described later, an address corresponding to the area code signal 139 for determining the area and the corresponding memory address in the area, for example, X1 to X4 = "1,1"
(A1, A2, A3, A4) = (α1, α2, α3, α4), (B1, B2, B3,
B4) = (β1, β2, β3, β4), and when the J1 signal changes as shown in FIG. 29 (D), for example, J1 becomes “Lo”.
Is a color determined by (Y, M, C, Bk) = (α1, α2, α3, α4). When J1 is “Hi”, (Y, M, C, Bk) =
The color is determined by (β1, β2, β3, β4). That is, the output color can be arbitrarily determined based on the memory contents. on the other hand,
On an operation panel described later, Y, M, C, and Bk are each adjusted or set in (%) percent. That is, each gradation 8bit
Therefore, the numerical value is from 00 to 255, so that the 1% variation is a digital value of 2.55. Set value is (Y, M, C, Bk)
= (Y%, m%, c%, k%), the set values (ie, the values written to the memory) are (2.55y,
2.55m, 2.55c, 2.55k). In practice, a rounded integer is written to a predetermined memory. Further, if the adjustment mechanism adjusts in%, △%
It is sufficient to write the value obtained by adding (darkening) or subtracting (lightening) only 2.55 ° for the fluctuation of.

In the truth table of Figure No. 28 (c), column i is the character, image gradation, an output table of the resolution switching signal _{LCHG149, X 1, X 0,} J1, J2 by A or B output When output to Y, "0" is output, and when V is output to Y, the input is output as it is. LCHG149 is a signal for switching the printing density at the time of printing at the time of output, for example. When LCHG = "0", for example, 400 dpi, and when LCHG = "1", printing is performed at 200 dpi. Therefore, when A or B is selected, LCHG = 0 means that the inner area of the character synthesized is 400 dpi, and the area other than the character is 400 dpi.
It means printing at 200dpi, characters keep high resolution,
The halftone section is controlled so as to maintain a high gradation and output smoothly. As mentioned above, LCHG140 is
That is why the character image correction circuit E outputs the character based on the MJAR output from the character / image separation circuit I.

<Image processing / editing circuit> Next, the image signal after the color balance adjustment is received at P
115 and the gradation resolution switching signal LCHG141 are input to the image processing / editing circuit G. A rough schematic diagram of the image editing and processing circuit G is shown in FIG.

Input image signal 115, gradation resolution switching signal LCHG14
1 is first input to the texture processing unit 101g. The texture processing section is roughly divided into a memory section 103g for storing a texture pattern, memories RD and WR for controlling the memory section, an address control section 104g, and an arithmetic circuit 105g for performing a modulation process using the pattern stored for input image data. It is configured. The image data processed by the texture processing unit 101g is next input to the scaling, mosaic, and taper processing unit 102g. The variable magnification, mosaic, and taper processing unit 102g includes a double buffer memory 105
g, 106g and a processing / control unit 107g, and various processes are independently performed by the CPU and output. Here, the texture processing unit 101g and the scaling, mosaic, and taper processing unit 102g perform texture processing on independent areas by using GHi1 (119) and GHi2 (149), which are enable signals for each process sent from the switching circuit N. It is configured to perform mosaic processing.

The gradation resolution switching signal LCHG141 input together with the image data 155 is processed in various processes while adjusting the phase with the image signal. Hereinafter, the image processing / editing circuit G will be described in detail.

<Texture processing section> The texture processing is a processing of cyclically reading out the pattern written in the memory and modulating the video. For example, the image shown in FIG. The modulation is performed in such a pattern to generate an output image as shown in FIG.

FIG. 32 is a diagram for explaining the texture processing circuit.
Hereinafter, the writing section of the modulated data 218g to the texture memory 113g and the data from the texture memory 113g
The operation will be described separately for the calculation unit (texture processing) of 216g and image data 215g.

[Data writing unit to the texture memory 113g] At the time of writing data, the color correction circuit D that performs masking, under color removal, and extraction of smear Is output, and data is input from 201g. This data is selected by the selector 202g. On the other hand, the data 220g is selected by the selector 208g, and the data 220g is input to the ▼ of the memory 113g and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC and a horizontal counter 211g that counts up in synchronization with the image clock and VCK, B is selected by the selector 210g, and the address of the memory 113g is selected. input. Thus, the density pattern of the input image is written to the memory 113g. Usually, this pattern is located and written by an input device, for example, a digitizer.

[Data writing by CPU]

The CPU data is selected by the selector 202g. On the other hand, A is selected by the selector 208g, and is input to the ▼ of the memory 113g and the enable signal of the driver 203g. A is selected as the memory address by the selector 210g, and is input to the address of the memory 113g. Thus, an arbitrary density pattern is written to the memory.

(Texture memory 113g data 216g and image data 21
5g Operation Unit] This operation is realized by the operation unit 215g. This arithmetic unit is constituted by a multiplier here. Enable signal 12
The operation of the data 216g and 201g is performed only when 8g is active, and when the data is enabled, 201 is in a through state.

Also, 300g and 301g are the XOR and OR gates respectively, and the MJ signal 308
g, that is, when "0" is set in the register 304g "1" 305g, which is a portion for generating an enable signal using a character composite signal, the texturing process is applied to portions other than the portion containing the composite character signal. On the other hand, register 304g “0” 30
When "0" is set to 5g in the register, it is applied only to the part where the text processing is applied and the synthesized character signal is included.

Reference numeral 302g denotes a portion that generates an enable signal using the GHi1 signal 307g, that is, a non-rectangular signal. Register 306g “0”
At this time, texture processing is applied only to the place where the GHi1 signal is enabled. At this time, if enable 128 is kept active, non-rectangular texture processing synchronized with HSNC is performed if enable 128 is kept, and if enable signal GHi1 and enable 128 are made the same, non-rectangular signal is synchronized. This is a texture treatment. If a 31-bit signal is used for GHi1, for example, texture processing can be performed only on a certain color.

The LCHG _IN signal 141g is a gradation resolution switching signal,
Delayed by 215g and output from LCHG _OUT 350g.

<Mosaic, scaling, and taper processing unit> Next, the schematic operation of the mosaic, scaling, and taper processing unit G12 of the image processing / editing circuit G will be described with reference to FIG.

The image data 126g and the LCHG signal 350g input to the mosaic / magnification / taper processing unit 102g are first input to the mosaic processing unit 401g. The mosaic processing unit 401g determines the presence or absence of mosaic processing and the size of the mosaic in the main scanning direction based on the Mj signal 145 output from the character synthesizing circuit F, the area signal GHi2149 from the switching circuit N, and the mosaic clock MCLK from the mosaic processing control unit 402g. Are input to the 1to2 selector 403g. Here, the size of the mosaic process in the main scanning direction is variable by controlling the mosaic clock MCLK. The control of the mosaic clock MCLK will be described later in detail.

The 1to2 selector 403g outputs a line memory select signal LM obtained by dividing HSYNC118 by a D flip-flop 406G.
By SEL, input image signal and LCHG signal are converted to Y1, Y2
Output to either of

Output from Y1 of 1to2 selector 403g is line memory
A404g and A of 2to1 selector 407g. The output from Y2 is line memory B405g and 2
Connected to B of to1 selector 407g. When an image is sent from the selector 403g to the line memory A, the line memory A404g is in the write mode, and the line memory B405g is in the read mode. Similarly, when an image is sent from the selector 403g to the line memory B 405g, the line memory B is in the write mode, and the line memory A 404g is in the read mode. in this way,
The image data read alternately from the line memories A404g and B405g is output as continuous image data while being switched by the 2to1 selector 407g by the inverted signal of the output LMSEL signal of the D flip-flop 406g. 2to1
The output image signal from the selector 407g is sent to the enlargement processing unit next.
After a predetermined enlargement process is performed at 414g, it is output.

Next, write / read control of these memories will be described. First, when writing and reading, the line memory
The addresses following A404g and the line memory B405g are configured by up / down counters 409g and 410g so as to synchronize with HSYNC which is a reference of one scan, and to increment and decrement in synchronization with the image CLK. The counter enable signal output from the line memory address control unit 413g, the control signal WENB for controlling the write address generated from the scaling control unit 415g, and the control signal RENB for controlling the read address generate an address counter ( 409g, 410g) are operation-controlled. Each of these controlled address signals is a 2to1 selector 40
Input to 7g and 408g. When the line memory A404g is in the read mode, the 2to1 selectors 407g and 408g use the line memory selector signal LMSEL to set the read address to the line memory A404g and the write address to the line memory B40.
Give 5g. When the line memory A404g is in the write mode, the reverse operation is performed. Next, line memory
A, the memory write pulses WEA and WEB to the line memory B are output from the scaling controller 415g. Memory write pulse
WEA and WEB are controlled when the input image is reduced and when the mosaic processing is performed by the mosaic length control signal MOZWE in the sub-scanning direction output from the mosaic processing control unit 402g. Next, a detailed description of these operations will be described below.

<Mosaic processing> The mosaic processing is basically realized by repeatedly outputting one image data. This mosaic processing operation will be described with reference to FIG.

First, the mosaic processing control unit 402g independently performs main scanning and sub-scan mosaic processing control. First, variables corresponding to the desired mosaic size are stored in the latches 501g (for main scanning) and 502g (for sub-scanning) connected to the CPUBUS.
CPU set. First, for the mosaic processing in the main scanning direction, the same data is continuously written to a plurality of addresses of the line memory. For the mosaic processing in the sub-scanning direction, writing to the line memory is performed within a mosaic processing area by a predetermined line. This is done by thinning out each time4.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic width control counter 504g, and is configured to load a set value by the HSYNC signal and the ripple carry of the counter 504g. Latch 501g per HSYNC
The counter 504g loads the value set in (1), counts a predetermined value, and outputs the ripple carry to the NOR gate 502g and the AND gate 509g. The mosaic clock MCLK from the AND gate 509g is a signal wrapped around the image clock CLK by the ripple carry from the counter 504g.
MCLK is output only when the ripple carry is output. AN
The MCLK output from the D gate 509g is then sent to the mosaic processing unit 4
Entered in 01g.

The mosaic processing unit 401g includes two D flip-flops 51.
0g, flip-flop 510g is output irrespective of the Mj signal. When the GHi2 signal 149 is 1 and the Mj signal is 0, the flip-flop 511g controlled by the mosaic clock MCLK.
Is output. When the Mj signal is 1, the output outputs the signal from the flip-flop 510g. With this control, it is possible to output a part of the image in the mosaic processing image in the main scanning direction without performing the mosaic processing. That is, for a character synthesized in an image by the character synthesis circuit F at the preceding stage as shown in FIG. 2, mosaic processing of only the image can be performed without performing mosaic processing. The output from the selector 512g is input to the 2to1 selector 403g shown in FIG. 33 described above. As described above, the mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) The sub-scanning direction is also controlled by the latch 502g connected to the CPU BUS, the counter 505g, and the NOR gate 503g as in the main scanning. The sub-scan mosaic width control counter includes ITOP signals 144 and 511g, a selector 512g, an AND gate 514g, and an inverter 513g. Flip Flop 510g, 5
A tone resolution switching signal LCHG is connected to 11g in addition to the image signal.The flip-flop 510g holds the image clock CLK, the flip-flop 511g holds the image data input by the mosaic processing clock MCLK, and the LCHG signal. I do. In other words, the grayscale resolution switching signal LCHG corresponding to one pixel is flip-flopped in phase.
510g and 511g are held during the respective cycles of CLK and MCLK. Each held image signal and LCHG signal are input to a 2to1 selector 512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mi signal. Selector 512g The operation shown in the truth table in the left diagram is performed by the AND gate 514g and the inverter 513g. That is, the mosaic area signal
Synchronous when the GHi2 signal 149 is 0, and the HSYNC 118 is counted to generate a ripple carry pulse. As the lip carry pulse, the inverted signal ▼ of the mosaic area signal GHi2149 and the character signal Mi are input to the OR gate 508g. Sub-scan mosaic control signal MOZWE The signals are controlled as shown in the truth table on the left. The MOZWE signal output in such a combination is
A write pulse which is input to the scaling controller 415g and is generated by a line memory write pulse generator (not shown) is controlled by a NAND gate 515g. The line memory write pulse generation circuit is a circuit that can vary the output clock rate such as a rate multiplier generally used for scaling control.
This embodiment is different from the gist of the invention, and therefore, detailed description is omitted. The WR pulse controlled by the MOZWE signal
Switching signal LMS in which the switching pulse changes every SYNC118
The WR pulse is alternately output to WEA and WEB from the 1to2 selector by the EL signal. With the above control, even when the mosaic area signal GHi2 signal 149 is “1”, when the Mj signal becomes “1”, writing to the memory is performed, so that a part of the mosaic processing image in the sub-scanning direction is It is possible to output without mosaic processing. FIG. 35 (a) is a diagram showing a distribution of density values for each pixel for a certain recording color when mosaic processing is actually performed. In the mosaic processing of FIG. 35, each pixel in a 3 × 3 pixel block is set as a representative pixel value. In this processing, the mosaic processing is not performed on the character A, that is, the pixel in the hatched portion based on the character signal Mj. That is, when the combined character and the mosaic processing area overlap, the character can be given priority. Therefore, even when the mosaic processing is performed, an image can be formed so that only characters can be read. The mosaic area is not limited to a rectangle, and a mosaic process can be performed on a non-rectangular area.

(Italic and Taper Processing) First, the italic processing will be described with reference to FIGS. 33 and 36.

The inside of the line memory address control unit 413g shown in FIG.
This is shown in FIG. This line memory address controller 413g
Controls the enable signal of the write / read counters 409g and 410g, and controls the address counter to determine which part in one line of main scanning is to be written to or read from the line memory, so that movement, italics, etc. can be performed. It is possible. First, the enable control signal generation circuit will be described with reference to FIG.

As for the counter 701g, the HSYNC counter output becomes 0,
Then image clock 11 which is the clock of counter 701g
Count seven. The output Q of the counter 701g is input to iso-surface comparators 706g, 708g, 709g, and 710g. The A input side of each comparator other than the comparator 709g is connected to an independent latch (not shown) connected to the CPU BUS.
When the output matches, a pulse is output. The output of the iso-surface comparator 706g is the J of the JK flip-flop 708g.
And the comparator 707g is connected to the K input,
After the comparator 706g outputs a pulse, the comparator
JK flip-flop until 707g outputs pulse
708g is configured to output 1. This output is used as a write address counter control signal, and the write address counter is in an operation state only in a period where it is 1, and an address is generated for the line memory. Similarly, the read address counter control signal is used to control the read address counter. Here, the selector 703g is connected to the input signal to A of the comparator 709g in order to make the input value to the comparator different between when the italic processing is performed and when it is not performed. Here, when the italic processing is not performed, the value set in the latch connected to the CPUBUS (not shown) is input to the A input of the selector 703g, and the A input is similarly selected by the select signal output from the latch (not shown). Output from 703g. Subsequent operations are performed by the comparators 706g and 707g described above.
This is the same operation as. When performing italic next, the selector
The value input to A of 703g is also input to the selector 702g as a preset value. Selector 702g, 703g
When the select signal of B selects the B input, the selector
The output of 702g is an adder 704g, which also performs addition with a value set in a latch (not shown). Here, this value indicates the amount of change for each line due to the oblique angle, and can be obtained by tan θ when the desired angle is θ. Addition result is HSYNC
The data is input to a flip-flop 708g having a clock 118, and the value is held during one main scan. Flip flop
The output of 705g is connected to the B input of selector 702g and the B input of selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter can be changed at a constant rate from HSYNC. As a result, reading from the line memories A404g and B405g is shifted with respect to HSYNC, and italic processing can be performed. In addition, the above-mentioned change amount may be either positive or negative.
If it is negative, it shifts toward HSYNC. Also,
By changing the select signals of the selectors 702g and 703g in synchronization with HSYNC, it is possible to form a part of italic.

The enlargement processing method generally includes methods such as 0th-order, 1st-order, and SINC interpolation. However, since it is different from the gist of the present invention, the description is omitted. The taper processing is enabled by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing italic processing.

In these processes, the input gradation resolution switching signal is processed while adjusting the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG142 are output to the edge enhancement circuit.

The conceptual diagram of the italic processing and taper processing explained above
These are shown in FIGS.

FIG. 37 (a) is a block diagram showing details of a bit map memory 537L for masking for limiting an area of an arbitrary shape and its control. This memory has a shape as shown in FIG. 37 (e), for example, and is used to turn on various image processing and editing such as the above-described color conversion, image cutting (non-rectangular trimming), image painting (non-rectangular painting), and the like. This signal is used as a switching signal for processing and OFF (not processing). That is, in FIG. 2, BHi123 and BHi122 are used for switching signals of the color conversion circuit B, the color correction circuit D, the character synthesis circuit F, the image processing / editing circuit G, the color balance circuit P, and the external device image synthesis circuit 502, respectively. , FHi121, GHi
119, PHi145, and AHi148 signal lines.

As shown in FIG. 38, the mask is configured such that 4 × 4 pixels constitute one block, and one block corresponds to one bit of the bit map memory.
For an image having a pixel density of 297 mm × 420 mm (A3 size), (297 × 420 × 16 × 16) ÷ 16 ≒ 2 Mbit, that is, for example, a dynamic RAM of 1 Mbit and 2 chips can be configured.

Signal 132 input to FIFO559L in FIG.
Is a data input line for generating a mask as described above. For example, the output 421 of the binarization circuit 532 in FIG.
When it is input as 2, it is input to buffer 559L, 560L, 561L, 562L for 1 bit × 4 lines in order to count the number of “1” in the 4 × 4 block. FIFO559L ~ 562L
As shown in the figure, the output of 559L is connected to the input of 560L, the output of 560L is connected to the input of 561L, and the output of each FIFO is latched in parallel by 4 bits to latches 563L to 565L and VCLK (No. (See the timing chart in Fig. 37 (d).) FI
FO output 615L and Latch 563L, 564L, 565L output 616
L, 617L, and 618L are added by adders 566L, 567L, and 568L (signal 602L), and I / O is performed by the CPU 22 in the comparator 569L.
The value set via the port 25L (for example, “12”) is compared with its magnitude. That is, it is determined whether the number of 1s in the 4 × 4 block is larger than a predetermined number.

In FIG. 37 (d), the number of "1" s in the block N is "14" and the number of 1s in the block (N + 1) is "4", so that the output of the comparator 569L in FIG. 603L is a signal
When 602L is "14", it is "1" because it is larger than "12", and when it is "4", it is "0" because it is smaller than "12". Therefore, the latch pulse 605L shown in FIG. 4 × 4
Is latched once per block of, Q output of the latch 570 is D _IN input of the memory 573L, that is, the mask making data. Reference numeral 580L denotes an H address counter for generating an address in the main scanning direction of the mask memory. One address is assigned by 4 × 4 blocks.
The count is incremented by the clock obtained by dividing 8 by 4 by the frequency divider 577L. Similarly, 575L is an address counter for generating an address in the sub-scanning direction of the mask memory. For the same reason, the frequency divider 574L outputs the synchronization signal HSYNC of each line to 4 bits.
Counted up by the divided clock, H address, V
The operation of the address is controlled so as to synchronize with the operation of counting (adding) "1" in the 4.times.4 block.

Also, the lower 2 bits output of the V address counter, 610
L and 611L are NORed by a NOR gate 572L, and a signal 606L for gating a clock 607L of 4 frequency division is generated, and AND gate
As shown in Fig. 37 (c), timing chart by 571L
A latch signal 605L is generated so that only one latch is performed in 4 × 4 blocks. Also, 616L is CPU bus 22
(FIG. 2) is a data bus included therein, 613L is an address bus similarly, and a signal 615L is a write pulse WR from the CPU 22. At the time of WR (write) operation from the CPU 22 to the memory 573L, the write pulse becomes “Lo” and the gate 578 is output.
L, 576L, 581L are opened, the address bus and data bus from the CPU 22 are connected to the memory 573L, and predetermined data is written at random, and the WR (write), RD When reading, the gate 576 'connected to the I / O port 25
The gates 576'L and 582L are opened by the control lines L and 582L, and a sequential address is supplied to the memory 573L.

For example, if the mask as shown in FIG. 39 is formed by the output 421 of the binarized output 532 or the CPU 22, the image can be cut out and synthesized based on the area within the thick line frame.

Further, the bit map memory of FIG. 37 (a) can be read out by thinning out or interpolation in both the H and V directions at the time of reading. That is, as shown in FIG. 40 in detail of the H or V address counter (580L, 575L) of FIG.
MULSEL636L is set to "0" to select an input.
Reference numeral 635L denotes a thinning circuit (rate multiplier) for the input clock 614L. As shown in FIG. 41 (timing diagram), the input clock 614L is thinned out, for example, so that CLK is output once every three times (setting is performed by an I / O port). 641L) (637L). 630L
For example, when the value "2" is set and the thinned output 637L is output, the outputs 638L and 633 of the address counter 632L are output.
The value set to 0L (eg, "2") is added and the result is loaded into the counter. Therefore, as shown in FIG. 41, the progress proceeds by "+2" every three clocks in the order of 1 → 2 → 3 → 5 → 6 → 7 → 9. On the other hand, when expanding, MULSEL
= "1" and the A input 614L is selected, so that the address count proceeds as 1 → 2 → 3 → 3 → 4 → 5 → 6 → 6 →... As shown in the timing chart of FIG.

FIG. 40 shows the details of the H address counter 580L and the V address counter 575L of FIG. 37, and since the hardware circuits are the same, the description will be limited to FIG. 37 only.

As a result, enlargement 2 and reduction 1 are generated for the non-rectangular area 1 immediately input as shown in FIG. 42. Therefore, once the non-rectangular area is input, no new input operation is performed. In addition, the magnification can be changed by one mask plane according to various magnifications.

Next, the binarization circuit (FIG. 2 532) and the high-density binary memory circuit K will be described. FIG. 43 (a) shows a binarization circuit.
Reference numeral 532 denotes a circuit for comparing the video signal 113 output from the character image correction circuit E with a threshold value 141k to obtain a binary signal. The threshold value is set by the CPU bus 22 in conjunction with the operation unit. That is, the threshold value is 43
When the memory of the operation unit in FIG. 9C is designated as M (middle point), the value is “128”. As the scale moves in the + direction, the value changes by −30 from the middle point, and as the scale moves in the − direction, “+30” changes. "Everything changes. Therefore, “weak → −2 → −1 → M → + 1 → + 2
The threshold value is “218 → 188 → 158 → 128 → 98 →
It is controlled to change from 68 to 38 ".

As shown in FIG. 43 (a), two threshold values are set from the CPU BUS 22, and are switched by the selector signal 35k by the switching signal 151, and are set as the threshold values in the comparator 32k. The switching signal 151 is set to a different threshold value only in the specific area set by the digital tiger 58.For example, the threshold value is relatively low in a monochromatic area of a document and relatively high in a mixed color area. By setting, it is possible to always obtain a uniform binary signal regardless of the color of the document.

The memory circuit K is a memory for storing a signal in which the binarized signal 421 is output to 130 for one page of an image. In the present device, the image is handled at A3, 400 (dpi), so that the memory circuit K is approximately 32 Mbit. Have. FIG. 43B illustrates details of the memory circuit K. Input data D _IN 130
It is gated by the enable signal HE528, and is input to the memory unit 37k when the W / 1 output of the IO port 23k controlled by the CPU 20 at the time of writing is "Hi". At the same time, the synchronization signal HSYNC 118 in the main scanning (horizontal scanning) direction is counted from the synchronization signal ITOP 144 in the vertical direction of the image, and a vertical address is generated. The image transfer clock VCLK 117 is counted by the V address counter 35k and the HSYNC 118, and the horizontal address is counted. An address corresponding to the storage of the image data is generated by the H address counter. Memory WP input at this time (write timing signal)
A clock having the same phase as the clock VCLK117 is input to the 551k as a strobe, and the input data Di is sequentially stored in the memory section.
Stored in 37k (timing diagram, Fig. 44) Memory 37k
When reading data from, set the control signal W / 1 to “Lo”
Then, the output data _DOUT is read out in exactly the same procedure. However, since both writing and reading of data are performed by the HE528, for example, as shown in FIG.
The E528 at an input timing of the D _2, raised to "Hi", the fall in "Lo" at an input timing of D _m, the memory 37k is
From D ₂ only the image up to D _m is entered, D _0, D ₁ and D
_No data is written after _{m + 1} , and data "0" is written instead. The same applies to reading, except that data is read as "0" except during the section in which HE is "Hi".
HE is output from an area signal generation circuit 17 described later. That is, for example, when a character document as shown in FIG. 45A is placed on the document table, if the HE is generated as shown in FIG. The converted image can be stored in the memory. Similarly, unnecessary characters and the like can be erased and written to the memory.

Further, the address counters 35k and 36k for reading the data of the memory 37k operate in the same configuration as in FIG. 40 and at the same timing as in FIG. 41.
Can be scaled. Therefore, when a binary character image as shown in FIG. 46B, which is stored in the main memory in advance as shown in FIG. 46, is combined with the image shown in FIG. As shown in FIG. 4D, the composition such as enlarging only the character portion to be composed without changing the size of the sketch (portion A) is possible.

FIG. 47 shows each image of the data from the binary bitmap memory L for non-repeated masking (FIG. 2) and the 400 dpi binary memory K for character and line images (FIG. 2) stored at 100 dpi as described above. This is a switching circuit for switching between distribution to the processing blocks A, B, D, F, P, and G and distribution of binarized video images to the memories L and K. The mask data for limiting the non-rectangular area stored in the memory L is sent to, for example, the above-described color conversion circuit B (BHi123), and, for example, the color data is written only inside the shape as shown in FIG. Conversion takes. No.
In FIG. 47, 1n is an I / O port connected to the CPU bus 22, 8n
Reference numerals 13n denote 2to1 selectors, which are configured to output the A input when the switching input S = "9" and the B input when S = "0" to Y. Therefore, for example, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B as described above, A is selected by the selector 9n, that is, 28n = "1", AND
In the gate 3n, the 21n input may be set to "1". Similarly, other signals can be arbitrarily controlled by 16n to 31n. I /
Outputs of O port n1, 30n and 31n are binarization circuits 532 (Fig. 2)
Is a control signal as to which of the binary memories L and K is to be stored, the binary input 421 is 100 dpi memory L when 30n = "1"
When 31n = "1", the data is input to the 400 dpi memory K. By the way, when AHi148 = "1", the image data sent from the external device is synthesized. When BHi123 = "1", the color conversion is performed as described above. When DHi122 = "1", the color correction circuit is used. More monochrome image data is calculated and output. Hereinafter, FHi 121, PHi 145, GHi1 119, and GHi2 149 are used for character synthesis, color balance change, texture processing, and mosaic processing, respectively.

As described above, there are two binary memories of the 100 dpi memory L and the 400 dpi memory K, and character information is input to the high density 400 dpi memory K, and area information (including rectangles and non-rectangles) is input to the 100 dpi memory L. Thus, character synthesis can be performed in a predetermined area, particularly in a non-rectangular area.

Further, by having a plurality of bit map memories, a color processing as shown in FIG. 62 becomes possible.

FIG. 49 is a view for explaining the area signal generation circuit J. The region means, for example, a portion like a hatched portion in FIG. 49 (e), which is a section of the timing chart AREA of FIG. Such signals are distinguished from other areas. Each area is specified by the digitizer 58 in FIG. FIGS. 49 (a) to 49 (d) show a configuration in which the generation position, section length, and number of sections of the area signal can be obtained by the CPU 20 in a programmable manner. In this configuration, one area signal is generated by one bit of a RAM accessible to the CPU. For example, in order to obtain n area signals AREA0 to AREAn, an n-bit RAM is used.
(Fig. 49 (d) 60j, 61j). Now, the fourth
When obtaining a region signal AREA0 and AREAn such as Figure 9 (b), set a "1" in bit 0 of the address of the RAM x _1, x _3,
Bits 0 of the remaining addresses are all set to "0". Meanwhile, RA
Make a "1" to M address 1, x _1, x _2, x _4, and that all the bits n of other addresses "0". HSYNC118 in synchronism with the constant clock 117 as a reference, As you read sequentially Shikenshiyaru data RAM for example, as to the 49 Figure (c), the data in terms of addresses x ₁ and x ₃ "1" is read out It is.
The read data is shown in FIG. 49 (d) 62j-0 to 62j.
The output is a toggle operation, that is, "1" is read out from the RAM and CLK is input, so that the output becomes "0" → "1", “1” →
Changing to "0", an interval signal such as AREA0, and thus an area signal, is generated. When data = "0" over all addresses, no area section occurs and no area is set. FIG. 47 (d) shows this circuit configuration, where 60j and 61j are the RAMs described above. This is because the CPU 20 (FIG. 2) performs a memory write operation for setting a different area to the RAMB 61j while reading data from the RAMA 60j line by line to switch the area section at high speed. As described above, the section generation and the writing to the memory from the CPU are alternately switched. Therefore, when the shaded area in FIG. 49 (f) is designated, the RA is changed to A → B → A → B → A.
MA and RAMB are switched. If (C ₃ , C ₄ , C ₅ ) = (0,1,0) in FIG. 49 (d), the counter output counted by VCLK 117 becomes an address. Selector 63
The gate 66j is opened and the gate 68j is closed and read out from the RAMA 60j, and the entire bit width and n bits are read out from the RAMA 60j through the j-k flip-flops 62j-0 to 62j-j.
n and an interval signal of AREA0-AREAn is generated according to the set value. Writing from B to the CPU is performed by the address bus A-Bus, the data bus D-Bus, and the access signal / during this time. Conversely, when generating a section signal based on the data set in the RAMB61j (C ₃ , C
₄ , C ₅ ) = (1,0,1) to do the same, CPU
Can write data to RAMA60j.

Reference numeral 58 denotes a digitizer for specifying an area.
Enter the coordinates of the specified position from 0 through the I / O port. For example, in FIG. 50, when two points A and B are designated, A (X ₁ ,
The coordinates of Y ₂ ) and B (X ₂ , Y ₁ ) are input.

FIG. 51 shows an interface circuit M for performing bidirectional communication of image data with an external device connected to the image processing system. 1m is an I / O port connected to the CPU bus 22, and outputs signals 5m to 9m for controlling the directions of the data buses A0 to C0, A1 to C1, and D. 2m and 3m are bus buffers having an output dry-state control signal E, and 3m is D bus
The direction can be changed by input. 2m, 3m is E
When the input is “1”, a signal is output. When the input is “0”, the output is in a high impedance state. 10m selects one from three parallel inputs A, B, and C using selection signals 6m and 7m.
It is a selector. In this circuit, basically, there is a bus flow of 1. (A0, B0, C0) → (A1, B1, C1), 2. (A1, B1, C1) → D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, as shown in FIG. 53, images input from external devices through A1, A2, and A3 can be rectangular as shown in FIG. 53 (A) or non-rectangular as shown in FIG. 53 (B). It has a configuration. When inputting in a rectangular shape as shown in FIG. 53 (A), the switching input of the selector 503 in FIG.
A control signal 147 is output from the I / O port 501 so as to set “1” so that A is selected. At the same time, it corresponds to the area to be combined. As described above, the CPU writes the predetermined data to the predetermined addresses of the RAMs 60j and 61j (FIG. 51) in the area signal generation circuit J, thereby generating the rectangular area signal 129. In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and the resolution switching signal 140 are simultaneously switched. That is, in the area where the image from the external device is input, the image is generated based on the character area signal MIAR 124 (FIG. 2) detected from the color separation signal of the image read from the document table. tone,
By stopping the resolution switching signal and forcibly setting it to "Hi",
An image area from an external device to be fitted is smoothly output with high gradation. As described with reference to FIG. 51, the bit map mask signal from the binary memory L
When selected by the signal 147 in the AHi148
Image synthesis from an external device as shown in FIG. 53 (B) is realized.

<Overview of Operation Section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. A key 1100 is a copy start key. The key 1100 is a reset key, which returns all settings on the operation unit to the values at power-on. A key 1102 is a clear stop key used to reset the input numerical value such as the number of copies and to stop the copying operation. A group of keys 1103 is a numeric keypad used for inputting numerical values such as the number of copies and magnification. A key 1104 is a document size detection key. A key 1105 is a center movement designation key. A key 1106 is an ACS function (black original recognition) key. When ACS is ON, copy a single black color original in black. A key 1107 is a remote key for giving control to a connected device. Key 1108 is a preheat key.

Reference numeral 1109 denotes a liquid crystal screen for displaying various information. Also, the surface of the screen is a transparent touch panel, and when pressed with a finger or the like, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies,
The copy density is displayed. While various copy modes are being set, the screens required for mode setting are sequentially displayed.
(The copy mode is set using the keys displayed on the screen.) The self-diagnosis display screen of the guide screen is displayed.

A key 1100 is a zoom key, and is an enter key for a mode for specifying a magnification ratio. A key 1111 is a zoom program key, and is an enter key for a mode for calculating a magnification ratio from a document size and a copy size. Key 1112
Is an enlargement transfer key, which is an enter key for the enlargement transfer mode. A key 1113 is a key for setting the fit synthesis. A key 1114 is a key to be set in character synthesis. Key
Reference numeral 1115 denotes a key for setting a color balance. Key 1116
Is a key for setting a color mode such as black / negative / positive inversion. A key 1117 is a user's color key, and an arbitrary color mode can be set. A key 1118 is a paint key, and can set a paint mode. A key 1119 is a key for setting a color conversion mode. A key 1120 is a key for setting a contour mode. A key 1121 sets a mirror image mode. Keys 1124 and 1123 specify trimming and masking. An area can be designated with the key 1122, and the internal processing can be set differently from other parts.
A key 1129 is an enter key for a mode for performing operations such as reading a texture image. A key 1128 is an enter key for a mosaic mode such as changing a mosaic size.

A key 1127 is a key for entering a mode for adjusting the sharpness of an edge of an output image. A key 1126 is a key for setting an image repeat mode for outputting a designated image repeatedly.

A key 1125 is a key for applying italic / taper processing or the like to an image. A key 1135 is a key for changing the movement mode. A key 1134 is used to make settings such as continuous page copying and arbitrary division. A key 1133 is used to make settings relating to the projector.
A key 1132 is an enter key for a mode for controlling a connected device of the option. The key 1131 is a recall key, and can recall settings up to three times before. Key 1130 is an asterisk key. Keys 1136 to 1139 are mode memory call keys, which are used when calling the registered mode memory. Keys 1140 to 1143 are program memory recall keys, which are used when recalling a registered operation program.

<Color Conversion Operation Procedure> The procedure of the color conversion operation will be described with reference to FIG.

First, when the color conversion key 1119 on the main body operation unit is pressed, the display unit 1109 is displayed like P050. Place the original on the digitizer and specify the color before conversion with the pen. When the input is completed, the screen of P050 is displayed. Here, the width of the color before conversion is adjusted by using the touch keys 1050 and 1051, and the touch key 1052 is pressed after the setting is completed. The screen changes to P052, and the touch key 1053 and the touch key 1054 are used to select whether to add shades to the converted color. When the shade is selected, the converted color also has a gradation according to the shade of the color before the conversion. That is, the above-described gradation color conversion is performed. On the other hand, if no shading is selected, it is converted to a designated color having the same density. If you select “with / without shading”, the screen changes to P053 and the type of color after conversion is selected. In P053
When 1055 is selected, the operator can specify any color in P054. When the color adjustment key is pressed, the processing shifts to P055, and color adjustment can be performed for each of Y, M, C, and Bk in increments of 1%.

Pressing 1056 in P053 moves to P056, where the point pen is used to specify the desired location of the original on the digitizer. Next, in P057, the shading of the color can be adjusted.

When 1057 is pressed in P053, the process proceeds to P058, where a predetermined registered color can be selected by a number.

<Procedure for Specifying Trimming Area> Hereinafter, referring to FIGS. 56 and 57, the procedure for specifying the trimming (similarly to the masking method, and also to the partial processing, etc., is the same procedure). explain.

Press the trimming key 1124 on the main unit operation unit 100, and when the display unit 1109 becomes P001, enter the two diagonal points of the rectangle using the digitizer to display the screen of P002, and then enter the rectangular area continuously. it can. When multiple areas are specified, the area key 1001 before P001, then the area key
By pressing 1002, each designated area in the XY coordinates can be confirmed as in P002.

On the other hand, in this embodiment, a non-rectangular area can be designated using the bit map memory. While the screen of P001 is displayed, press the touch key 1003 to move to P003. Here you choose the sentence. When the required coordinate values are input for the circle, oval, and R rectangle, the penalty is expanded to the bitmap memory by calculation. In the case of a free shape, coordinate values are continuously input by tracing a desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap memory.

 Hereinafter, each of the non-rectangular area designations will be described.

(Circular area command) When the key 1004 is pressed in P003, the display unit 1109 shifts to P004 and can specify a circular area.

Hereinafter, the circular area command will be described with reference to the flowchart of FIG. In S101, the center point is input from the digitizer 58 in FIG. 2 (P004). Next, the display unit 1109
Moves to P005, and inputs one point on the circumference of a circle having a radius to be designated from the digitizer 58 in S103. In step S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bit map memory L (100 dpi binary memory) shown in FIG.

In S107, the coordinate value of another point on the circumference is calculated. Next, in S109, the bank of the bit map memory L is selected,
In S111, the above calculation result is input to the bit map memory L via the CPU bus 22. In FIG. 37 (a), the CPU DAT
The data is written from the A 616L to the bit map memory from the 604L via the driver 578L. The address control is the same as that described above, and will not be described. This is repeated for all points on the circumference (S113), and the designation of the circular area ends.

Instead of inputting while calculating with the CPU 20 as described above, the template information for the previously input two points of information is stored in the ROM 11, and the two points are directly specified without calculation by designating with a digitizer. The data may be written in the bitmap memory L.

(Oval area specification) Pressing the key 1005 in P003 moves to P007. The following
This will be described with reference to the flowchart in FIG.

First, in step S202, two diagonal points of the largest rectangular area inscribed in the ellipse are designated by the digitizer 58. Hereinafter, for the circumferential portion, S206 to S212 are performed in the same manner as in the case of the circular region command.
Is written to the bit map memory L by the following procedure.

Next, the linear portion is written into the memory L in the steps S214 to S202, and the area command is terminated. As in the case of a circular shape, it can be stored in advance in the ROM 21 as template information.

(Specification of R rectangular area) This is the same as the method of the instruction as in the case of the oval in both the memory writing and the description is omitted.

Although the case of a circle, an ellipse, and an R rectangle has been described above as an example, it is needless to say that other non-rectangular areas can be specified based on the same template information.

In P006, P008, P010, and P102, when the clear key (1009 to 1012) is pressed after each shape input, partial deletion on the bit map memory can be performed.

Therefore, even if you make a specification mistake,
Only point designation can be cleared and only two point designations can be performed again.

In addition, it is possible to continuously specify a plurality of areas. In the case of specifying a plurality of areas, the processing of the area specified later is prioritized in performing each processing on the overlapping area. However, for this, the priority may be given to the one specified earlier.

FIG. 57 shows an output example in which trimming is performed on an ellipse with the above settings.

<Operation Procedure for Character Synthesis> The operation setting procedure for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When the character synthesis key 1114 on the main body operation unit is pressed, the liquid crystal display unit 1109 is displayed as P020. When the character document 1201 to be synthesized is placed on the document table and the touch key 120 is pressed, the character document is read, binarized, and the image information is stored in the bit map memory shown in FIG. Since the specific means of the processing has been described above, duplication is avoided. To specify the range of the image to be stored at this time, press the touch key 1021 in P020 to go to the screen of P021, place the character document 1201 on the above-mentioned digitizer 58, and specify the range with two points using the digitizer's point pen. I do. When the specification is completed, the display unit becomes P022, and selects whether to read in the range specified by the touch keys 1023 and 1024 (trimming) or to read outside the specified range (masking). Further, for some character documents, it is difficult to extract a character portion in the character document during the above-described binarization process. In this case P020
Use the middle touch key 1022 to move to the screen of P023, and change the slice level of the binarization processing to the touch key 1025 and the touch key.
It can be adjusted in 1026.

Since the slice level can be manually adjusted in this manner, appropriate binarization processing can be performed according to the color and thickness of the characters on the document.

Further, by pressing the touch key 1027 and designating an area with P024 'and P025', it is possible to partially change the slice level at P026 '.

In this way, by specifying the area and changing the slice level only for that part, even if there is, for example, a yellow character in a part of the black character original, separate appropriate slice levels are set for each of the black and yellow characters By doing so, good binarization processing can be performed on the entire character.

When the reading of the text original is completed, the display unit 1109 displays the P024 in FIG. 61.
become that way.

To select the color skipping process, press the touch key 1027 in P024 to move to the screen of P025, and select the color of the character to be synthesized from the displayed colors. In addition, the color of the text can be changed partially.In that case, press the touch key 1029 to move to the screen of P027, specify the area, and then
Select the text color on the screen. Further, a color bordering process can be added to the border of the character to be synthesized. In this case, the screen is shifted to the screen of P032 by the touch key 1031 in P030, and the color of the border portion is selected. At this time, the color can be adjusted in the same manner as in the color conversion. Plus Touch Key 10
Press 33 to adjust the border width on the screen of P041.

Next, a case will be described in which a color covering process is added to a rectangular area including a character to be combined (hereinafter, referred to as a mud process). P024
Press the middle touch key 1028 to move to the screen of P034 and specify the area. Mado processing is performed in the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen shifts to P039, and the color of the mud is selected.

In the above color selection, for example, on the screen of P025, by pressing the color adjustment key of the touch key 1030,
Screen, and the color tone of the selected color can be changed.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an output example when the setting is actually performed.

In the area specification, a non-rectangular area as described above can be specified in addition to the rectangular area specification.

<Texture processing setting procedure> Next, the texture processing will be described with reference to FIG.

When you press the texture key 1129 on the main body operation unit 1000,
The display 1109 displays like P060. To apply texture processing, press the touch key 1060 to highlight this key. When the image pattern for texture processing is read into the above-mentioned texture image memory (113g in FIG. 32), the touch key 1061 is pressed. At this time, if the pattern is already in the image memory, the display is P061 if it is not displayed, as in P062. By placing the original of the image to be read on the original platen and pressing the touch key 1062, the image data is stored in the texture image memory. At this time, in order to read an arbitrary portion of the original, press the touch key 1063 and display the digitizer 58 on the P063 screen.
Specify by. The specification can be made by inputting a pen with one point at the center of the reading range, 16 mm × 16 mm.

Reading of the texture pattern by specifying one point as described above can be performed as follows.

Without touching the pattern, press the touch key 1060 to set the texture processing, and
00 or another mode key (1110-1143) or touch key
When trying to escape the P064 screen with 1064 etc., the display section
Give a warning as shown on page 065.

This range can also allow the operator to specify the length and width.

<Mosaic Processing Setting Procedure> FIG. 64 is a view for explaining the procedure of the mosaic processing setting.

Press the mosaic key 1128 on the operation panel to display P1
It is displayed as 00. To apply a mosaic process to the original, press the touch key 1400 and highlight this key.

To change the mosaic size at the time of performing the mosaic processing, press the touch key 1401 to perform the change on the P101 screen. The change of the mosaic size can be set independently in both the vertical (Y) direction and the horizontal (X) direction.

<Regarding * Mode Operation Procedure> FIG. 65 is a diagram for explaining the * mode operation procedure.

Pressing the * key 1130 on the main body operation unit 1000 enters the * mode, and the display unit 1109 is displayed as P110. Touch key
The 1500 enters a color registration mode for registering color information used in paint user's color, color conversion, color characters, and the like. A touch key 1501 turns on / off a function of correcting an image missing by the printer. A touch key 1502 is a key for entering a mode memory registration mode. The touch key 1503 enters a mode for specifying a manual feed size. Touch key 1504 enters program memory registration mode. Touchy key 1505
Is a key for entering a mode for setting a default value of the color balance.

(About the color registration mode) Pressing the touch key 1500 when P110 is displayed enters the color registration mode. The display section is as shown in P111, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color to be changed on the screen of P116, and adjust the values of the yellow, magenta, cyan, and black components on the screen of P117 in 1% increments. be able to.

To register an arbitrary color on the original, touch
Press 1507, select the registration destination number on the screen of P118, designate using the digitizer 58, set the original on the platen at the time of the screen of P120, and press the touch key 1501 to register.

(About manual feed size specification) As shown on page 112, the manual feed size can be specified for both standard and non-standard sizes.

For an irregular shape, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding Mode Memory Registration) The mode set as shown in P113 can be registered in the mode memory.

(Regarding Program Memory Registration) As shown in P114, a series of programs for performing area designation and predetermined processing can be registered.

(About color balance registration) As shown in P115, it is possible to register the color balance for each of Y, M, C, and Bk.

<Regarding the Program Memory Operation Procedure> The registration operation to the program memory and its use procedure will be described below with reference to FIGS. 66 and 67.

The program memory is a memory function for storing an operation procedure related to the setting and reproducing the procedure. It is possible to connect necessary modes and skip unnecessary screens. As an example, a program memory is used to perform a procedure of performing image repetition by scaling a certain area in a document.

Press the * mode key 1130 on the operation panel of the main unit.
Display the screen of P080 and press the program memory of the touch key 1200. In this embodiment, four programs can be registered. Select the number to be registered on the screen of P081. Thereafter, the mode shifts to the program registration mode. In the program registration mode, for example, a screen 1301 shown in FIG. The skip key of the touch key 1302 is specified when the user wants to skip the current screen. The clear key of the touch key 1303 is used to stop the registration up to now while registering the program memory and to restart the registration from the beginning. The end key of the touch key 1304 bypasses the registration mode of the program memory, and registers it in the memory of the number determined first.

First, a trimming key 1124 in the main body operation unit is pressed, and an area is designated by a digitizer. The display unit displays P084. If no more area is to be set here, the user touches the touch key 1202 to specify that this screen should be skipped. (The screen is P085.) Next, when the zoom key 1110 on the main body operation unit is pressed, the display unit becomes P086. Here, set the magnification, and touch
Pressing 03 changes the display to P087. Finally, press the image repeat key 1126 on the operation panel of the main unit, set the image repeat on the screen of P088, and then touch the
To register in the first of the program memory.

To call the program registered in the above procedure, the program memory 1 call key 1140 on the main body operation unit is pressed. The display unit displays P091, and waits for an input of an area.
Here, when the area is input using the digitizer, the display unit displays P092, and further proceeds to next P093. When the touch key 1210 is pressed after setting the magnification here, the display becomes P094, and image repeat can be set. When the touch key 1211 is pressed, the mode using the program memory (called the trace mode) is exited. Until the program memory is called and the program memory is terminated, each key of the edit mode (1110-
1143) is disabled, and operations can be performed according to the registered program.

FIG. 69 shows a program memory registration algorithm. Turning the screen in S301 means rewriting the display on the display unit with a key or a touch key. When the user presses the touch key 1302 to specify that the currently displayed screen is to be skipped (S303), the information is set on the recording table when the next screen is turned (S305). Then, a new screen number is set in the recording table in S307. When the clear key is pressed, the entire recording table is cleared (S309, S31
1) In other cases, return to S301 and move to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen turning in S401, it is determined whether or not the new screen is a standard screen (S403). In the case of the standard screen, the process proceeds to S411, in which the next screen number is set from the recording table. If the screen is not the standard image, the new screen number is compared with the screen number scheduled in the recording table (S405). Is S4
Move to 09, if there is a skip flag, skip S411 and S4
Return to 01. If they are not equal, a recovery process is performed (S407), and the screen is turned.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide an image processing apparatus which can efficiently remove an isolated point included in data to be processed and is suitable for identifying a tone of each pixel of an input image. Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall view of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a circuit diagram of image processing according to an embodiment of the present invention, FIG. FIG. 4 is a circuit diagram for generating ODRV118a and EDRV119a, FIG. 5 is a diagram for explaining black correction operation, FIG. 6 is a circuit diagram for shading correction, FIG. 7 is a color conversion block diagram, FIG. 8 is a block diagram of a color detector, FIG. 9 is a block diagram of a color conversion circuit, FIG. 10 is a diagram showing a specific example of color conversion, FIG. 11 is a diagram for explaining logarithmic conversion, and FIG. 13 is a diagram showing an unnecessary transmission region of the filter, FIG. 14 is a diagram showing an unnecessary absorption component of the filter, FIG. 15 is a circuit diagram of a character image region separation circuit, and FIG. 16 is a contour. Fig. 17 illustrates the concept of regeneration, Fig. 17 illustrates the concept of contour regeneration, and Fig. 18 illustrates a loop. FIG. 19 is an outline regenerating circuit diagram, FIG. 20 is a timing chart of EN1 and EN2, FIG. 21 is a block diagram of a character image correction unit, FIG. 22 is an explanatory diagram of addition / subtraction processing, and FIG. FIG. 24 is a circuit diagram of a switching signal generation circuit, FIG. 24 is a circuit diagram of a residual color removal processing, FIG. 25 is a diagram for explaining residual color removal processing and addition / subtraction processing, FIG. 26 is a diagram showing edge emphasis, and FIG. FIG. 28 is a diagram for explaining processing and modification processing by a binary signal, FIG. 29 is a diagram showing characters and image synthesis, FIG. 30 is a block diagram of an image editing and processing circuit, and FIG. 31 is a texture. FIG. 32 is a circuit diagram of a texture process, FIG. 33 is a circuit diagram of a mosaic, scaling, and taper process, FIG. 34 is a circuit diagram of a mosaic process, and FIG. 35 describes a mosaic process and the like. FIG. 36 is a circuit diagram of a line memory address control unit, and FIG. 37 is a mask circuit. FIG. 38 is a diagram showing an address, FIG. 39 is a diagram showing a specific example of a mask, FIG. 40 is a circuit diagram of an address counter, FIG. 41 is a timing chart for enlargement / reduction, FIG. FIG. 43 is a diagram showing a specific example of enlargement / reduction, FIG. 43 is an explanatory diagram of a binarization circuit, FIG. 44 is a timing chart of an address counter, FIG. 45 is a diagram showing a specific example of bit map memory writing, FIG. FIG. 46 is a diagram showing a specific example of text and image synthesis, FIG. 47 is a circuit diagram of distribution switching, FIG. 48 is a diagram showing a specific example of a nonlinear mask, FIG. 49 is a circuit diagram of a region signal generation circuit, FIG. FIG. 50 is a diagram showing area designation by a digitizer, FIG. 51 is an interface circuit diagram with an external device, FIG. 52 is a truth table of a selector, FIG. 53 is a diagram showing an example of a rectangular region and a non-rectangular region, FIG. 54 is an external view of the operation unit, and FIG. 55 explains a procedure of a color conversion operation. FIG. 56 is a diagram illustrating a procedure for specifying a trimming area, FIG. 57 is a diagram illustrating a procedure for specifying a trimming area, FIG. 58 is a diagram illustrating an algorithm for specifying a circular area, and FIG. FIG. 60 is a diagram showing an algorithm for specifying an area of an R rectangle, FIG. 60 is an explanatory diagram of an operation procedure of character synthesis, FIG. 61 is an explanatory diagram of an operation procedure of character synthesis, FIG. Fig. 63 is a diagram illustrating the procedure of the texture processing, Fig. 64 is a diagram illustrating the procedure of the mosaic process, Fig. 65 is a diagram illustrating the procedure of the * mode operation, and Fig. 66 is a procedure of the program memory operation. Fig. 67 explains the procedure of the program memory operation, Fig. 68 illustrates the procedure of the program memory operation, Fig. 69 shows the algorithm of the program memory registration, Fig. 70 shows the program Memory recall Shows an algorithm of operation after, 71 figure is a diagram showing a Fomatsuto the record table.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kimyo Hayashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Toshio Honma 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Yoshiko Usui 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-54-47636 (JP, A) JP-A-54-59035 (JP) , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 17/21-17/26 G06K 9/36-9/60 G06T 1/00-5/50 H04N 1/38-1 / 40

Claims (1)

(57) [Claims] An input unit for inputting image data; a first processing unit for performing a thinning process on the image data to narrow an image represented by the image data; and a first processing unit. A second processing unit for performing a fattening process on the output image data so as to fatten an image represented by the image data; and a second processing unit configured to input the input image data using the output of the second processing unit. And an identification means for identifying an image tone of an image represented by the image data.