JP3352085B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus that digitally processes an input image and performs various types of image processing on the image.

[Related Art] In recent years, color originals have been color-separated and read for each pixel.
2. Description of the Related Art Digital color copiers for obtaining digital color hard copies by digitally processing read image data and outputting the processed data to a color printer are becoming widespread. This type of device has the advantage that image data can be processed digitally, so that the image output position can be moved (FIG. 72 (a)) or a desired image region can be extracted (FIG. 72 (a)).
(FIG. 72 (b)), color conversion of only a certain color in a desired area (FIG. 72 (c)), and fitting of characters and images stored in a memory to a reflection original (FIG. 72 (d)). ) And various other image processings are possible, and applications in the field of so-called color copying are expanding.

Therefore, by combining various functions, it can be easily applied to a color plan, an advertisement poster, a promotional material, a design drawing, and the like.

On the other hand, there is a growing demand for characters to be more character-like and images to be more image-like for color reflective originals.
In contrast, character areas and image areas are separated by image area separation, and high-resolution processing is applied to the character area, especially black characters are processed in a single black color, while high gradation processing is applied to the image area. Has been proposed by the present applicant.

[Problems to be solved by the invention]

However, in the above conventional example, (1) when a binary color character image is combined with a reflection original, for example, an image area discrimination for identifying the outside of the character area is performed on the image of the reflection original, and if the printing conditions are different based on that, When such processing is performed, there is a disadvantage that the printing conditions affect the synthesized character portion.

Further, even when the printing condition is not changed in the composite character portion, since high resolution processing is not performed, a high resolution character image cannot be obtained.

(2) A case where a color image is combined with a reflective original When the same processing as in (1) is performed on a reflective original, there is a disadvantage that the printing conditions affect the composite image portion.

Even when the printing conditions are not changed in the composite color image portion, since high gradation processing is not performed, a high gradation color image cannot be obtained.

The present invention has been made in view of the above-described problems, and has as its object to output a high-quality image based on the characteristics of a binary image such as a character and other color images. An object of the present invention is to enable high-quality images to be output by control.

<Means for Solving the Problems> In order to solve the above-described problems, the image processing apparatus of the present invention superimposes and outputs a binary image and another multi-valued color image according to a given instruction. Superimposing / combining output means for switching between a high-resolution line-number image forming output and a high-gradation line-number image forming output for a combined image based on a binary image before being combined by the superimposing / combining means. Control means for controlling the superposition / combination output means as described above.

Further, the control means forms a high-resolution line frequency image in an area of the binary image in the image output by the synthesis output means, based on the binary image before being synthesized by the superimposition synthesis output means. Output, forming a high gradation frequency image in the area of the other multi-valued color image, and outputting a high resolution frequency image in the area where the binary image and the other multi-valued color image overlap. It is a control means for outputting.

The image processing apparatus further includes a determination unit configured to determine an image attribute of the other multi-valued color image combined by the combination output unit,
The control means performs control based on a result of the determination by the determination means.

Still further, the synthesis output means is means for converting the other multi-valued color into density information and then synthesizing it with the binary image.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. This system is equipped with a digital color image reader (hereinafter, referred to as
A color reader 1 is provided, and a digital color image printing apparatus (hereinafter, referred to as a color printer) 2 is provided below. This color reader 1 is provided with a color separation unit described later.
The color image information of the original is read for each color by a photoelectric conversion element such as a CCD, and is converted into an electric digital image signal. The color printer 2 is an electrophotographic laser beam color printer that reproduces a color image for each color in accordance with the digital image signal, and transfers the color image onto a recording sheet a plurality of times in a digital dot form and records the image.

 First, an outline of the color reader 1 will be described.

Reference numeral 3 denotes a document, 4 denotes a platen glass on which the document is placed, and 5 denotes a rod door for condensing a reflected light image from the document scanned and exposed by a halogen exposure lamp 10 and inputting the image to a 1: 1 full-color sensor 6. Ray lenses, 5, 6, 7, and 10 are integrally scanned as an original scanning unit 11 to perform exposure scanning in the direction of arrow A1. The color-separated image signal read line by line during exposure scanning is output to a sensor output signal amplifying circuit 7.
After that, the signal is amplified to a predetermined voltage by a signal line 501 and input to a video processing unit to be described later, where the signal is processed. Details will be described later. 501 is a coaxial cable for ensuring a faithful transmission of a signal. A signal 502 is a signal line for supplying a drive pulse for the 1: 1 full-color sensor 6, and all necessary drive pulses are generated in the video processing unit 12.
Reference numerals 8 and 9 denote a white plate and a black plate for white level correction and black level correction of an image signal, which will be described later. By irradiating with a halogen exposure lamp 10, a signal level of a predetermined density can be obtained, respectively. Used for white level correction and black level correction of signals. Reference numeral 13 denotes a control unit having a microcomputer, which controls the display, key input control and video processing unit 12 on the operation panel 1000 by a bus 508, and the position of the document operation unit 11 by signal lines 509 and 510 by the position sensors S1 and S2. Control via a signal line 503 to control the stepping motor drive circuit for pulse driving the stepping motor 14 for moving the scanning body 11, and turning on / off the halogen exposure lamp 10 by the exposure lamp driver via the signal line 504. All controls of the color reader unit 1 such as OFF control, light amount control, control of the digitizer 16 and internal keys via the signal line 505, and control of the display unit are performed. A color image signal read by the above-described exposure scanning unit 11 at the time of document exposure scanning is input to the video processing unit 12 via the amplifier circuit 7 and the signal line 501, and subjected to various processes described later in the main unit 12. Is transmitted to the printer unit 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be described. Reference numeral 711 denotes a scanner, which is a laser output unit that converts an image signal from the color reader 1 into an optical signal, a polyhedron (for example, an octahedron)
, A motor (not shown) for rotating the mirror 712, an f / θ lens (imaging lens) 713, and the like. 714 is a reflection mirror that changes the optical path of laser light, 7
Reference numeral 15 denotes a photosensitive drum. The laser beam emitted from the laser output unit is reflected by the polygon mirror 712, passes through the lens 713 and the mirror 714, scans the surface of the photosensitive drum 715 linearly (raster scan), and forms a latent image corresponding to the original image. .

Also, 711 is a primary charger, 718 is an overall exposure lamp, 723
Is a cleaner section for collecting the residual toner not transferred,
724 is a pre-transfer charger, and these members are the photosensitive drum 7
It is located around 15.

A developing unit 726 develops an electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure.
1Y, 731M, 731C, and 731Bk are development sleeves that perform direct development in contact with the photosensitive drum 715, 730Y, 730M, 730C, and 730Bk are toner hoppers that hold spare toner, and 732 is a screw that transfers developer. , These sleeves 731Y-73
1Bk, toner hopper 730Y ~ 730Bk and screw 732
Constitutes a developing unit 726, and these members are disposed around the rotation axis P of the developing unit. For example, when a yellow toner image is formed, yellow toner development is performed at the position shown in the figure, and when a magenta toner image is formed, the developing unit 726 is rotated about the axis P in the figure to expose the photosensitive element. The developing sleeve 731M in the magenta developing device is disposed at a position in contact with the body 715. The development of cyan and black operates in the same manner.

Reference numeral 716 denotes a transfer drum that transfers the toner image formed on the photosensitive drum 715 to paper, and 719 denotes a transfer drum 716.
An actuator plate 720 for detecting the movement position of the actuator, a position sensor 720 for detecting that the transfer drum 716 has moved to the home position by approaching the actuator plate 719, a transfer drum cleaner 725, a transfer drum cleaner 727
Is a paper pressing roller, 728 is a static eliminator, and 729 is a transfer charger. These members 719, 720, 725, 727, 729 are transfer rollers 7
It is located around 16.

On the other hand, 735,736 is a paper feed cassette for storing paper (sheets), 737,738 is a paper feed roller for feeding paper from the cassette 735,736, and 739,740,741 are timing rollers for timing of paper feed and conveyance, and via these. The paper fed and conveyed is guided by a paper guide 749 and wrapped around the transfer drum 716 while the leading end is held by a gripper described later,
The process proceeds to the image forming process.

Reference numeral 550 denotes a drum rotation motor, and the photosensitive drum 715
750 rotates the transfer drum 716 synchronously. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed.
Is a transport belt that transports the removed paper, 743 is an image fixing unit that fixes the paper that has been transported by the transport belt 742, and the image fixing unit 743 has a pair of thermal pressure rollers 744 and
745.

The image processing circuit according to the present invention will be described in detail with reference to FIG. This circuit exposes a full-color original with an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and converts the obtained analog image signal into an A / D converter. A color image copying apparatus that processes and processes the digitized full-color image signal, outputs it to a thermal transfer type color printer, an ink jet color printer, a laser beam color printer, etc. (not shown) to obtain a color image, or A color image signal is input from a computer, another color image reading device, or a color image transmitting device, and is subjected to processing such as synthesis, and is applied to a color image output device for outputting to the aforementioned color printer. Things.

In FIG. 2, A is an image reading unit, which is a staggered CCD line sensor 500a, a shift register 501a, a sample / hold circuit 502a, an A / D converter 503a, a shift correction circuit 504a, a black correction / white correction circuit 506a, and a CCD driver. 533a, panel generator 534
a, composed of an oscillator 558a.

B is a color conversion circuit, C is a LOG conversion circuit, D is a color correction circuit, O is a line memory, E is a character image correction circuit, F is a character synthesis circuit, P is a color balance circuit, G is an image processing and editing circuit, and H is Is an edge enhancement circuit, I is a character image region separation circuit, J is a region signal generation circuit, K is a binary memory of 400 dpi,
L is a 100 dpi binary memory, M is an external device interface, N is a signal switching circuit, 532 is a binarization circuit, and R is a printer driver such as a laser driver of a laser beam printer or a BJ head driver of a bubble jet printer. Is a printer unit including a driver R.

58 is a digitizer, 1000 is an operation unit, 1000 'is an operation interface, 18, 19 are RAM, 20 is CPU, 21 is ROM, 22
Is a CPU bus, and 500 and 501 are I / O ports.

The original is first irradiated by an exposure lamp (not shown),
The reflected light is color-separated for each image by the color reading sensor 500a and read, and is amplified to a predetermined level by the amplifier circuit 501a. 533a is a CCD driver that supplies a pulse signal for driving the color reading sensor, and the necessary pulse source is the system control panel generator 53
Generated in 4a.

FIG. 3 shows a color reading sensor and a driving pulse. FIG. 3A shows a color reading sensor used in the present example.
Assuming that μm is one pixel (400 dots / inch (hereinafter referred to as dpi)), since 1024 pixels, that is, one pixel is divided into three in the main scanning direction by G, B, and R as shown in the figure, a total of 1024 × 3 = 3
072 effective pixels. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the first, third, and fifth (5
8a, 60a, 62a) are on the same line LA, and the second and fourth are 4
Line L separated by line (63.5 μm × 4 = 254 μm)
It is arranged on B and scans in the direction of arrow AL when reading a document.

The driving pulse group ODRV118a is the first, third, and fifth of each of the five CCDs.
The second and fourth are driven independently and synchronously by the EDRV 119a. O01A, O02A, ORS included in ODRV118a
And E01A, E02A, and ERS included in EDRV119a are the charge transfer clock and charge reset pulse in each sensor, respectively. It is generated completely synchronously so as not to be in the jitter. For this reason, these pulses are generated by one reference oscillation source OSC558.
a (FIG. 2).

FIG. 4 (a) is a circuit block for generating ODRV 118a and EDRV 119a, and FIG. 4 (b) is a timing chart, which is included in the system control pulse generator 534a in FIG. Original clock CLK0 generated from a single OSC558a
Clock K0135a is a clock for generating reference signals SYNC2, SYNC3 for determining the timing of ODRV and EDRV generation, and SYNC2, SYNC3 are presettable counters 64a, set by the signal line 22 connected to the CPU bus. The output timing is determined according to the set value of 65a, and SYNC2 and SYNC3 initialize frequency dividers 66a and 67a and drive pulse generators 68a and 69a. That is, based on the HSYNC 118 input to this block as a reference, all the pulses are generated by the CLK0 output from one oscillation source OSC558a and the frequency-divided clocks generated in synchronization with each other, so that the respective pulses of the ODRV118a and the EDRV119a The groups are obtained as synchronized signals without any jitter, and signal disturbance due to interference between sensors can be prevented.

Here, the sensor drive pulses obtained in synchronization with each other
ODRV118a is connected to the first, third and fifth sensors 58a, 60a and 62a, and the EDRV119a
Is supplied to the second and fourth sensors 59a and 61a, and the respective sensors 58a and 59a
a, 60a, 61a, 62a
1 to V5 are output independently, amplified to a predetermined voltage value by independent amplifier circuits 501-1 to 501-5 for each channel shown in FIG. 2, and passed through a coaxial cable 101a as shown in FIG.
The signals V1, V3, and V5 are transmitted at the timing of OOS 129a, and the signals of V2 and V4 are transmitted at the timing of EOS 134a, and input to the video image processing circuit.

A color image signal obtained by reading the original input to the video image processing circuit by dividing it into five divisions is G (green), B (blue), and R by the sample / hold circuit S / H502a.
(Red) are separated into three colors. Therefore, after S / H, signal processing of 3 × 5 = 15 systems is performed.

The analog color image signal sampled and held for each color R, G, B by the S / H circuit 502a is converted to a next-stage A / D conversion circuit 503.
In a, each 1-5 channel is digitized, and each 1-channel
The data is output to the next stage in parallel for 5 channels independently.

In this embodiment, as described above, four lines (63.5
(μm × 4 = 254 μm) in the sub-scanning direction, and the original is read by five staggered sensors divided into five regions in the main scanning direction. At 1, 3, and 5, the reading position is shifted. Therefore, in order to connect these correctly, the misalignment is corrected by a misalignment correction circuit 504a having memories for a plurality of lines.

Next, a black correction / white correction circuit 506a will be described with reference to FIG.
Will be described. As shown in FIG. 5B, the black level outputs of the channels 1 to 5 have large variations between chips and between pixels when the amount of light input to the sensor is small.
If this is output as it is to output an image, streaks and unevenness occur in the data portion of the image. Therefore, it is necessary to correct the output variation of the black portion, and the correction is performed by a circuit as shown in FIG. Prior to the original reading operation, the original scanning unit is moved to a position of a black plate having a uniform density arranged in the non-image area at the leading end of the original platen to turn on the halogen and to input a black level image signal to this circuit. As for the blue signal B _IN , one line of this image data is stored in the black level RAM 78a.
A is selected by the selector 82a to store it in the
Close 0a () and open 81a. That is, the data line is 151
a → 152a → 153a, while RAM78a address input 1
55a is initialized by ▲ ▼, and the output to the selector 83a is output so that the output 154a of the address counter 84a that counts VCLK is input, and a black level signal for one line is stored in the RAM 78a (the above is referred to as black). This is called a reference value acquisition mode).

At the time of image reading, the RAM 78a is in the data reading mode, and is read and input for each line and one pixel to the B input of the subtractor 79a via the data line 153a → 157a. That is, at this time, the gate 81a closes () and the gate 80a opens (). The selector 86a has an A output. Therefore,
The black correction circuit output 156a is, for example, B _IN (i) −DK (i) = B in the case of a blue signal with respect to the black level data DK (i).
_OUT (i) (referred to as black correction mode). Similarly, the green G _IN and the red R _IN are similarly controlled by 77aG and 77aR. The control lines of each selector gate for this control are connected to the CPU 22 (FIG. 2).
This is performed under CPU control by a latch 85a assigned as an I / O of the CPU. The RAM 78a can be accessed by the CPU 22 by selecting the selectors 82a, 83a, 86a by B.

Next, white level correction (shading correction) in the black correction / white correction circuit 506a will be described with reference to FIG. In the white level correction, the sensitivity variation of the illumination system, the optical system, and the sensor is corrected based on the white data when the original scanning unit is moved to the position of the uniform white plate and irradiated. FIG. 6 (a) shows a basic circuit configuration. The basic circuit configuration is the same as that shown in FIG. 5 (a), except that the black correction is performed by the subtractor 79a, whereas the white correction uses a multiplier 79'a. Therefore, the description of the same part is omitted.

At the time of color correction, when the CCD (500a) for reading the original is at the reading position (home position) of the uniform white plate, that is, before the copying operation or the reading operation,
An unillustrated exposure lamp is turned on, and image data of a uniform white level is stored in the correction RAM 78'a for one line. For example, if it has a width in the main scanning direction A4 longitudinal direction, 16pe
16/297 mm = 4752 pixels in l / mm, that is, at least the capacity of the RAM is 4752 bytes. As shown in FIG. 6 (b), assuming that white plate data Wi (i = 1 to 4752) of the i pixel, the RAM 78 '
As shown in FIG. 6 (c), data for a white plate for each pixel is stored in a.

On the other hand, for Wi, the data Do corrected to the read value Di of the normal image of the i-th pixel should be Do = Di × FF _H / Wi. Then, the CPU 85 sends the latches 85'a ',',
Gates 80'a and 81'a are opened for 'and', and selectors 82'a, 83'a and 86'a output so that B is selected, and the RAM 78'a can be accessed by the CPU. Next, according to the procedure shown in FIG. 6 (d), the CPU 22 sets the first pixel Wo to FF _H / Wo, W ₁
FF / W ₁ ... Are sequentially operated to replace data. When the process is completed for the blue component of the color component image (FIG. 6D)
Step B) Similarly, the green component (Step G) and the red component (St
epR), and thereafter, the gate 80'a so that Do = Di × FF _H / Wi is output for the input original image data Di.
Is open ('), 81'a is closed ('), and selectors 83'a, 8
A is selected for 6'a, and the coefficient data FF _H / Wi read from the RAM 78'a passes through the signal line 153a → 157a, is multiplied by the original image data 151a input from one, and is output. .

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the variation of the sensitivity between each sensor, the variation of the light intensity of the optical system, and the sensitivity of the white level. Over the scanning direction,
Image data B _OUT uniformly corrected for each color for both white and black
101, G _OUT 102 and R _OUT 103 are obtained. The obtained color-separated image data of which the white and black levels have been corrected are obtained by detecting pixels on an image having a specific color density or a specific color ratio according to an instruction from an operation unit (not shown), and performing the same operation. The data is sent to a color conversion circuit B for performing data conversion to another color density or a color ratio specified by the unit.

<Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit of FIG. 7 is an 8-bit color separation signal R _IN , G
_IN , B _IN (1b to 3b), a color detection unit 5b for determining an arbitrary color set in the register 6b by the CPU 20, an area signal Ar4b for performing color detection and color conversion for a plurality of locations, A signal (hereinafter referred to as a hit signal) output from the color detection unit and indicating that the color is a specific color is referred to as a "hit signal" in the main scanning direction and the sub-scanning direction (the seventh direction).
In the example of the figure, only the line memories 10b to 11b for performing the process of expanding in the sub-scanning direction, the OR gate 12b, and the expanded hit signal 3
AND gate 32b from 4b and non-rectangular signal (including rectangle) BHi27b
The color conversion enable signal 33b, the enable signal 33b and the input color separation data (R _IN , G _IN , B _IN 1b to 3b) generated in the above, and line memories 13b to 16 for synchronizing the area signal Ar4
b, delay circuits 17b to 20b, enable signal 33b, synchronized color separation data (R _IN ', G _IN ', B _IN '21b to 23
b), register 2 is determined by area signal Ar'24b and CPU 20.
The color conversion unit 25b that performs color conversion based on the color data after the color conversion set in 6b, the color separation data (R
_OUT , G _OUT , B _OUT 28b-30b), and a hit signal H _OUT 31b output in synchronization with R _OUT , G _OUT , and B _OUT .

Next, an outline of an algorithm for gradation color determination and gradation color conversion will be described. Here, the gradation color determination and the gradation color conversion are the same hue color determination and the same hue color for performing the color conversion while preserving the density value for the color having the same hue in performing the color determination and the color conversion. To do the conversion.

Same color (there hue), for example the ratio between-intensity signal R ₁ and the green signal G ₁ and Blue signal B ₁ is possible is known equal.

Therefore, one of the colors to be converted (here, the maximum value color,
Select data M ₁ below referred to as primary colors), therewith obtaining the ratio of the other two colors data. For example, the M ₁ = R ₁ when the main color is R, Ask for.

Then, for the input data R _i , G _i , B _i , M ₁ × γ ₁ ≦ R _i ≦ M ₁ × γ ₂ (3) where α ₁ , β ₁ , γ ₁ ≦ 1 α ₂ , β ₂ , γ ₂ ≧ 2 judge.

Further, also for the data (R ₂ , G ₂ , B ₂ ) after the color conversion, the ratio between the data M ₂ of the primary color (here, the maximum value color) and the data of the other two colors is obtained.

For example, when G ₂ is the primary color, M ₂ = G ₂ , Ask for.

Then, the input data to the main color M _1, Ask for.

If the data is a color conversion pixel, If the pixel is not a color conversion pixel, (R _i , G _i , B _i ) is output.

As a result, it is possible to detect all portions of the same hue having a gradation and output color conversion data corresponding to the gradation.

FIG. 8 is a block diagram showing an example of the color judgment circuit.
This part is a part for detecting a pixel to be color-converted.

In this figure, 50b is a smoothing unit for smoothing the input data of R _IN b1, G _IN b2, and B _IN b3, and 51b is a selector for selecting one of the outputs (primary colors) of the smoothing unit.
52b _R , 52b _G , 52b _B are the outputs of the selector 51b and the fixed values R ₀ , G ₀ , B ₀
Selector for selecting one _{of, 54b R, 54b G, 54b} B is OR _{gate, 63b, 64b R, 64b G} , 64b B are each area signal Ar10, A
The selector 51b based on the r20, 52b _R, 52b _G, selector for excisional a select signal _{52b B, 56b R, 56b G} , 56b B and 57
b _R , 57b _G and 57b _B are multipliers for calculating the upper and lower limits, respectively.

Also, each upper limit ratio register 5 set by CPU 20
8b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B can set data for color detection for a plurality of areas based on the area signal Ar30.

Here, Ar10, Ar20, and Ar30 are signals generated based on Ar4b in FIG. 7, and each has a required number of DF / Fs. Also
61b is an AND gate, 62b is an OR gate, and 67b is a register.

Next, the actual movement will be described. R _IN b1, G _IN b2, B
Data R ', G', B 'obtained by smoothing _IN b3
One of the, CP20 and select the selector 51b by the select signals S ₁ which is excisional primary color data is selected.
Here, the CPU 20 sets different data A and B in the registers 65b and 66b respectively, and the selector 63b sets the data A and B in accordance with the Ar10 signal.
Input to the selector 51b as a select one of then S ₁ signal.

In this way, two registers 65b and 66b are prepared, and different data are input to A and B of the selector 63b, and the area signal Ar10
By selecting one of them, separate color detection can be performed for a plurality of areas. This area signal Ar10 may be a signal for a non-rectangular area as well as a rectangular area.

In the next selectors 52b _R , 52b _G , 52b _B , either the R ₀ , G ₀ , B _{0 set} by the CPU 20 or the main color data selected by the selector 51b is output to the outputs 53ba to 53bc of the decoder 53b and fixed colors. is select by a select signal generated by the mode signal S _2. The selectors 64b _R , 64b _G , and 64b _B output the area signal
By selecting either A or B according to Ar20, it is possible to detect different colors for a plurality of areas as in the case of the selector 63b. here,
R ₀ , G ₀ , and B ₀ are selected for the main color in the conventional color conversion (fixed color mode) and gradation color determination, and the main color data is selected for a color other than the main color in the gradation color conversion. .

The operator can freely select the fixed color determination and the gradation color determination from the operation unit. Alternatively, for example, it is also possible to change by software according to color data (color data before color conversion) input from an input device such as a digitizer.

From the outputs of these selectors 52b _R , 52b _G , 52b _B and the upper limit ratio registers 58b _R , 58b _G , 58b _B and the lower limit ratio registers 59b _R , 59b _G , 59b _B set by the CPU 20, R ′,
The upper and lower limit values of G ′ and B ′ are multipliers 56b _R , 56b _G and 56b _B
And 57b _R, 57b _G, is calculated by 57 b _B, the window comparator 60b _R, 60b _G, is set as the upper and lower limit values in 60b _B.

In the window comparators 60b _R , 60b _G , and 60b _B , it is determined by the AND gate 61b whether or not the main color data falls within a certain range and two colors other than the main color fall within a certain range. The register 67b can set "1" regardless of the determination signal by the enable signal 68b of the determination unit. In that case, the part to which "1" is set has a color to be converted.

With the above configuration, the fixed color determination or the gradation color determination can be performed for a plurality of areas.

FIG. 9 is a block diagram of an example of the color conversion circuit. This circuit selects a signal that has undergone color conversion or an original signal based on the output 7b of the color determination unit 5b.

In FIG. 9, the color conversion unit 25b includes a selector 111b and registers 112b _R1 , 112b _R2 , 112b _G1 , 112b _G2 , 112b for setting respective ratios of the converted color to the main color data (here, the maximum value).
_B1, 112b _B2, the multiplier _{113b R, 113b G, 113b B} , the selector 114b _R,
114b _G , 114b _B , selector 115b _R , 115b _G , 115b _B , AND gate 3
2b, Ar5 generated based on area signal Ar'24 in FIG. 7
0, Ar60, Ar70 the data selector 111b to be excisional by CPU 20, the multiplier _{113b R, 113b G, 113b B} , the selector 114
b _R , 114b _G , 114b Selectors 117b, 112b _R , 112 set to _B
b _G , 112b _B , 116b _R , 116b _G , 116b _B and a delay circuit 118b.

 Next, the actual movement will be described.

The selector 111b receives the input signals R _IN '21b, G _IN ' 22b, B _IN '
One of 23b (main color) is selected according to the select signal S5. Here, the signal S5 is generated when the area signal Ar40 selects the selector 117b to either A or B for the two data set by the CPU 20. In this way, color conversion processing can be performed on a plurality of areas.

The signal selected by the selector 111b is applied to multipliers 113b _R , 11
In 3b _G and 113b _B , multiplication with the register value set by the CPU 20 is performed. Again, the area signal Ar50 has two register values 112b _R1 , 112b _R2 , 112b _G1 , 112b _G2 , 112b _B1 , 112b
By selecting _B2 by the selectors 112b _R , 112b _G , and 112b _B , different color conversion processes can be performed on a plurality of areas.

Next, the results of the multiplication by the selectors 114b _R , 114b _G and 114b _B and
Two fixed values Ro '/ Ro ", Go'-Go", Bo' set by 20
Selectors 116b _R , 116b _G ,
One of the fixed values selected in 116b _B is selected by the mode signal S6. Here, as the mode signal S6, a signal selected by the area signal Ar60 in the same manner as in S5 is used.

Finally selector 115b _R, 115b _G, 'with _{R IN ", G IN",} B IN "(R IN' select signal S _B in 115b _B, G _IN ',
_BIN 'delayed and timing adjusted) and selector 1
Either 14b _R , 114b _G or 114b _B output is selected,
Output as R _OUT , G _OUT , B _OUT . Hit signal H _OUT
Are also output in synchronization with R _OUT , G _OUT , and B _OUT .

Here, the selector signal S _B ′ is obtained by delaying the AND of the color determination result 34b and the color conversion enable signal BHi34b. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on the non-rectangular area. In this case, the area signal is a region such as a one-dot chain line, that is, the uppermost left position (FIG. 10a), the uppermost right position (FIG. 10b), the lowermost left position (FIG. 10c), and the lower left position obtained from the dotted line. It is generated by the coordinates (Fig. 10d). The non-rectangular area signal BHi is an area signal input from an input device such as a digitizer and expanded in a 100 dpi binary memory L. When color conversion is performed using this non-rectangular enable signal, the enable area can be specified along the boundary of the area to be converted, so that the threshold for color detection can be expanded as compared with the conventional color conversion using a rectangle. it can. Therefore, it is possible to obtain an output image in which the detection capability is improved and the gradation color conversion is performed with high accuracy.

From the above, color conversion having lightness according to the main color of the color determination unit 5b (for example, when converting red to blue gradation color, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion Can be freely performed on a plurality of regions.

Further mosaic only specific color area (non-rectangular or square) based on Hitsuto signal H _OUT as described later, Tekusuchiya process, trimming process may be subjected to a masking process or the like.

The area signals Ar10, Ar20, Ar30, and Ar70 are signals generated based on Ar4b, and the area signals Ar40, Ar50, Ar60, and Ar70 are signals generated based on Ar'24b.
Although this is based on the area signal 134 shown in FIG. 2, not only the rectangular area signal as described above, but also a non-rectangular area signal may be used. That is, stored in 100dpi binary memory,
The non-rectangular area signal BHi based on the non-rectangular area information may be used.

The generation of the BHi signal will be described later. The BHi signal can include both rectangular and non-rectangular area signals.

As described above, according to the present embodiment, a color conversion area can be set based on not only a rectangular area signal but also a non-rectangular area signal, so that more accurate color conversion processing can be performed.

Then, as shown in FIG.
Reference numeral 4,105 denotes a logarithmic conversion circuit C for converting image data proportional to the reflectance into density data, a character image area separation circuit I for determining a character area and a halftone area, a halftone area on a document, and the present system. The data is transmitted to the external device interface M for exchanging data with the external device via the cables 135, 136, and 137.

Next, the color image data proportional to the input light quantity is input to a logarithmic conversion circuit C (FIG. 2) which performs processing for matching the human eyes with the relative luminous efficiency characteristics.

Here, white = 00 _H, is as much as possible converted black = FF _H, further image source input to the image reading sensor, such as a conventional reflective originals, transmission original such as a film Puroji EKTAR and negative film in the same transparent original Since the sensitivity of the positive film or the film and the gamma characteristics input in the exposure state are different, as shown in FIGS. 11 (a) and 11 (b), there are a plurality of LUTs (lookup tables) for logarithmic conversion. And use them according to the purpose. The switching is performed by the signal lines lg0, lg1, lg2, and is performed by inputting an instruction from an operation unit or the like as an I / O port of the CPU 22 (FIG. 2). Here, the data output for each B, G, R is
It corresponds to the density value of the output image. For each signal of B (blue), G (green) and R (red), Y
(Yellow), M (magenta), and C (cyan) correspond to the toner amounts, so that the subsequent image data is associated with yellow, magenta, and cyan.

On the other hand, each color component image data from the original image obtained by logarithmic conversion, that is, a yellow component, a magenta component,
The color correction circuit D performs color correction on the cyan component as described below. As shown in FIG. 13, the spectral characteristics of the color separation filter arranged for each pixel in the color reading sensor have an unnecessary transmission area such as a hatched portion, while, for example, a color transferred to a transfer paper. Toner (Y, M, C) is also first
It is well known that it has an unnecessary absorption component as shown in FIG. Therefore, for each color component image data Yi, Mi, Ci, Masking correction for calculating a linear expression of each color and performing color correction is well known. Furthermore, by Yi, Mi, Ci, Min (Yi, M
i, Ci) (the minimum value of Yi, Mi, and Ci) is calculated as a sum (black), and black toner is added later (smearing). Undercolor removal (UCR) operations, which reduce the amount added, are also common. Fig. 12 (a)
2 shows a circuit configuration of a color correction circuit D that performs masking, darkening, and UCR. The feature of this configuration is that it has two masking matrices and can be switched at high speed with 1/0 of one signal line. It is possible to switch at a high speed with "1/0".

First, prior to image reading, desired first matrix coefficients M ₁ and second matrix coefficients M ₂ are set from a bus connected to the CPU 22. In this example Where M ₁ is in registers 87d-95d and M ₂ is in registers 96d-
It is set to 04d.

Reference numerals 111d to 122d, 135d, 131d, and 136d denote selectors, respectively, which select A when the S terminal is "1" and select B when the S terminal is "0". Accordingly the switching signal MAREA364 = "1" when selecting the matrix M _1, when selecting the matrix M ₂ to "0".

Also, 123d is a selector, and the selection signals C ₀ and C ₁ (366
Output based on the truth table of Fig. 12 (b) by d) and 367d)
a, b, c are obtained. The selection signals C ₀ , C ₁ and C ₂ correspond to the color signals to be output, for example, in the order of Y, M, C, Bk (C ₂ , C ₁ ,
C ₀ ) = (0,0,0), (0,0,1), (0,1,0), (1,0,0),
Further, by setting (0, 1, 1) as a monochrome signal, a desired color-corrected color signal is obtained. Now (C ₀ , C ₁ , C ₂ ) =
If (0,0,0) and MAREA = "1", the output (a, b, c) of the selector 123d will have the contents of the registers 87d, 88d, 89d and therefore (a _Y1 , −b _M1 , − C _C1 ) is output. On the other hand, the input signal Y
The black component signal 374d calculated as Min (Yi, Mi, Ci) = k from i, Mi, Ci undergoes a primary conversion at 137d such that Y = ax−b (a, b are constants), and a subtractor 124d, It is input to the B input of 125d and 126d. In each of the subtracters 124d to 126d, Y = Yi
− (Ak−b), M = Mi− (ak−b), and C = Ci− (ak−b) are calculated, and the multipliers 127d and 127d for the masking operation are provided via the signal lines 377d, 378d and 379d. Input to 128d and 129d.

The multipliers 127d, 128d, and 129d have (A)
_Y1 , −b _M1 , −C _C1 ) and B input as described above [Yi− (ak−
b), Mi− (ak−b), Ci− (ak−b)] = [Yi, Mi, Ci]
As shown in the figure, the output D
_{For OUT} , under the condition of C ₂ = 0 (YorMorC), Y _OUT = Yi × (a _Y1 )
+ Mi × (−b _M1 ) + Ci × (−C _C1 ) is obtained, and yellow image data subjected to masking color correction and undercolor removal processing is obtained. Similarly, M _OUT = Yi × (−a _Y2 ) + Mi × (−b _M2 ) + Ci × (−C _C2 ) C _OUT = Yi × (−a _Y3 ) + Mi × (−b _M3 ) + Ci × (−C _C3 ) is output to D _OUT . The color selection is controlled by the CPU 22 according to the order of output to the color printer to be output (C ₀ , C ₁ , C ₂ ) according to the table of FIG. 12 (b). Register 1
05d to 107d and 108d to 110d are registers for forming a monochrome image, based on the same principle as the masking color correction described above.
MONO = k ₁ Yi + l ₁ Mi + m ₁ Ci is obtained by weighting and adding each color.

Also, at the time of Bk output, C ₂ = 1 due to C ₂ (368) inputted as a switching signal of the selector 131d. Therefore, the primary converter 133d receives a primary conversion of Y = cx−d and selects the selector.
Output from 131d. BkMJ110 is a black component signal to be output to the outline of a black character based on the output of a character image area separation circuit I described later. Color switching signals C ₀ ′, C ₁ ′, C ₂ ′
366 to 368 are set from the output port 501 connected to the CPU bus 22, and the MAREA 364 is output from the area signal generation circuit 364. The gate circuit 150d~153d, when the DHi = "1" by later-described binary memory circuit (bit Matsupu memory) L537 non-rectangular area signal DHi122 read from, the signal C ₀ ',
This is a circuit for controlling so that C ₁ ′, C ₂ ′ = “ ₁ , ₁ , 0”, and data for a mono image is automatically output.

<Character Image Area Separation Circuit> Next, the character image area separation circuit I uses the read image data and determines whether the image data is a character, an image, a chromatic color, or an achromatic color. Circuit. The flow of the processing will be described with reference to FIG.

Red (R) 103, green (G) 104, blue (B) 105 input to the character image area separating circuit I from the color conversion B
Is input to the minimum value detection circuit M _IN (R, G, B) 101I and the maximum value detection circuit Max (R, G, B) 102I. In each block, a maximum value and a minimum value are selected from three types of input luminance signals of R, G, and B. The subtraction circuit 104I calculates the difference between the selected signals. The difference is large,
That is, when the input R, G, and B are not uniform, it indicates that the signal is not a near-achromatic signal indicating black and white but a chromatic color depending on some color. Naturally, if this value is small, R, G, B
Are almost the same level, and it is understood that the signal is an achromatic signal which is not a signal depending on some color. This difference signal is output to the delay circuit Q as a gray signal GR125. Also, this difference is compared with the threshold value arbitrarily set in the register 111I by the CPU 20 and the comparator 11
A comparison is made at 2I, and the comparison result is output to the delay circuit Q as a gray determination signal GRBi126. These GR125 and GRBi126 signals are input to a character image correction circuit E, which will be described later, after being matched in phase with other signals by the delay circuit Q, and used as processing determination signals.

On the other hand, the minimum value signal obtained by M _IN (R, G, B) 101I is
It is also input to the edge enhancement circuit 103I. Edge enhancement circuit 10
In 3I, edge enhancement is performed by performing the following calculation using the preceding and following pixel data in the main scanning direction.

D _OUT : Image data after edge enhancement Di: i-th pixel data Edge enhancement is not necessarily limited to the above method, and other known techniques may be used. That is, a line memory for delaying two or five lines in the sub-scanning direction is provided, and a normal edge emphasis filter can be applied using data of 3 × 3 or 5 × 5 pixel blocks. In this case, edge enhancement is performed not only in the main scanning direction but also in the sub-scanning direction, and the effect of edge enhancement is increased. By performing such edge enhancement, an excellent effect of improving the accuracy of black character detection described below is obtained.

With respect to the image signal which has been edge-emphasized in the main scanning direction, an average value in a window of 5 × 5 pixels and 3 × 3 pixels is calculated by a 5 × 5 averaging circuit 109I and a 3 × 3 averaging circuit 110I. The line memories 105I to 108I are delay memories in the sub-scanning direction for performing average processing. 5 × 5 averaging circuit
The average value of 5 × 5 total 25 pixels calculated by 109I is next CPUBUS
The offset value independently set in the offset section connected to 22 is added to adders 115I, 120I, and 125I. The 5 × 5 average value added is the limiter 1 (113I) and the limiter 2
(118I) is input to the limiter 3 (123I). Each limiter is connected by the CPU BUS 22, and is configured so that the limiter value can be set independently. When the 5 × 5 average value is larger than the set limiter value, the output is clipped by the limiter value. The output signal from each limiter is input to a comparator 1116I, a comparator 2121I, and a comparator 3126I, respectively. First, comparator 1
In 116I, limiter 1 113I output signal and 3x3 average
Compared with the output from 110I. The output of the compared comparator 1116I is input to the delay circuit 117I so that the output signal of the comparator 1116I matches the phase of the output signal from the halftone area determination circuit 122I described later. The binarized signal is 5 × 5 and 3 × 5 in order to prevent collapse and skip due to MTF at a predetermined density or higher.
A 3 × 3 low-pass filter is used to cut the high frequency components of the halftone dot image so that the halftone dot of the halftone dot image is not detected at the time of binarization. Through.

Next, the output signal of the comparator 2 (121I) is determined so that the dot area determination circuit 122I at the subsequent stage can determine the halftone area.
In order to detect the high frequency component of the image,
Value conversion has been performed. Since the halftone dot image is composed of a group of dots, the halftone dot region discriminating circuit 122I confirms that the dot is a dot from the edge direction, and detects the dot by counting the number of dots around the dot. Specifically, it is determined as follows.

(Dot decision)

The halftone dot discrimination circuit 122I will be described with reference to FIG. The signal 101J binarized by the comparator 2 (121I) of the character image area separation circuit (FIG. 15 (a)) is subjected to one-line delay (fifo memory) 102J, 103J shown in FIG. 15 (b). Each line is delayed by one line, and the binarized signal 101J and the value delayed by the fifo memories 102J and 103J enter the edge detection circuit 104J. Edge detection circuit 10
In 4J, the edge direction is detected independently for the target pixel in a total of four directions, that is, up and down, left and right, and two slanting directions. After the edge direction is quantized to 4 bits by the edge detection circuit, the dot detection circuit 109J and one-line delay (fi
fo memory) Enter 105J. 1 line delay (fifo memory) 10
4bit delayed by 1 line each for 5J, 106J, 107J, 108J
Enters the dot detection circuit 109J. In the dot detection circuit 109J, by observing a peripheral edge signal,
It is determined whether or not the target pixel is a dot.
For example, as shown by the hatched portion of the dot detection circuit 109J in FIG. To The edge in the direction (there is a density gradient in the direction of the pixel of interest) is at least one pixel, and a total of 7 pixels in the second 2 lines including the pixel of interest To There is at least one pixel in the edge in the direction (there is a density gradient in the direction of the pixel of interest), and If there is an edge in the direction, it is determined as a dot.

In the case of, the dot is naturally determined in the same manner. Next, after the dot determination result is similarly delayed by the one-line delays 110J and 111J, the fattening is performed by the fattening circuit 112J. For fattening circuit 112J, 3 line
When at least one pixel is determined to be a dot in a total of 12 pixels of × 4 pixels, the pixel of interest is determined to be a dot determination regardless of the determination result of the pixel of interest. The fat dot determination result is delayed by one line each by one line delay 113J and 114J. Output from fattening circuit 112J and 1
The signal delayed by two lines in total by the line delays 113J and 114J is input to the majority circuit 115J. The majority decision circuit 115J samples one pixel every four pixels with respect to the lines before and after the line where the pixel of interest exists. This is sampled from the pixel of interest by a width of 60 pixels on the left and right, that is, 30 pixels each on the left and right in 2 lines of 15 pixels, and the number of pixels determined to be dots is calculated. If this value is larger than a preset value, it is determined that the target pixel is a halftone dot.

Here, in the copying apparatus of the present embodiment, the moving speed of the image reading unit in the reader unit is changed according to the magnification in the sub-scanning direction (paper feed direction) as a scaling method. In this case, in order to perform accurate halftone dot determination, the one-line delays 102J, 103J, 105
J, 106J, 107J, 108J, 110J, 111J, 113J, 114J fifo
Memory control is an operation in which one line is written out of two lines and one line is not written.

In this way, by controlling the writing in the fifo memory, it is possible to determine the halftone dot with the same size image even at the time of zooming. As a result, the accuracy of the determination at the time of zooming is improved.
Note that the types of filters for edge detection described above,
The size of the matrix of the dot detection circuit, the method of increasing the width of the dot, and the method of using the majority circuit are not limited to those described above. Deformation is possible.

Next, the sampling at the time of the enlargement will be described with reference to FIG. Shows the original image. Normally, when reading an image at the same magnification, the original image is read within a dotted line shown in the figure. This image is the fifo mentioned earlier
Writing is continuously performed on the memory line by line.
That is, as shown in the figure, all data is written without omitting the writing to the fifo memory. Next, at the time of enlargement, here, for the sake of simplicity, the case of 200% enlargement will be described. As described above, the moving speed of the reading unit is reduced during enlargement. Therefore, at the time of 200% enlargement, the moving speed is halved, and the width of one line shown in FIG.
Read as a line image. The figure shows the read image to correspond to the original.

As shown in the figure, the image data read is written to the above-mentioned fifo memory as in the case of the same magnification. At this time, writing to the fifo memory is performed while thinning out every line, and the state is shown in the figure.

In the present embodiment, the case of 200% enlargement has been described, so that writing is performed once for two lines. However, this writing method can be changed according to the magnification of the magnification.

The OR gate 1 is obtained by using the result determined by the halftone dot area determination circuit 122I and the signal from the delay circuit 117 in this manner.
The logical sum is taken at 29I. And the misjudgment removal circuit 130I
After the erroneous determination is removed by the above, the signal is output to the AND gate 132I. The OR gate 129I outputs a determination signal determined to be a halftone area or a halftone area. In the erroneous determination elimination circuit 130I, for a binarized signal, first, the image area is narrowed to take advantage of the characteristic that images such as characters are thin and images such as photographs have a large area. Remove. Specifically, when at least one pixel other than an image such as a photograph exists in an area of 1 mm around the center pixel xij, the center pixel is determined to be an outer region of the image. That is, the AND of the binary signals in the area is taken, and the center pixel xij = 1 only when all are 1 (in the case of the image area)
And After removing the image area of the isolated point in this way, a thickening process is performed to restore the thin image area. That is, when there is an image area such as a photograph of at least one pixel in an area of a peripheral 2 mm square, the central pixel xij is determined to be an image area. In this thickening process, the binary signal after the thinning process is ORed in an area, and when at least one pixel is 1 (in the case of an image area), the center image xij = 1.

Then, the erroneous determination removal circuit 130I outputs an inverted signal of the binary signal after the fattening process. This inverted signal is the halftone and halftone mask signal.

Similarly, the output of the halftone discrimination circuit 122I is directly
The data is input to 131I to perform a thinning process and a fattening process.

Here, the mask size of the thickening process is the same as the mask size of the thickening process, or by making the thickening process larger, the determination result when the thickening process crosses. I have. Specifically, the erroneous determination removal circuit 130
Both I and 131I are thinned by a 17 × 17 pixel mask, further thinned by a 5 × 5 mask, and then thickened by a 34 × 34 pixel mask. The output signal SCRN signal 27 from the erroneous determination elimination circuit 131I is connected to a character image correction circuit E described later.
Is a determination signal for performing smoothing processing only in the halftone dot determination unit and preventing moire of the read image.

Next, the contour of the input image signal is extracted from the output signal from the comparator 3 126I in order to process the character in a later stage in a sharp manner. As an extraction method, the binarized output of the comparator 3 126I is subjected to a thinning process using a 5 × 5 block, and a thickening process is performed to outline the difference area between the thickened signal and the thinned signal. And The contour signal extracted by such a method passes through the delay circuit 128I so as to match the phase with the mask signal output from the erroneous determination removal circuit 130I, and then the contour signal is determined as an image by the mask signal by the AND gate 132I. The contour signal at the portion is masked, and only the contour signal at the original character portion is output. The output from the AND gate 132I is then output to the contour regeneration unit 133I.

The reason why the average value in the 5 × 5 and 3 × 3 windows is taken as described above is to detect the halftone, but the matrix size and the way to take the window are not limited to the above cases. What is necessary is just to take the average value of the two types of regions including the target pixel.

Similarly, the matrix size of the thinning process and the fattening process of the erroneous determination removing circuits 130I and 131I can be arbitrarily set.

As described above, according to the contour signal extraction algorithm of the present embodiment, not only the Waku signal is extracted but also the halftone and the mask signal based on the tint signal are ANDed. Regions can be separated with high accuracy.

In addition, since an appropriate offset can be set by the CPU 20 in accordance with each of the 5 × 5 pixel block average values used for the detection of each of the halftone area, the halftone dot area, and the character area, the detection of each area can be performed accurately. Become like

Further, according to the present embodiment, the output of the halftone dot discriminating circuit and the binary signal indicating the halftone or halftone area are subjected to thinning processing and fattening processing to remove erroneous determination. An erroneous determination portion can be removed from a signal, and accurate image area separation can be performed.

In addition, the signal used in the character image area separation is Min
Since the (R, G, B) signal is used, the three-color information of R, G, B can be used more effectively than, for example, the case of using the luminance signal Y. In particular, character / image separation in a yellowish image Can be performed with high accuracy.

In addition, since the character / image area is separated after performing edge enhancement on the Min (R, G, B) signal, it becomes easy to detect a character portion and to prevent erroneous determination.

<Contour Regenerating Unit> The contour regenerating unit 133I performs a process of setting a pixel not determined as a character contour to a character contour based on information on surrounding pixels. As a result, the MjAr124 is used as a character image correcting circuit E To perform the processing described below.

Specifically, as shown in FIG. 16, bold characters (FIG. 16A)
As for the character, the dotted line portion in FIG. 6B is determined as a character as a character determination unit, and the processing described later is performed. For the thin character (FIG. 3C), the character portion is changed to the dotted line portion in FIG. , And a gap such as an oblique line is generated in the character portion, so that if the processing described later is performed, it may be difficult to see due to an erroneous determination. In order to prevent this, a contour regenerating process is performed for a portion that is not determined to be a character based on surrounding information as a character portion. Specifically, by changing the hatched portion to a character portion, the character portion becomes as shown by a dotted line portion in FIG.
The erroneous determination can be reduced even for a character having a color that is difficult to detect or a thin character, which leads to an improvement in image quality.

17 (a) to 17 (h) are diagrams showing how to use surrounding information to regenerate a target pixel in a character portion.
(A) ~ (d) are noted regardless of the information of the target pixel when the vertical and horizontal, and diagonal both character portion around the pixel of interest in 3 × 3 pixels block (S _1, S ₂ are "1") The pixel is a character part. On the other hand, (e) to (h) are 5 × 5 pixel blocks, each of which is one pixel centering on the target pixel, and both the vertical, horizontal, and oblique character portions (both S ₁ and S ₂ are “1”). Regardless, the pixel of interest is a character portion. In this way, by having the two-stage (plural types of blocks) structure, it is possible to cope with a wide range of errors. The size and number of the pixel blocks and the type of the filter can be variously modified, for example, to 7 × 7 pixel blocks.

FIG. 18 and FIG. 19 are circuits for realizing the processing of FIGS. 17 (a) to 17 (h). 18 and 19 are line memories 164i to 167i for obtaining information around the pixel of interest.
DF / Fs 104i to 126i, and AND gates 146i to 153i and an OR gate 154i for realizing FIGS. 17 (a) to 17 (h).

Fig. 17 (a) to 4 line memories and 23 DF / Fs
The information of S ₁ and S _{2 in} (h) is extracted. 146i-153
Registers 155i to 162i, where i corresponds to each of the processes (a) to (h), can independently control enable and disable. The register signal is
It is controlled by the CPU 20.

The correspondence between the AND circuits 146i to 153i and FIGS. 17 (a) to (h) is as follows.

FIG. 20 shows ▲ ▼ of the line memories 164i to 167i (EN
These are timing charts for 1) and ▲ ▼ (EN2). This is done so that EN1 and EN2 are at the same timing at the time of equal magnification, or at the time of enlargement (for example, 200% to 300%), ▲ is thinned once in two lines. Here, the amount of thinning can be arbitrarily determined. Thus, FIGS. 17 (a) to 17 (h)
The size of is expanded. This is because when the information is input at the time of enlargement, the information comes in an image enlarged only in the sub-scanning direction. Is going.

FIG. 17 (i) to FIG. 17 (n) illustrate this in detail. FIG. 17 (i) is a diagram showing the shape of a filter for regenerating the contour of a 3 × 3 pixel block at the same magnification, where A = B
When = 1orC = D = 1orE = F = 1, the target pixel is forcibly set to 1, that is, a character outline.

On the other hand, FIG. 10J shows the shape of a filter for regenerating a contour of 200%, which corresponds to a 3 × 3 pixel block at the same magnification.
The method of generating this block is as described above. A ~
F corresponds to A 'to F', respectively. That is, by taking A 'to F' every other line in the sub-scanning direction, the character image area can be separated under the same conditions at the time of the magnification change as at the time of the equal magnification.

FIGS. 17 (h) to 17 (n) show that this is actually applied, and FIG. 17 (m) is an input to the contour regenerating unit when the magnification is 1: 1 and (n) is 200%. . When FIG. 17 (i) is used for FIG. 17 (m), E = F = 1 becomes 1 and a contour as shown in FIG. 17 (k) is obtained. On the other hand, FIG.
17 (j), since E '= F' = 1, ',' becomes 1, and a contour as shown in Fig. 17 (l) is obtained.
By forming a block for contour regeneration using the thinned data at the time of enlargement and performing regeneration processing, it is possible to perform contour regeneration with the same detection power even at 200% enlargement as at the same magnification.

In this example, 200% enlargement has been described, but the same processing can be performed when the magnification is changed.

<Character image correction circuit> The character image correction circuit E is the character image area separation circuit I described above.
The following processing is performed on each of black characters, color characters, halftone images, and halftone images based on the determination signal generated in step (1).

[Processing 1] Processing related to black characters [1-1] Signal Bk obtained as a video by Sumi extraction
[1-2] The Y, M, and C data are subtracted according to the multi-valued achromatic signal GR125 or the set value. On the other hand, the Bk data is added in accordance with the multi-valued achromatic signal GR125 or the set value. [1-3] Edge enhancement is performed. [1-4] Black characters are printed out at high resolution 400 lines (400 dpi). 1-5] Perform a color residue removal process described below [Process 2] Process related to color characters [2-1] Perform edge enhancement [2-2] Note that color characters are printed out at a high resolution of 400 lines (400 dpi). [Process 3] Process related to halftone image [3-1] Perform smoothing (two pixels in the main scanning direction in this embodiment) to prevent moiré [Process 4] Process related to halftone image [4-1] Smoothing (main (2 pixels each in the scanning direction)
Alternatively, it is possible to select through.

 Next, a circuit for performing the above processing will be described.

 FIG. 21 is a block diagram of the character image correction unit E.

The circuit of FIG.
6e 'for generating a signal for controlling the selector, a block 16e for performing a color residual removal process described later, and an AND for generating an enable signal for the process.
Gate 16e ', multiplier 9e' for multiplying GR signal 125 and set value 10e of I / O port, select multiplication result 10e or set value 7e of I / O port according to output 12e of I / O port 3 Selector
11e, a multiplier 15e for multiplying the output 13e of the selector 6e and the output 14e of the 11e, an XOR gate 20e for taking an exclusive OR of the multiplication result 18e and the output 9e of the I / O port 4, an AND gate 22e, an adder / subtractor twenty four
e, line memories 26e and 28e for delaying one line data, edge emphasizing block 30e, smoothing block 31e, selector 33 for selecting through data or smoothing data.
e, a delay circuit 32e for synchronizing the control signal SCRN127 of the selector, a selector 42e for selecting a result of edge enhancement or a result of smoothing, and a control signal Mi of the selector.
A high-resolution 400 lines (dpi) for the delay circuit 36e for synchronizing the Ar124, the OR gate 39e for taking the logical sum of the output 37e of the delay circuit 36e and the output of the I / O port 8, the AND gate 41e, and the character determination unit ) An inverter circuit 44e for outputting a signal (“L” output), an AND circuit 46e, an OR circuit 48e, and a delay circuit 43 for synchronizing the video output 113 with the LCHG 49e.
Consists of e. The character image correction unit E is an I / O port 1e
Is connected to the CPU bus 22 via the.

Hereinafter, [1] color residual removal processing for removing a color signal remaining around the edge of the black character portion and subtraction at a certain ratio from the Y, M, and C data of the black character portion determination portion, and a certain ratio from the Bk data , [2] Edge enhancement for character part, smoothing for halftone determination part, other gradation image to select through data, [3] LCHG for character part
The signal will be divided into three parts of making the signal "L" (printing at a high resolution of 400 dpi).

[1] Color Remaining Removal Processing and Addition / Subtraction Processing Here, both the signal GRBi126 indicating an achromatic color and the signal MjAR124 indicating a character portion are active.
In other words, the processing is for the edge portion of the black character and its peripheral portion, in which the Y, M, and C components protruding from the edge portion of the black character are removed, and the edge portion is smeared.

 Next, a specific operation will be described.

This process is performed only when the character portion is determined (MjAR124 = "1"), the character is a black character (GRBi126 = "1"), and the print mode is the color mode (DHi122 = "0").
Therefore, it is not performed in the ND (black and white) mode (DHi = “1”) or in the color character (GRBi = “0”).

When the original is scanned for any of the recording colors Y, M, and C, the video input 111 is selected by the selector 6e of FIG. 21 (I / O-6).
This is set to "0" in (5e). In 15e, 20e, 22e, and 17e, data to be subtracted from the video data 8e is generated.

For example, if "0" is set in the I / O-3 12e, the multiplier 15e multiplies the output data 13e of the selector 6e by the value set in the I / O-17e and selected by the selector 11e. Done. Here, data 18e that is 0 to 1 times that of 13e is generated. By setting 1 to registers 9e and 25e, 18e
Is generated by 17e, 20e, and 22e.
Finally, since the addition 23e of 8e and 23e is a two's complement number in the adder / subtractor 24e, the subtraction of 17e-8e is actually performed and the result is output from 25'e.

When "1" is set in I / O-3 12e, the selector 11
e selects B data.

At this time, the multi-valued achromatic signal GR125 generated by the character image area separating circuit I (a signal which takes a large value if it is close to achromatic) is multiplied by 9e by the value set by I / O-210e. Is used as a multiplier of 13e. When this mode is used, coefficients can be independently multiplied for each of the colors Y, M, and C, and the subtraction amount can be changed according to the achromaticity.

At the time of recording color Bk scanning, BkMj112 is selected by selector 6e ("1" is set in I / O-65e). 15e, 20e, 22e, 1
In 7e, data to be added to the video 17e is generated. the above
The difference from Y, M and C is that “0” is set in I / O−4, 9e, whereby 23e = 8e, Ci = 0, and 17e + 8e is output from 25e. The way of generating the coefficient 14e is the same as in the case of Y, M, C. In the mode in which "1" is set to I / O-312e, the coefficient changes according to the achromaticity. Specifically, the addition amount is large when the achromaticity is large, and small when the achromaticity is small.

FIG. 22 shows this processing in which the shaded portions of the black characters N shown in FIG. 22 are enlarged (a) and (c). Where the character signal portion is "1" for any of Y, M, and C video data, subtraction from the video is performed ((b) in the figure), and the character signal portion for Bk video data Is "1", the addition is performed on the video data ((d) in the figure). This figure shows an example in which 13e = 18e, that is, the Y, M, C data of the character portion is 0, and the Bk data is twice the video data.

By this processing, the outline portion of the black character is almost entirely black, but the Y, M, and C data outside the outline signal are marked around the character with the * mark shown in FIG. It is unsightly because it remains.

What removes the remaining color is a color removal removal process. This processing is performed when the video data 13e is in the range where the character area is expanded and the video data 13e is smaller than the comparison value set by the CPU 20, that is, a pixel having a possibility of color remaining outside the character area. Is a process for taking the minimum value of 3 or 5 pixels before and after.

 Next, the explanation will be supplemented by using a circuit.

FIG. 23 shows a character area enlarging circuit which functions to expand a character area, and includes DF / Fs 65e to 68e and AND gates 69e and 71.
e, 73e, 75e and an OR gate 77e.

Mj when all "1" are set to I / O ports 70e, 72e, 74e, 76e
Signals obtained by expanding two pixels before and after in the main scanning direction with respect to the signal in which Ar124 is “1” are I / O ports 70e, 75e “0”, 71e, 73e “1”.
In the case of, the signal expanded by one pixel before and after in the main scanning direction is Sig218e
Output from This switching signal is the AND gate shown in FIG.
16'e.

 Next, the remaining color removal processing circuit 16e will be described.

 FIG. 24 is a circuit diagram of the residual color removal processing.

In FIG. 24, 57e is a 3 pixel for selecting a minimum value of a total of 3 pixels of the pixel of interest and 1 pixel before and after the pixel of interest for the input signal 13e.
The min select circuit 58e selects a maximum value of a total of five pixels, that is, a target pixel and two pixels before and after the target pixel, for the input signal 13e. 5 pixel min select circuit, 55e is input signal 13e and I / O-18 (54
When 54e is larger than the comparator e), 1 is output. 61e and 62e are selectors, 53e and 53'e
Is an OR gate and 63e is a NAND gate.

In the above configuration, the selector 60e receives the I / O signal from the CPU bus 22.
Based on the value of O-19, select between 3 pixel min and 5 pixel min. The effect of removing the residual color is greater for 5 pixels min. This can be selected by manual setting of the operator or automatic setting of the CPU. It should be noted that the number of pixels to be min can be arbitrarily set.

When the output of the NAND gate 63e is "0", that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and the selector 62e is in the range where the signal of the character portion is expanded, and 17'e is 1 In this case, the A side is selected; otherwise, the B side is selected. (However, at this time, the registers 52e and 64e are "1" and the register 52'e is "0".) When the B side is selected, the through data is output as 8e.

The EXCON 50e can be used instead of the comparator 55e when, for example, a binary signal of the luminance signal is input.

By performing the above-described color residual removal processing, it is possible to remove dust in colors around characters and obtain a clearer image.

FIG. 25 shows the place where the above two processes have been performed. FIG. 25 (a) shows a black character N, and FIG. 25 (b) shows an area determined as a character in the Y, M, C data which is the shaded density data, that is, a character determination section (* 2, * 3, * 6, * 7)
Is set to 0 by subtraction processing, and * 1 and * 4 are set to * 1 ← * 0, * 4 ← * 5 by residual color removal processing.
Figure 25 (c) is required.

On the other hand, for B and data as shown in FIG.
Only the addition processing is performed on the character determination units (* 8, * 9, * 10, * 11), and the output is completed with black rims as shown in FIG.

Note that no change is made to the color characters as shown in FIG. 25 (f).

[2] Edge Enhancement or Smoothing Process Here, edge enhancement is performed for the character determination unit, smoothing is performed for the halftone dot portion, and a through output is performed for the others.

Character part → 3 of 25e, 27e, 29e since MjAR124 is “1”
The output of the 3 × 3 edge emphasis 30e generated from the line signal is selected by the selector 42e, and output from the 43e. Here, the edge enhancement is obtained from a matrix and a calculation formula as shown in FIG.

Halftone part → 27 because SCRN35e is “1” and MjAR21e is “0”
The result of the smoothing 31e applied to e is output by the selectors 33e and 42e. Here, smoothing as shown in Fig. 27, when the target pixel is a _{V N (V N + V N} + 1)
/ 2 process to V _N of data, that is, smoothing of the main scanning two pixels. This prevents moire that may occur in the halftone dots.

Other → Other part is a part other than a character part (character outline) or a halftone part, specifically, a process for a halftone part. At this time, since both the MjAR 124 and the SCRN 35e are "0", the data of 27e is output from the video output 43e as it is.

If the character is a colored character, the character
No processing is performed.

In the embodiment, the example in which the residual color is removed only in the main scanning direction is described. However, the residual color removal processing may be performed in both the main scanning and the sub-scanning.

Note that the type of edge-enhanced filter is not limited to the above-described case.

Also, smoothing may be performed over both the main scanning and the sub-scanning.

[3] Character part high-resolution 400-line (dpi) output processing The LCHG 140 is output from 48e in synchronization with the video output 113. Specifically, the inverted signal of MjAR124 is output in synchronization with 43e. LCHG (200/400 switching signal) = 0 for text part
Other parts have LCHG = "1".

As a result, the character portion judging section, specifically, the outline portion of the character is struck by a laser beam printer at a high resolution of 400 lines (dpi), and the others at a high gradation of 200 lines.

Here, FIG. 25 (g) shows a soft key screen of the liquid crystal touch panel 1109 in the operation unit 1000 for changing the conditions of the character image separation processing of this embodiment. In this embodiment, five types of conditions can be selected by soft keys. Soft key positions are configured from left to right: -2, -1, standard, and strong. Each of these will be described below.

〔weak〕

The weak position is used to avoid an erroneous determination that always occurs when copying an indistinguishable original such as a line drawing, and the limiter value of 123I in FIG. To an appropriate value.

As shown in FIG. 25 (h), in the standard, the limiter level is a bright portion of the original (the limiter value = 15 in this embodiment).
8) The value equal to or larger than the limiter value is clipped to the limiter value as shown in FIG. 25 (i). When the limiter level is "weak", the limiter is set to 0 as shown in FIG. 25 (j), so that all of the limiter levels are clipped to 0 (FIG. 25 (k).
The outputs binarized by the comparator 3 (126I) in FIG. 15A are all 1 (or 0), no outline is extracted, and the above-described black character processing is performed on the read image signal. Absent. In this way, in the [weak] position, processing is not performed in a portion where the image area is separated by preventing the generation of the contour signal.

[-2] [-1] The position of -2, -1 is used to make erroneous determination in a document in which characters and images are mixed inconspicuous. Black characters in the character part separated at the time of standard document copying are such that the outline of the character is monochrome black and that part is formed with high resolution,
Control of the gradation resolution switching signal LCHG is performed. Therefore, in “−2, −1”, the control of the gradation resolution signal is the same as that of the image part, and Y, M, C
Is increased as the number decreases to “−1” and “−2”. As a result, control is performed so that the image difference of the processed image based on the determination result is not recognized.

This will be described with reference to FIGS. 25 (l) to (p). (L) The figure shows read image data, which becomes darker as the value increases and becomes lighter as the value decreases. In the image area separation in the present embodiment,
(L) As shown in the figure, processing is performed for the two pixels of the contour part, and when the soft lever displayed on the touch panel α is [standard] or [strong], the Y, M and C figures are shown in (m). For black characters and lines as shown in
In order to prevent the Y, M, and C toners from being printed, and to make the black lines or characters look sharper in the case of Bk (n), the ratio of the contours is increased as shown in the figure. [-1],
In the mode [-2], as shown in FIG. (O), the ratio of Bk is set so that the toner is slightly applied to the outline for Y, M, and C, and for Bk, as shown in FIG. I have less.

〔standard〕

 The processing described above is performed for “standard”.

〔strength〕

In the case of "strong", a parameter is set such that no erroneous determination is made for the character, and thin characters, pale characters, etc. are also made into a single color black. Specifically, the contour signal limiter 3 (15th
By increasing the value of (I) in FIG. 13 (a), it becomes possible to extract a contour signal in a highlight portion.

As described above, the erroneous determination can be avoided or made inconspicuous by changing the condition of the image area separation and the processing based on the separation according to the image to be read.

Further, since the limiter value can be easily changed by the CPU 20, the circuit configuration is not complicated.

The strength of the black character processing is not limited to the case where the strength is set to five levels. In particular, by setting in multiple stages, it is possible to select a process matching the original image.

<Relation with Mode Selection> Next, processing according to output color mode selection such as a four-color mode, a three-color mode, and a single-color mode will be described.

A digital color copying machine has a function of copying in a color different from the original color, for example, a function of copying a full-color original in mono-color. Generally, in a portion where the image area is separated, a process of changing a color balance is performed in response to a demand for clearer characters. Therefore, when the above processing is performed on the input image after the image area is separated, the output image is significantly deteriorated.

Therefore, in the present embodiment, in order to provide an image processing apparatus that does not cause image degradation due to a difference in output color mode,
The conditions of the image area determination means or the processing means accompanying the determination are changed according to the output color mode.

That is, when the monochrome signal described in the masking section is selected, or when the image is formed only with the Y, M, and C toners,
When the color mode is selected, the input image processing by the main image area separation processing is not performed.

 Specifically, the following processing is performed.

As shown in FIG. 25 (h), in the four-color mode of recording in four colors of Y, M, C, and Bk, the limiter level is set to a bright portion of the document (the limiter value = 158 in this embodiment). is there. The value equal to or larger than the limiter value is clipped to the limiter value as shown in FIG. 25 (i). In the case of a three-color mode in which the limiter level is recorded in three colors of Y, M, and C, by setting the limiter level to 0 as shown in FIG. 25 (j),
All output signals are clipped to zero. Therefore, all outputs binarized by the comparator 3 (126I) in FIG.
(Or 0), no contour is extracted, and no processing is performed on the read image signal. In this manner, in the three-color mode, processing is not performed in a portion where the image area is separated by preventing the generation of the contour signal.

Also, in the case of the single-color mode, the same configuration as in the case of the above-described three-color mode does not perform the process of extracting the character signal.

As described above, in the present embodiment, based on the input image information, the determination means for determining whether the input image information is image information or character information, and the processing means for processing the input information according to the determination result Color copying machine having
It has a color mode other than the normal copy, and in the color mode other than the normal copy, the process according to the determination result is different from the normal. As a result, it is possible to simplify the processing and prevent erroneous determination.

<Relationship with control of lamp light amount> The same processing as that performed by the conventional analog copying machine for land skipping is also required for digital color copying machines. A system for skipping colors has been considered.

However, when the light amount of the light source is changed, the level of the reflected light of the document is also different. Accordingly, in the case of the separation method in which the character and the image are distinguished based on the difference in the brightness of the read image signal or the color, etc., erroneous determination is likely to occur. .

Therefore, in the present embodiment, by changing the character image discrimination condition according to the document reading light amount, erroneous judgment by character image discrimination due to a change in light amount is eliminated.

First, the lamp light amount adjustment will be described. Fig. 25 (q)
Fig. 5 shows a flow of lamp light amount adjustment. When pre-scanning to detect the position size of the original, 50 points in the main scanning direction,
The data of a total of 1500 points of 30 lines are read at equal intervals in the sub-scanning direction, and the number of data of the document is counted (S1).
Next, the maximum value in the data is detected (S2), and the maximum value of 85 is detected.
Count the number of data points within% to 100% (S
3). At this time, the light amount adjustment is performed only when the maximum value is 60H or more (S4), and when 1/4 or more of the points are within 85% to 100% of the maximum value (S5) (S7). As the set light amount, the maximum value becomes FF _H , The value obtained by the above equation is set as a lamp light amount set value (S6).

On the other hand, if the maximum value of the data is less than 60H, or 1
If the point less than / 4 is between 85% and 100% of the maximum value, the lamp light amount adjustment is not performed.

Here, when the light amount adjustment is performed, FIG.
The offset 2 (1190) and the offset 3 (124I) are set to values larger than usual. This is because the dynamic range of the density of the read original is narrowed by increasing the light amount of the lamp, so that the noise component of the original is detected, and erroneous determination in halftone detection and erroneous detection in contour extraction occur. Therefore, in order to prevent erroneous detection due to this noise component, the offset value is set to a large value even when adjusting the light amount.

As described above, in the present embodiment, image reading means for reading an image by optical scanning, light amount adjusting means for changing the light amount of a reading light source corresponding to the density of a document to be read, and whether the read image information is halftone information or character information. In a copying apparatus having a discriminating means for discriminating the information and processing means for processing the input information based on the discrimination result, the discriminating condition is changed in accordance with the light quantity adjustment.

In this embodiment, the lamp light quantity control is performed under a certain condition. However, the lamp light quantity control may be performed in all cases.

The sampling data at the time of prescanning can be increased or decreased. Also, the threshold value for determining whether or not to perform light amount adjustment can be changed.

Further, the condition for determining the character and the image area may be selected from a plurality of stages in accordance with the light amount adjustment.

<Character Image Synthesis Circuit> Next, the character image synthesis circuit F will be described. FIG. 28 (a) shows processing of an image by a binary signal in the present apparatus,
It is a block diagram of a decoration circuit. The color image data 138 input from the image data input unit is input to the V input of the 3to1 selector 45f. The other two inputs A and B of the 3to1 selector 45f are connected to the lower part (A _n ,
A _n is the A of B _n) 555f is, the B B _n is latched by VCLK117 in latch 44f, is input. Therefore, the output Y of the selector 45f includes the select inputs X ₀ , X ₁ , J1,
One of V, A, and B is output based on J2 (114). The data _Xn is the upper 2 bits of the data in the memory in this embodiment, and is a mode signal for determining processing and modification. 139
Are controlled so as to be switched in synchronization with the VCLK 117 under the control of the CPU 20 in FIG. 2, which is a code signal output from the area signal generation circuit, and are input as an address of the memory 43f. That is, for example, (X ₁₀ , A ₁₀ , B ₁₀ ) = (01, A ₁₀ , B ₁₀ ) is written in advance at address 10 of the memory 43f,
As shown in FIG. 29 (B), if "10" is given to the code signal 139 from the point P to the point Q and "0" is given from the point Q to the point R in synchronization with the scanning of the line 1 in the main scanning direction, Data between P and Q
X _n = (0,1) is read out, and at the same time, (A _n , B _n ) contains (A ₁₀ ,
Data that B ₁₀₎ is a latch output. As shown in FIG. 28 (c), the truth table of the 3to1 selector 45f is (X ₁ ,
X ₀₎ = (0,1) is the case of (B), J1 is a if A input it is "1" to Y, therefore, the constant A ₁₀ to Y, if J1 is "0" , V input to Y, and thus to output the input color image data to the output 114 as it is. Thus, for example, a so-called hair-cut character combination of a character portion having a value of (A ₁₀ ) is realized for a color image of an apple as shown in FIG. 29 (b). Similarly, (X ₁ ,
X ₀ ) = (1,0), and when a signal like J1 in FIG. 29 (C) is input to the binary input, the FIFOs 47f-49f and the circuit 46
f (details in FIG. 28 (b)) generates a signal as shown in J2 of FIG. 28, and according to the truth table of FIG. 28 (c), characters are set in the apple image as shown in FIG. 28 (c). (Contour or bag character). Similarly, in FIG. 28 (D), the rectangular area in the apple is output at the density of (B _n ), and the characters inside the apple are output at the density of (A _n ). Figure (A)
Is (X ₁ , X ₀ ) = (0,0), ie, any J1, J
Even for the change of 2, there is a control that does nothing depending on the binary signal.

According to FIG. 28 (b), the expanded signal input to J2 is an extension of 3 × 3 pixels, but it is easy to further increase the size by adding a hardware circuit.

Here, the FHi signal 121 input to the FiFo 47f is the second
A non-rectangular area signal stored in the binary memory L of FIG. 100dpi. By using the FHi signal 121, the above-described various processes can be performed.

Also, C0, C1 (366, 3) output from the I / O port 501 in FIG. 2 in association with the output color (Y, M, C, Bk) to be printed.
67) is input to the lower 2 bits of the address of the memory 43f, and therefore corresponds to “0, 0”, “Y”, “M”, “C”, and “Bk”.
Since it changes to “0,1”, “1,0”, “1,1”, for example, when outputting yellow (Y), addresses 0, 4, 8, 12, 16,..., Magenta (M)
Are 1,5,9,13,17 ... addresses, cyan (C) is 2,6,10,14,18 ...
For the address, black (Bk), addresses 3, 7, 11, 15, 19 ... are selected.
Therefore, in accordance with an operation instruction on the operation panel described later, an address corresponding to the area code signal 139 for determining the area and the corresponding memory address in the area, for example, X1 to X4 = "1,1"
(A1, A2, A3, A4) = (α1, α2, α3, α4), (B1, B2, B3,
B4) = (β1, β2, β3, β4), and when the J1 signal changes as shown in FIG. 29 (D), for example, J1 becomes “Lo”.
Is a color determined by (Y, M, C, Bk) = (α1, α2, α3, α4). When J1 is “Hi”, (Y, M, C, Bk) =
The color is determined by (β1, β2, β3, β4). That is, the output color can be arbitrarily determined based on the contents of the memory. on the other hand,
On an operation panel described later, Y, M, C, and Bk are each adjusted or set by (%) percent. That is, each gradation 8bit
Therefore, the numerical value is from 00 to 255, so the 1% change is a digital value of 2.55. Set value is (Y, M, C, Bk)
= (Y%, m%, c%, k%), the set values (ie, the values written to the memory) are (2.55y,
2.55m, 2.55c, 2.55k). In practice, a rounded integer is written to a predetermined memory. Further, if the adjustment mechanism adjusts in%, △%
It is sufficient to write a value obtained by adding (darkening) or subtracting (lightening) only 2.55 ° with respect to the fluctuation of.

As described above, according to the present embodiment, the output colors of Y, M, C, and Bk can be specified in units of 1% for each color, and the operability of color specification is improved.

In the truth table of Figure No. 28 (c), column i is the character, image gradation, an output table of the resolution switching signal _{LCHG149, X 1, X 0,} J1, J2 by A or B output When output to Y, "0" is output, and when V is output to Y, the input is output as it is. LCHG149 is a signal for switching the print density at the time of output printing, for example. When LCHG = "0", for example, high resolution 400 dpi, and when LCHG = "1", printing is performed at high gradation 200 dpi. Therefore, when A or B is selected, LCHG = 0
That means that the inside area of the synthesized character is 400 dpi,
The area other than the text is printed at 200 dpi, and the text is controlled so as to maintain a high resolution and sharpness, and the halftone portion to maintain a high gradation and output smoothly. As described above, the LCHG 140 is the output of the character / image separation circuit I, M
That is why the output from the character image correction circuit E is based on the JAR.

<Image Processing / Editing Circuit> Next, the image signal 115 and the gradation resolution switching signal LCHG141 that have undergone the color balance adjustment in FIG. 2P are input to the image processing / editing circuit G. A rough schematic diagram of the image editing and processing circuit G is shown in FIG.

Input image signal 115, gradation resolution switching signal LCHG14
1 is first input to the texture processing unit 101g. The texture processing section is roughly divided into a memory section 103g for storing a texture pattern, memories RD and WR for controlling the memory section, an address control section 104g, and an arithmetic circuit 105g for performing a modulation process using a pattern stored for input image data. It is configured. The image data processed by the texture processing unit 101g is next input to the scaling, mosaic, and taper processing unit 102g. The variable magnification, mosaic, and taper processing unit 102g includes a double buffer memory 105
g, 106g and a processing / control unit 107g, and various processes are independently controlled and output by the CPU 20. Here, the texture processing unit 101g and the scaling, mosaic, and taper processing unit 102g perform texture processing on independent areas by using GHi1 (119) and GHi2 (149), which are enable signals for each process sent from the switching circuit N. It is configured to perform mosaic processing.

The tone resolution switching signal LCHG signal 141 input together with the image data 115 is processed in various editing processes while adjusting the phase with the image signal. Hereinafter, the image processing / editing circuit G will be described in detail.

<Texture processing section> The texture processing is a processing of cyclically reading out a pattern written in the memory and modulating the video. For example, an image as shown in FIG. The modulation is performed in such a pattern to generate an output image as shown in FIG.

FIG. 32 is a diagram for explaining the texture processing circuit.
Hereinafter, the writing section of the modulated data 218g to the texture memory 113g and the data from the texture memory 113g
The operation will be described separately for the calculation unit (texture processing) of 216g and image data 215g.

[Data writing unit to the texture memory 113g] At the time of writing data, the color correction circuit D that performs masking, under color removal, and extraction of smear Is output, and data is input from 201g. This data is selected by the selector 202g. On the other hand, the data 220g is selected by the selector 208g, and the data 220g is input to the ▼ of the memory 113g and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC and a horizontal counter 211g that counts up in synchronization with the image clock and VCK. B is selected by the selector 210g, and the address of the memory 113g is selected. input. Thus, the density pattern of the input image is written to the memory 113g. For this pattern, a position on the document is designated by an input device, for example, a digitizer 58, and image data obtained by reading the portion is written to the memory 113g.

[Data writing by CPU]

The CPU data is selected by the selector 202g. On the other hand, A is selected by the selector 208g, and is input to the ▼ of the memory 113g and the enable signal of the driver 203g. A is selected as the memory address by the selector 210g, and is input to the address of the memory 113g. Thus, an arbitrary density pattern is written to the memory.

(Texture memory 113g data 216g and image data 21
5g Operation Unit] This operation is realized by the operation unit 215g. This arithmetic unit is constituted by a multiplier here. Enable signal 12
The operation of the data 216g and 201g is performed only when 8g is active, and when the data is enabled, 201 is in a through state.

Also, 300g and 301g are the XOR and OR gates respectively, and the MJ signal 308
g, that is, when "0" is set in the register 304g "1" 305g, which is a portion for generating an enable signal using a character composite signal, the texturing process is applied to portions other than the portion containing the composite character signal. On the other hand, register 304g “0” 30
When "0" is set to 5g in the register, it is applied only to the part where the text processing is applied and the synthesized character signal is included.

Reference numeral 302g denotes a portion that generates an enable signal using the GHi1 signal 307g, that is, a non-rectangular signal. Register 306g “0”
At this time, texture processing is applied only to the place where the GHi1 signal is enabled. At this time, if enable 128 is kept active, non-rectangular texture processing synchronized with HSNC is performed if enable 128 is kept, and if enable signal GHi1 and enable 128 are made the same, non-rectangular signal is synchronized. This is a texture treatment. If a 31-bit signal is used for GHi1, for example, texture processing can be performed only on a certain color.

The LCHG _IN signal 141g is a gradation resolution switching signal,
Delayed by 215g and output from LCHG _OUT 350g. As described above, in the texture processing section, the gradation resolution switching signal LCHG141 is also subjected to the predetermined delay processing, and corresponds to the image after the texture processing.

<Mosaic, scaling, taper processing unit> Next, the schematic operation of the mosaic, scaling, taper processing unit 102g of the image processing / editing circuit G will be described with reference to FIG.

The image data 126g and the LCHG signal 350g input to the mosaic / magnification / taper processing unit 102g are first input to the mosaic processing unit 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesizing circuit F, the area signal GHi2 (149) from the switching circuit N, and the mosaic clock MCLK from the mosaic processing control unit 402g to determine whether or not mosaic processing is to be performed. After the size in the scanning direction, combination of characters, and the like are performed, the data is input to the 1to2 selector 403g. Area signal GH
i2 is based on the non-rectangular area information stored in the binary memory L of FIG. 2, and this signal enables the mosaic processing on the non-rectangular area. Here, the size of the mosaic process in the main scanning direction is variable by controlling the mosaic clock MCLK. The control of the mosaic clock MCLK will be described later in detail.

The 1to2 selector 403g outputs a line memory select signal LM obtained by dividing HSYNC118 by a D flip-flop 406G.
By SEL, input image signal and LCHG signal are converted to Y1, Y2
Output to either of

Output from Y1 of 1to2 selector 403g is line memory
A404g and A of 2to1 selector 407g. The output from Y2 is line memory B405g and 2
Connected to B of to1 selector 407g. When an image is sent from the selector 403g to the line memory A, the line memory A 404g is in the write mode, and the line memory B 405g is in the read mode. Similarly,
When an image is sent from the selector 403g to the line memory B 405g, the line memory B is in the write mode and the line memory A 404g is in the read mode. As described above, the image data read from the line memories A404g and B405g alternately is output as continuous image data while being switched by the 2to1 selector 407g by the inverted signal of the output LMSEL signal of the D flip-flop 406g.
The output image signal from the 2to1 selector 407g is output after a predetermined enlargement process is performed by the enlargement processing unit 414g.

Next, write / read control of these memories will be described. First, when writing and reading, the line memory
A404g and an address given to the line memory B405g are configured by up / down counters 409g and 410g to increment and decrement in synchronization with HSYNC which is a reference of one scan and in synchronization with the image CLK. The counter enable signal output from the line memory address control unit 413g, the control signal WENB for controlling the write address generated from the scaling control unit 415g, and the control signal RENB for controlling the read address generate an address counter ( 409g, 410g) are operation-controlled. Each of these controlled address signals is a 2to1 selector 40
Input to 7g and 408g. When the line memory A404g is in the read mode, the 2to1 selectors 407g and 408g use the line memory select signal LMSEL to set the read address to the line memory A404g and the write address to the line memory B40.
Give 5g. When the line memory A404g is in the write mode, the reverse operation is performed. Next, line memory
A, the memory write pulses WEA and WEB to the line memory B are output from the scaling controller 415g. Memory write pulse
WEA and WEB are controlled when the input image is reduced and when the mosaic processing is performed by the mosaic length control signal MOZWE in the sub-scanning direction output from the mosaic processing control unit 402g. Next, a detailed description of these operations will be described below.

<Mosaic processing> The mosaic processing is basically realized by repeatedly outputting one image data. This mosaic processing operation will be described with reference to FIG.

First, the mosaic processing control unit 402g independently performs main scanning and sub-scan mosaic processing control. First, variables corresponding to the desired mosaic size are stored in the latches 501g (for main scanning) and 502g (for sub-scanning) connected to the CPUBUS.
CPU set. First, for the mosaic processing in the main scanning direction, the same data is continuously written to a plurality of addresses of the line memory. For the mosaic processing in the sub-scanning direction, writing to the line memory is performed within a mosaic processing area by a predetermined line. This is done by thinning out each time.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic width control counter 504g, and is configured to load a set value by the HSYNC signal and the ripple carry of the counter 504g. Latch 501g per HSYNC
The counter 504g loads the value set in (1), counts a predetermined value, and outputs the ripple carry to the NOR gate 502g and the AND gate 509g. The mosaic clock MCLK from the AND gate 509g is a signal wrapped around the image clock CLK by the ripple carry from the counter 504g.
MCLK is output only when the ripple carry is output. AN
The MCLK output from the D gate 509g is then sent to the mosaic processing unit 4
Entered in 01g.

The mosaic processing unit 401g includes two D flip-flops 51.
0g, flip-flop 510g is output irrespective of the Mj signal. When the GHi2 signal 149 is 1 and the Mj signal is 0, the flip-flop 511g controlled by the mosaic clock MCLK.
Is output. When the Mj signal is 1, the output outputs the signal from the flip-flop 510g. With this control, it is possible to output a part of the image in the mosaic processing image in the main scanning direction without performing the mosaic processing. That is, for a character synthesized in an image by the character synthesis circuit F at the preceding stage as shown in FIG. 2, mosaic processing of only the image can be performed without performing mosaic processing. The output from the selector 512g is input to the 2to1 selector 403g shown in FIG. 33 described above. As described above, the mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) The sub-scanning direction is controlled by a latch 502g connected to the CPU BUS, a counter 505g, and a NOR gate 503g, similarly to the main scanning. The sub-scan mosaic width control counter is ITOP
It comprises signals 144 and 511g, a selector 512g, an AND gate 514g, and an inverter 513g. Flip flop 510
g and 511g include the gradation resolution switching signal LCHG in addition to the image signal.
The flip-flop 510g is the image clock CLK, the flip-flop 511g is the image data input by the mosaic processing clock MCLK, and the LCHG
Hold the signal. In other words, the gradation resolution switching signal LCHG corresponding to one pixel is held in the flip-flops 510g and 511g in the same phase during the respective cycles of CLK and MCLK. Each held image signal and LCHG signal are input to a 2to1 selector 512g. The output is switched according to the mosaic area signal GHi2 and the binary character signal Mj signal.

The selector 512g performs the operation shown in the truth table in the left diagram by the AND gate 514g and the inverter 513g. That is, when the mosaic area signal GHi2 signal 149 is 0, the pulse is synchronized, and the ripple carry pulse is generated by counting the HSYNC 118. Ripple carry pulse is OR
Inverted signal of mosaic area signal GHi2149 to gate 508g ▲
▼ and the character signal Mj are input.

The sub-scan mosaic control signal MOZWE is controlled as shown in the truth table in the left diagram. The MOZWE signal output in such a combination is input to the scaling controller 415g and
An AND gate 515g controls a write pulse generated by a line memory write pulse generation circuit (not shown). The line memory write pulse generation circuit is a circuit that can vary the output clock rate such as a rate multiplier generally used for scaling control. This embodiment is different from the gist of the invention, and therefore, detailed description is omitted. As for the WR pulse controlled by the MOZWE signal, a WR pulse is output alternately to WEA and WEB from the 1to2 selector by a switching signal LMSEL signal in which a switching pulse changes every HSYNC 118. With the above control, even when the mosaic area signal GHi2 signal 149 is “1”, when the Mj signal becomes “1”, writing to the memory is performed, so that a part of the mosaic processing image in the sub-scanning direction is It is possible to output without mosaic processing.
FIG. 35 (a) is a diagram showing a distribution of density values for each pixel for a certain recording color when mosaic processing is actually performed. In the mosaic processing of FIG. 35, each pixel in a 3 × 3 pixel block is set as a representative pixel value. In this processing, the mosaic processing is not performed on the character A, that is, the pixel in the hatched portion based on the character signal Mj. That is, when the combined character and the mosaic processing area overlap, the character can be given priority.
Therefore, even when the mosaic processing is performed, an image can be formed so that only characters can be read. The mosaic area is not limited to a rectangle, and a mosaic process can be performed on a non-rectangular area.

(Italic and Taper Processing) Next, the italic processing will be described with reference to FIGS. 33 and 36. FIG.

The inside of the line memory address control unit 413g shown in FIG.
This is shown in FIG. This line memory address controller 413g
Controls the enable signal of the write / read counters 409g and 410g, and controls the address counter to determine which part in one main scanning line is to be written to or read from the line memory, thereby controlling movement, italics, etc. It is possible. First, the enable control signal generation circuit will be described with reference to FIG.

The counter 701g has a counter output of 0 at HSYNC, and then counts the image clock 117, which is the clock of the counter 701g. The output Q of the counter 701g is input to iso-surface comparators 706g, 708g, 709g, and 710g. The A input side of each comparator other than the comparator 709g is connected to an independent latch (not shown) connected to the CPU BUS22. When an arbitrary set value matches the output of the counter 701g, a pulse is output. You.
The output of the equal plane comparator 706g is LK flip-flop
The JK of the 708g and the comparator 707g are connected to the K input, and the JK flip-flop 708g is configured to output 1 until the comparator 707g outputs a pulse after the comparator 706g outputs a pulse. I have. This output is used as a write address counter control signal, and the write address counter is in an operation state only in a period where it is 1, and an address is generated for the line memory. Similarly, the read address counter control signal is used to control the read address counter. Here, the selector 703g is connected to the input signal to A of the comparator 709g in order to make the input value to the comparator different between when the italic processing is performed and when it is not performed. Here, when the italic processing is not performed, a CP (not shown) is used.
The value set in the latch connected to the UBUS 22 is input to the A input of the selector 703g, and the A input is similarly selected by a select signal output from a latch (not shown).
Output from 703g. Subsequent operations are performed by the comparator
This is the same operation as 706g and 707g. Next, when performing italics,
The value input to A of the selector 703g is also input to the selector 702g as a preset value. Selector
When the 702g and 703g select signals select the B input,
The output of the selector 702g is an adder 704g, which also performs addition with a value set on a latch (not shown).
Here, this value indicates the amount of change for each line due to the oblique angle, and can be obtained by tan θ when the desired angle is θ. The addition result is 708 g of flip flop with HSYNC118 clock.
And the value is held during one main scan. The output of the flip-flop 705g is connected to the B input of the selector 702g and the B input of the selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, thereby starting the read address counter.
It can be changed at a fixed rate from HSYNC. This allows reading from the line memories A404g and B405g to be
Since the data is read out of the YNC, italic processing can be performed. In addition, the above-mentioned change amount may be either positive or negative. In the case of a positive value, the reading shifts in a direction away from HSYNC, and in the case of a negative value, the reading shifts in a direction approaching HSYNC. Further, by changing the select signals of the selectors 702g and 703g in synchronization with HSYNC, it is possible to make it partly italic.

The enlargement processing method generally includes methods such as 0th-order, 1st-order, and SINC interpolation. However, since it is different from the gist of the present invention, the description is omitted. While performing italic processing, the taper processing is enabled by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line.

In addition, as in the case of the mosaic processing and the texture processing, the above processing can also be performed on the non-rectangular area according to the non-rectangular area signal GHi.

Further, in these processes, the input gradation resolution switching signal is processed while adjusting the phase with the image signal.
That is, the switching signal LCHG142 is subjected to the same processing according to the processing of the image signal in each processing such as scaling, italic, and taper. Then, the output image data 114 and the output gradation resolution switching signal LCHG142 are output to the edge enhancement circuit.

The conceptual diagram of the italic processing and taper processing explained above
These are shown in FIGS.

<Outline Processing Unit> FIGS. 35 (d) and 35 (f) are diagrams for explaining the outline processing. In the present embodiment, as shown in FIG. 35 (d), signals inside characters and images (broken line inside (I), (II) in FIG. 35)
103Q) and the outer signal (broken line outside (I), (II) FIG. 10).
2Q) is generated and the logical product of both signals is used to extract the contour. In the timing diagram (Fig. 35 (II)), 10
1Q is a signal obtained by binarizing the multi-valued original signal with a predetermined threshold value, and indicates a boundary portion between the original image (hatched portion) and the background in FIG. On the other hand, 102Q expands the “Hi” part of 101Q and makes the character part thicker (the signal after the fattening process), and 103Q degenerates the “Hi” part of 101Q to make the character part Is a signal obtained by further inverting the signal obtained by reducing the signal (the signal after the reduction processing). 104Q is the result of the logical product of 102Q and 103Q, and is the extracted contour signal. The shaded area in 104Q indicates that a wider outline is extracted, which is 10
By selecting a wider width in 2Q and a larger degeneration width in 103Q, contours with different widths are extracted. That is, the width of the contour can be changed. FIG. 35 (f) is an example of a circuit diagram for implementing the contour processing described in FIG. 35 (d). This circuit is provided in the image processing / editing circuit G shown in FIG. The input multi-valued image data 138 is compared in magnitude by a comparator 2q with a predetermined threshold value 116q to generate a binary signal 101q. The threshold value 116q is an output of the data selector 3q, a value set in the register group 4q for each color, yellow, magenta, cyan, and black to be printed by a CPU (not shown), and an output 1 from r1, r2, r3, and r4.
These signals are selected and output by the selector 3q corresponding to the same color from 10q to 113q. That is, from a CPU not shown,
By the signals 114q and 115q that are switched for each color, the threshold value for binarization can be varied for each color, and the effect of the color contour can be varied. The data selector 3q is, for example, (114q, 115
q) = (0,0), (0,1), (1,0), (1,1), so that A, B, C, and D are selected, respectively. Corresponds to the magenta, cyan, and black thresholds. The binary signal 101q is stored in the line buffers 5q to 8q for 5 lines, and the next-stage thickening circuit 150q and the thinning circuit 151q are stored.
Is output to 150q is a circuit that generates signal 102q, 5x
If at least one of the 25 (or 9) pixels in the 5 (or 3 × 3) small pixel block has “1”, the value of the center pixel is set to “1”.
It operates as determined by That is, two pixels (or one pixel) with respect to the original image (hatched portion) in FIG.
Is formed. Similarly, 151q is a circuit for generating a signal 103q. If at least one of the 25 (or 9) pixels in the 5 × 5 (or 3 × 3) small pixel block has “0”, the value of the center pixel is changed. Operates to determine "0". this is,
In FIG. 35 (a) (I), a signal I inside two pixels (or one pixel) is formed. Therefore, as described with reference to FIGS. 35 (a) and (II), the logical product of 102q and 103q is AND gate 41q.
To generate a contour signal 104q. As can be seen from the circuit operation, the signals 110q and 111q correspond to the aforementioned small pixel block by three.
It is a selection signal for selecting 3 × or 5 × 5, and 3 ×
When 3 is selected, (110q, 111q) = (0, 1), and the outline width at this time is two pixels since the width is one pixel and the width is one pixel. When selecting 5 × 5, (11
(0q, 111q) = (1,1), and similarly, the outline width is 4 pixels. This is controlled by an I / O port connected to a CPU (not shown) so that the operator can switch according to the application and desired effect.

In FIG. 35 (f), the selector 45q is a selector for switching between outputting the original signal 138 as it is or outputting the extracted contour. Based on the output of the selector 45'q,
Either A or B is selected. The selector 45'q outputs an inverted signal of the contour signal 104q and an I / O connected to a CPU (not shown).
One of the EDSL signals output from the port is output as a select signal of the selector 45q. At this time, the select signal SEL is input from the CPU to the selector 45'q.

The selector 44q is a selector for selecting fixed values r5 and r6 set in the registers 42q and 43q by the CPU according to the contour signal 104q. The selectors 44q, 45q, 45'q select A when the switching terminal S = 0 and B when the switching terminal S = 1.

When "1" is input to the switching terminal of the selector 45'q, the terminal on the B side is selected, and the selector 45q is connected to a CPU (not shown).
It is switched by the signal ESDL output from the I / O port connected to. And when ESDL = "0", the selector 45q
A side is selected and the normal copy mode is selected, and when ESDL = "1", the B side is selected and the contour output mode is set. q42 and q43 are registers in which fixed values r5 and r6 are set by a CPU (not shown), and the contour output 104q is set when the contour output mode is selected.
When r is "0", the value of r5 is output, and when 104q is "1", the value of r6 is output. That is, for example, when r5 = 00 _H, r6 = the FF _H is set, the contour portion as the FIG. 35 (e) is, FF _H namely black, other portions becomes 00 _H, i.e. white, An outline image is formed. Since the values of r5 and r6 are programmable, different effects can be obtained by changing them for each color. That is, it is not always necessary to set FF _H and 00 _H, and two different levels such as setting FF _H and 88 _H may be set.

On the other hand, when "0" is set to the switching terminal S of the selector 45'q, the A side is selected, and an inverted signal of the contour signal 104q is input to the switching terminal S of the selector 45q. And for the selector 45q The contour is output original data A side, with respect to the other edge portion, 00 _H namely white selected by the selector 44q of the fixed value of the B-side is output. In this way, it is possible to apply a process to the contour portion using multi-valued original data instead of fixed values for each of Y, M, C, and K.

As described above, according to the present embodiment, a mode for outputting a binary contour image for each of Y, M, C, and K (multiple color contour processing mode) and a mode for outputting a multi-valued contour image (full color contour processing mode) ) Can be arbitrarily selected by the operator.

In addition, the threshold for contour extraction is also stored in the register 4q as r1, r2, r.
By setting 3, r4, different values can be set for each of Y, M, C, and K. The value can be appropriately rewritten by the CPU.

Also, by selecting the matrix size,
The width of the contour can be changed, and a contour image of a different image can be obtained.

Note that the matrix for contour extraction is 5 × 5 and 3 × 3.
The present invention is not limited to this, and can be freely changed by increasing or decreasing the number of line memories and gates.

The contour processing circuit Q shown in FIG. 35 (f) is provided in the image processing / editing circuit G shown in FIG. The image processing / editing circuit G further includes a texture processing section 101g,
Although a mosaic / taper processing unit 102g is provided, since these are connected in series, any processing can be freely combined by operating the operation unit 1000 described later. Also, the order of various processes can be freely set by arranging the respective processing units in parallel and combining the selectors.

In the present embodiment, binarization is performed for each color component input to the outline processing circuit Q, an outline signal is obtained for each color component, and an outline image is output in a color corresponding to the color component.
The method is not necessarily limited to such a method.
An ND image signal is generated from (red), G (green), and B (blue), an outline is extracted based on the ND image signal, and original multi-valued data or predetermined binary data for each recording color is applied to the outline. To form a contour image. At that time, an ND image signal can be generated based on one of the R, G, and B signals. In particular, since the G signal has the closest characteristic to the neutral density signal (ND image signal), it is effective to use this signal directly as the ND signal from the viewpoint of the circuit configuration and the like.

 Alternatively, an NTSC Y signal (luminance signal) may be used.

<Non-Rectangular Area Storage Unit> Next, means for storing the non-rectangular area specified in the present invention will be described.

Conventionally, in the designated area editing process, the designated area is only possible to be a rectangle or a non-rectangular FIG. 37 (f) with a limit on the number of input points and a mixed FIG. 37 (g) of the rectangle and the non-rectangle. Therefore, there were the following disadvantages.

That is, as shown in FIG. 37 (h), the red “Fuji”
Can not be converted to green with the free color, or only the red cloud portion can be painted blue, so that the editing process is severely limited.

Therefore, in this embodiment, by providing a memory for storing a non-rectangular area, it is possible to cope with such advanced editing processing.

FIG. 37 (a) is a block diagram showing details of a bit map memory 573L for a mask for limiting an area of an arbitrary shape and its control. This memory corresponds to a 100 dpi memory L in the entire circuit of FIG. 2, and has a shape as shown in FIG. 37 (e), for example, the above-described color conversion, image cutting (non-rectangular trimming), image It is used as a means for generating ON (processing) and OFF (not processing) switching signals for various image processing and editing such as painting (non-rectangular paint). That is, in FIG. 2, the color conversion circuit B, the color correction circuit D, the character synthesizing circuit F, the image processing and editing circuit G, the color balance circuit P, and the external device image synthesizing circuit 502 are used for ON / OFF switching signals. BHi12 each
3, supplied by the signal lines of DHi122, FHi121, GHi119, PHi145, and AHi148.

Note that the term “non-rectangular” described here is not intended to exclude a rectangle, and a rectangular area is also included in the non-rectangular area.

As shown in FIG. 38, the mask is configured such that one block is composed of 4 × 4 pixels, and one block corresponds to one bit of the bit map memory.
For an image having a pixel density of 297 mm × 420 mm (A3 size), (297 × 420 × 16 × 16) ÷ 16 ≒ 2 Mbit, that is, for example, a dynamic RAM of 1 Mbit and 2 chips can be used.

Signal 132 input to FIFO559L in FIG.
Is a non-rectangular area data input line for generating a mask as described above. As the signal 132, for example, 2 in FIG.
The output signal 421 of the value conversion circuit 532 is input through the switching circuit N.

A signal from the reader unit A or the external device interface M is input to the binarization circuit. When the signal 132 is input, first, in order to count the number of "1" in the 4.times.4 block, a buffer 559L, 5 for one bit.times.4 lines.
Input to 60L, 561L, 562L. The FIFOs 559L to 562L are connected such that the output of the 559L is connected to the input of the 560L, the output of the 560L is connected to the input of the 561L, and the outputs of the FIFOs are latched in parallel by 4 bits to the latches 563L to 565L and VCLK. (Refer to the timing chart of FIG. 37 (d)). FIFO output 615L and latch 563L, 564L, 565L output 616L, 617L,
618L is added by adders 566L, 567L, and 568L (signal 602).
L) In the comparator 569L, the CPU 22 compares the value (for example, “12”) set via the I / O port 25L with the magnitude thereof. That is, it is determined whether the number of 1s in the 4 × 4 block is larger than a predetermined number.

In FIG. 37 (d), the number of "1" s in the block N is "14" and the number of 1s in the block (N + 1) is "4", so that the output of the comparator 569L in FIG. 603L is a signal
When 602L is "14", it is "1" because it is larger than "12", and when it is "4", it is "0" because it is smaller than "12". Therefore, the latch pulse 605L shown in FIG. 4 × 4
Is latched once per block of, Q output of the latch 570 is D _IN input of the memory 573L, that is, the mask making data. Reference numeral 580L denotes an H address counter for generating an address in the main scanning direction of the mask memory. One address is assigned by 4 × 4 blocks.
The count is incremented by the clock obtained by dividing 8 by 4 by the frequency divider 577L. Similarly, 575L is an address counter for generating an address in the sub-scanning direction of the mask memory. For the same reason, the frequency divider 574L outputs the synchronization signal HSYNC of each line to 4 bits.
Counted up by the divided clock, H address, V
The operation of the address is controlled so as to synchronize with the operation of counting (adding) "1" in the 4.times.4 block.

Also, the lower 2 bits output of the V address counter, 610
L and 611L are NORed by a NOR gate 572L, and a signal 606L for gating a clock 607L of 4 frequency division is generated, and AND gate
As shown in Fig. 37 (c), timing chart by 571L
A latch signal 605L is generated so that only one latch is performed in 4 × 4 blocks. Also, 616L is CPU bus 22
This is a data bus included in FIG. 2 and can set non-rectangular area data in the bit map memory 573L according to an instruction from the CPU 20. For example, as shown in FIG. 3 (e), a circle or an ellipse is obtained by calculation of the CPU 20 (the procedure will be described later), and the calculated data is written to the memory 573L to generate a fixed non-rectangular mask. Can be. At this time, for example, the radius and the center position of the circle can be specified by a numeric keypad of the operation unit 1000 (FIG. 2) or input by the digitizer 58. Similarly, 613L is an address bus, and signal 615L is a write pulse WR from CPU22. WR (write) from CPU22 to memory 573L
During operation, the write pulse becomes “Lo” and the gates 578L and 576
L and 581L are opened, an address bus 613L and a data bus 616L from the CPU 22 are connected to the memory 573L, predetermined non-rectangular area data is written at random, and a sequential WR (write) is performed by an H address counter and a V address counter. When performing RD read, the gates 576'L, 582L are controlled by the control lines of the gates 576'L, 582L connected to the I / O port 25L.
2L is opened, and a sequential address is supplied to the memory 573L.

For example, if the mask as shown in FIG. 39 is formed by the output 421 of the binarized output 532 or the CPU 22, the image can be cut out and synthesized based on the area within the thick line frame.

Further, the bit map memory 573L of FIG. 37 (a) can be read out by reducing or enlarging by thinning out or interpolation in both the H and V directions at the time of reading. That is, as shown in FIG. 40 in detail of the H or V address counter (580L, 575L) of FIG. 37, for example, at the time of reduction, the MULSEL63 is selected so that the B input of the selector 634L is selected.
6L is set to “0”. The selection signal 636L is sent through the CPU 22. 635L is a thinning circuit (rate multiplier) for the input clock 614L. Fig. 41 (Timing diagram)
As shown in (1), thinning is performed so that, for example, CLK is output once every three times (setting is performed by the I / O port 641L) (637).
L). On the other hand, for example, "2" is set in the 630L, and the address counter 632L is set only when the thinned output 637L is output.
The set value (for example, "2") is added to the outputs 638L and 630L, and the result is loaded into the counter. Therefore,
As shown in FIG. 41, the process proceeds by "+2" every three clocks in the order of 1 → 2 → 3 → 5 → 6 → 7 → 9. On the other hand, at the time of enlargement, MULSEL = “1”, and the A input 614L is selected, so that the address count is 1 → 2 → 3 → 3 → 4 → 5 → 6 → 6 →. And proceed.

FIG. 40 shows the H address counter 580L, V of FIG. 37 (a).
Since the details of the address counter 575L are the same and the hardware circuit is the same, the description will be limited to FIG. 37 (a) only.

Under the control of this address counter, enlargement 2 and reduction 1 are generated for the non-rectangular area 1 immediately input as shown in FIG. 42, so once the non-rectangular area is input,
The magnification can be changed according to various magnifications with one mask plane without performing a new input operation.

Next, the binarization circuit (FIG. 2 532) and the high-density binary memory circuit K will be described. FIG. 43 (a) shows a binarization circuit.
Reference numeral 532 denotes a circuit for comparing the video signal 113 output from the character image correction circuit E with a threshold value 141k to obtain a binary signal. The threshold value is set by the CPU bus 22 in conjunction with the operation unit. That is, the threshold value is 43
When the memory of the operation unit in FIG. 9C is designated as M (middle point), the value is “128”. As the scale moves in the + direction, the value changes by −30 from the middle point, and as the scale moves in one direction, “+30”. "Everything changes. Therefore, “weak → −2 → −1 → M → + 1 → + 2
The threshold value is “218 → 188 → 158 → 128 → 98 →
It is controlled to change from 68 to 38 ".

As shown in FIG. 43 (a), two threshold values are set from the CPU BUS 22, and are switched by the selector signal 35k by the switching signal 151, and are set as the threshold values in the comparator 32k. The switching signal 151 from the area generating circuit J is set to a different threshold value only in the specific area set by the digitizer 58,
For example, the threshold value of the monochrome region of the document is set relatively low, and the color mixture region of the document is set relatively high, so that a uniform binary signal can be always obtained regardless of the color of the document.

The memory circuit K is a memory for storing a signal in which the binarized signal 421 is output to 130 for one page of an image. In this device, the image is handled with an A3 size and a density of 400 (dpi). It has about 32Mbit. FIG. 43B illustrates details of the memory circuit K. The input data D _IN 130 is the enable signal HE from the area generation circuit J when writing to the memory.
Gated at 528, and the W /
When one signal 549 is "Hi", it is input to the memory unit 37k. At the same time, the synchronization signal HSYNC 118 in the main scanning (horizontal scanning) direction is counted from the synchronization signal ITOP 144 in the vertical direction of the image, and a vertical address is generated. The image transfer clock VCLK 117 is counted by the V address counter 35k and the HSYNC 118, and the horizontal address is counted. An address corresponding to the storage of the image data is generated by the H address counter. At this time, a clock having the same phase as the clock VCLK117 is input to the memory WP input (write timing signal) 551k as a strobe, and the input data Di is input.
Are sequentially stored in the memory unit 37k (timing diagram, 4th
4). When reading data from the memory 37k, the control signal W / 1 is set to "Lo", and the procedure is exactly the same.
The output data D _OUT is read. However, the data writing, reading, since both carried out in HE528, for example, the HE528 as of FIG. 44 at an input timing of the D _2, "H
i "raised to, at the input timing of D _m" Lowering standing Lo ", the memory 37k only images from D ₂ to D _m is input, D _0, D ₁ and D _{m + 1} after Is not written, and data “0” is written instead.
Data other than the section in which HE is “Hi” is read “0”. HE is an area signal generation circuit 17 described later.
Output. That is, for example, when a character document as shown in FIG. 45A is placed on the document table, if the HE is generated as shown in FIG. Images can be captured in memory. Similarly, unnecessary characters and the like can be erased and written to the memory.

Further, the address counters 35k and 36k for reading the data of the memory 37k operate in the same configuration as in FIG. 40 and at the same timing as in FIG. 41.
Can be scaled. Therefore, when a binary character image as shown in FIG. 46B, which is stored in the main memory in advance as shown in FIG. 46, is combined with the image shown in FIG. As shown in FIG. 4D, the composition such as enlarging only the character portion to be composed without changing the size of the sketch (portion A) is possible.

FIG. 47 shows the binary bitmap memory L (FIG. 2) for non-rectangular masks stored at 100 dpi as described above and characters,
The distribution of the data from the line image 400 dpi binary memory K (FIG. 2) to each image processing block A, B, D, F, P, G, and the binarized video image to the memory L, K This is a switching circuit for switching distribution and performing real-time selectable output of rectangular and non-rectangular area signals. The rectangular / non-rectangular area real-time switching will be described later. The mask data for limiting the non-rectangular area stored in the memory L is sent to, for example, the above-described color conversion circuit B (BHi123).
Color conversion is applied only inside the shape as shown in FIG. 48 (B). In FIG. 47, 1n is an I / O port connected to the CPU bus 22, 8n to 13n are 2to1 selectors, and a switching input S =
The A input is output to Y when "9" and the B input is output to Y when S = "0". So, for example, 100d
In order to send the output of the pi mask memory L to the color conversion circuit B, A is selected by the selector 9n, that is, 28n =
"1", in the AND gate 3n, the 21n input may be set to "1". Similarly, other signals can be arbitrarily controlled by 16n to 31n. Output of I / O port n1, 30n and 31n are binarization circuits 532
When 30n = “1”, which is a control signal indicating whether the output of FIG. 2 is stored in the binary memory L or K, the binary input 421 is 100d
The pi memory L is input to the 400 dpi memory K when 31n = "1". By the way, when AHi148 = “1”, the image data sent from the external device is synthesized, and BHi123 =
When “1”, color conversion is performed as described above, and DHi122 = “1”
At this time, monochrome image data is calculated and output from the color correction circuit. FHi 121, PHi145, GHi1 119, GHi21
49 is used for character synthesis, color balance change, texture processing, and mosaic processing, respectively.

As described above, there are two binary memories of the 100 dpi memory L and the 400 dpi memory K, and character information is input to the high density 400 dpi memory K, and area information (including rectangles and non-rectangles) is input to the 100 dpi memory L. Thus, character synthesis can be performed in a predetermined area, particularly in a non-rectangular area.

Further, by having a plurality of bit map memories, a color processing as shown in FIG. 62 becomes possible.

FIG. 49 is a view for explaining the area signal generation circuit J. The region means, for example, a portion such as a hatched portion in FIG. 49 (e), which corresponds to a section in the sub-scanning direction A → B for each line as in the timing chart AREA in FIG. 49 (e). Signal is distinguished from other areas. Each area is specified by the digitizer 58 in FIG. FIGS. 49 (a) to 49 (d) show a configuration in which the generation position, section length, and number of sections of the area signal can be obtained by the CPU 20 in a programmable manner. In this configuration, one area signal is generated by one bit of a RAM accessible to the CPU. For example, in order to obtain n area signals AREA0 to AREAn, an n-bit RAM is used.
(Fig. 49 (d) 60j, 61j). Now, the fourth
When obtaining a region signal AREA0 and AREAn such as Figure 9 (b), set a "1" in bit 0 of the address of the RAM x _1, x _3,
Bits 0 of the remaining addresses are all set to "0". Meanwhile, RA
Make a "1" to M address 1, x _1, x _2, x _4, and that all the bits n of other addresses "0". HSYNC118 in synchronism with the constant clock 117 as a reference, As you read sequentially Shikenshiyaru data RAM for example, as in the 49 view (c), the data in terms of addresses x ₁ and x ₃ "1" is read out It is.
The read data is shown in FIG. 49 (d) 62j-0 to 62j.
The output is a toggle operation, that is, "1" is read out from the RAM and CLK is input, so that the output becomes "0" → "1", “1” →
Changing to "0", an interval signal such as AREA0, and thus an area signal, is generated. When data = "0" over all addresses, no area section occurs and no area is set. FIG. 49 (d) shows this circuit configuration, where 60j and 61j are the above-mentioned RAMs. This is because, for example, while data is being read out line by line from the RAMA 60j in order to switch the area section at high speed, the CPU 20 (FIG. 2) writes a different memory write operation to the RAMB 61j for the area setting. Is performed, the interval generation and the memory writing from the CPU are alternately switched. Therefore, when the shaded area in FIG. 49 (f) is designated, the RA is changed to A → B → A → B → A.
MA and RAMB are switched. If (C ₃ , C ₄ , C ₅ ) = (0,1,0) in FIG. 49 (d), the counter output counted by VCLK 117 becomes an address. Selector 63
(Aa), the gate 66j is opened, the gate 68j is closed and read from the RAM 60j, and the entire bit width is
The n bits are input to the JK flip-flops 62j-0 to 62j-n, and a section signal of AREA0 to AREAAn is generated according to the set value. Writing from B to the CPU is performed by the address bus A-Bus, the data bus D-Bus, and the access signal / during this time. Conversely, when the section signal is generated based on the data set in the RAMB61j (C ₃ , C ₄ ,
C ₅₎ = (1,0,1) by a, performed in the same way, perform the data write to RAMA60j from CPU.

Reference numeral 58 denotes a digitizer for specifying an area.
Enter the coordinates of the specified position from 0 through the I / O port. For example, in FIG. 50, when two points A and B are designated, A (X ₁ ,
The coordinates of Y ₂ ) and B (X ₂ , Y ₁ ) are input.

FIG. 37 (i) is a diagram for explaining a method of performing processing and editing processing on each area when images of a rectangular area and a non-rectangular area are mixed in one document. sgl1 to sg
ln and ArCnt are rectangular area signals, such as the signals AREA0 to AREAn of the rectangular area generation circuit shown in FIG. 49 (d).

On the other hand, Hi is a non-rectangular area signal such as the bit map memory L shown in FIG. 37 (a) and the output 133 of the control circuit thereof.

In sgl1~sgln (h _2l ~h _2n) is an enable signal for each of the editing processing, for the rectangular area, all enabled where you want subjected to editing processing. On the other hand, for the non-rectangular area, only the rectangular area inscribing the non-rectangular area is enabled. Specifically, as shown in FIG. 37 (n), the non-rectangular area shown by the solid lines A and B enables the rectangular area shown by the dotted line.

ArCnt (h ₃₎ is enabled in synchronization with sgl1~sgln for the rectangular region. On the other hand, a non-rectangular area is enabled.

Hi (h ₂ ) is enabled in the non-rectangular area for the non-rectangular area. The device is enabled for a rectangular area.

Hi signal h ₂ and ArCnt signal h ₃ is the logical sum is taken by OR circuit h _1, sgl1~sgln and now AND circuit _{h 3l ~h 3n (h 2l ~h} 2n)
And is taken.

Thus consisting output out1~outn (h _4l ~h _4n) allows mixed desired rectangular region signal and a non-rectangular signal.

FIGS. 37 (j) to 37 (m) are diagrams for explaining what each input signal looks like when a rectangular area signal (B) and a non-rectangular area signal (A) are mixed.

As described above, sgl1 to sgln (FIG. 37 (k)) are enabled for the whole area for a rectangle and for a rectangular area inscribing a non-rectangular area for a non-rectangle.

As for Hi (FIG. 37 (l)), as described above, the device is enabled for rectangles and the entire region is enabled for non-rectangles.

As shown in FIG. 37 (m), the entire area is enabled for rectangles and the entire area is enabled for non-rectangles.

 Finally, the correspondence between FIG. 37 (i) and FIG. 47 will be described.

OR gate h ₁ 47th view of FIG. 37 (i), 38n, the OR gate 39n, the AND gate h _3l to h _3n of Figure 37 (i) is 47 4
The area signals of FIG. 37 (i), sgl1 to sgln (h
_{2l to} h _2n ) correspond to the output out of FIG.
1~outn (h _4l ~h _4n) is DHi, FHi, hit the PHi, GHi1, GHi2.

As described above, editing and processing can be performed on a plurality of regions in which a rectangular region and a non-rectangular region are mixed in one document.

According to this embodiment as described above, means for designating means (domain signal Sgl1～sgln) non-rectangular region to specify the rectangular area (Hitsuto signal HIH _2), the rectangular area, real-time selecting means non-rectangular region by providing (aND gate h _3l ~h _3n), it is possible to perform the editing processing rectangular area specified and non-rectangular area designation are mixed in one document.

In particular, according to the present embodiment, the signals sgl1 to n are non-rectangular area signals
It is possible to select a rectangle or non-rectangle according to Hi and the rectangular area signal ArCnt.

In addition, the area can be specified according to the nature of the area to be specified, for example, a rectangle can be specified when rough specification is sufficient, and a non-rectangular area can be specified when high precision is required. It can be carried out.

The number of regions, that is, the number of AND gates can be freely set. Further, the type of processing to be performed on each area can be freely determined by setting the I / O port 1n based on an input from the operation unit 1000.

FIG. 51 shows an interface circuit M for performing bidirectional communication of image data with an external device connected to the image processing system. 1m is an I / O port connected to the CPU bus 22, and outputs signals 5m to 9m for controlling the directions of the data buses A0 to C0, A1 to C1, and D. 2m and 3m are bus buffers having an output dry-state control signal E, and 3m is D bus
The direction can be changed by input. 2m, 3m is E
When the input is “1”, a signal is output. When the input is “0”, the output is in a high impedance state. 10m selects one from three parallel inputs A, B, and C using selection signals 6m and 7m.
It is a selector. In this circuit, basically, 1. (A0, B0,
There is a bus flow of (C0) → (A1, B1, C1), 2. (A1, B1, C1) → D. Each is controlled by the CPU 20 as shown in the truth table of FIG. In this system, as shown in FIG. 53, images input from external devices through A1, A2, and A3 can be rectangular as shown in FIG. 53 (A) or non-rectangular as shown in FIG. 53 (B). It has a configuration. Fig. 53 (A)
In the case of inputting a rectangle as shown in FIG.
The control signal 147 is output from the I / O port 501 so that the switching input 3 is set to “1” so that A is selected. At the same time, it corresponds to the area to be combined. RA in the area signal generation circuit J
As described above, the CPU writes predetermined data to predetermined addresses of M60j and 61j (FIG. 51), thereby generating a rectangular area signal 129. Image input from external device 128
In the area selected by the selector 507, the image data 128
Not only that, but also the gradation and resolution switching signal 140 are switched at the same time. That is, in an area where an image from an external device is input, a gradation area generated based on a character area signal MjAR 124 (FIG. 2) detected from a color separation signal of an image read from a document table. By stopping the resolution switching signal and forcibly setting it to "Hi", the image area from the external device to be fitted is smoothly output in high gradation. As described with reference to FIG. 51, when the bit map mask signal AHi 148 from the binary memory L is selected by the selector 503 by the signal 147, image synthesis from an external device as shown in FIG. Is realized.

<Overview of Operation Section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. A key 1100 is a copy start key. The key 1101 is a reset key, and all the settings on the operation unit are returned to the values at power-on. A key 1102 is a clear stop key used to reset the input numerical value such as the number of copies and to stop the copying operation. A group of keys 1103 is a numeric keypad used for inputting numerical values such as the number of copies and magnification. A key 1104 is a document size detection key. A key 1105 is a center movement designation key. A key 1106 is an ACS function (black original recognition) key. When ACS is ON, copy a single black color original in black. A key 1107 is a remote key for giving control to a connected device. Key 1108 is a preheat key.

Reference numeral 1109 denotes a liquid crystal screen for displaying various information. Also, the surface of the screen is a transparent touch panel, and when pressed with a finger or the like, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies,
The copy density is displayed. While various copy modes are being set, the screens required for mode setting are sequentially displayed.
(The copy mode is set using the keys displayed on the screen.) The self-diagnosis display screen of the guide screen is displayed.

A key 1110 is a zoom key, and is an enter key for a mode for designating a magnification ratio. A key 1111 is a zoom program key, and is an enter key for a mode for calculating a magnification ratio from a document size and a copy size. Key 1112
Is an enlarged continuous shooting key, and is an enter key for an enlarged continuous shooting mode. A key 1113 is a key for setting the fit synthesis. A key 1114 is a key to be set in character synthesis. Key
Reference numeral 1115 denotes a key for setting a color balance. Key 1116
Is a key for setting a color mode such as monochrome / negative / positive reversal. A key 1117 is a user's color key, and an arbitrary color mode can be set. A key 1118 is a paint key, and can set a paint mode. A key 1119 is a key for setting a color conversion mode. A key 1120 is a key for setting a contour mode. A key 1121 sets a mirror image mode. Keys 1124 and 1123 specify trimming and masking. An area can be designated with the key 1122, and the internal processing can be set differently from other parts.
A key 1129 is an enter key for a mode for performing operations such as reading a texture image. A key 1128 is an enter key for a mosaic mode such as changing a mosaic size.

A key 1127 is an enter key for a mode for adjusting the sharpness of an edge of an output image. A key 1126 is a key for setting an image repeat mode for repeatedly outputting a designated image.

A key 1125 is a key for applying italic / taper processing or the like to an image. A key 1135 is a key for changing the movement mode. A key 1134 is used to make settings such as continuous page copying and arbitrary division. A key 1133 is used to make settings related to the projector.
A key 1132 is an enter key for a mode for controlling a connected device of the option. The key 1131 is a recall key, and can recall settings up to three times before. Key 1130 is an asterisk key. Keys 1136 to 1139 are mode memory call keys, which are used when calling the registered mode memory. Keys 1140 to 1143 are program memory recall keys, which are used when recalling a registered operation program.

<Color Conversion Operation Procedure> The procedure of the color conversion operation will be described with reference to FIG.

First, press the color conversion key 1119 on the main unit operation panel to display
1109 is displayed like P050. Place the original on the digitizer and specify the color before conversion with the pen. When input is completed
The screen of P051 is displayed. Here, the width of the color before conversion is adjusted using the touch keys 1050 and 1051, and after the setting is completed, the touch key 1052 is pressed. The screen changes to P052, and the touch key 1053 and the touch key 1054 are used to select whether to add shades to the converted color. If the shade is selected, the converted color also has a gradation in accordance with the shade of the color before conversion. That is, the above-described gradation color conversion is performed. On the other hand, if no shading is selected, it is converted to a designated color having the same density. If you select “with / without shading”, the screen changes to P053 and the type of color after conversion is selected. 10 in P053
If 55 is selected, the operator can specify any color in P054. When the color adjustment key is pressed, the processing shifts to P055, and color adjustment can be performed for each of Y, M, C, and Bk in increments of 1%.

Pressing 1056 on P053 moves to P056, where the point pen is used to specify the desired color of the original on the digitizer. Next, in P057, the shading of the color can be adjusted.

When 1057 is pressed in P053, the process proceeds to P058, where a predetermined registered color can be selected by a number.

<Procedure for Specifying Trimming Area> Hereinafter, referring to FIGS. 56 and 57, the procedure for specifying the trimming (similarly to the masking method, and also to the partial processing, etc., is the same procedure). explain.

Press the trimming key 1124 on the main unit operation unit 1000, and when the display unit 1109 is set to P001, enter two diagonal points of the rectangle using the digitizer to display the screen of P002, and then enter the rectangular area continuously it can. When multiple areas are specified, the area key 1001 before P001, then the area key
By pressing 1002, each designated area in the XY coordinates can be confirmed as in P002.

On the other hand, in this embodiment, a non-rectangular area can be designated using the bit map memory. While the screen of P001 is displayed, press the touch key 1003 to move to P003. Select the shape here. When necessary coordinate values are input for a circle, an ellipse, an R rectangle, and the like, the CPU 20 calculates and develops the shape into the bit map memory. In the case of free shape, digitizer 58
Is used to continuously input coordinate values by tracing a desired shape with a point pen, process the values, and record them on a bit map.

 Hereinafter, each of the non-rectangular area designations will be described.

(Circular area designation) When the key 1004 is pressed in P003, the display unit 1109 shifts to P004 and can designate a circular area.

Hereinafter, the circular area designation will be described with reference to the flowchart in FIG. In S101, the center point is input from the digitizer 58 in FIG. 2 (P004). Next, the display unit 1109
Moves to P005 and inputs one point on the circumference of a circle having a radius to be designated from the digitizer 58 in S103. In step S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bit map memory L (100 dpi binary memory) shown in FIG.

In S107, the coordinate value of another point on the circumference is calculated. Next, in S109, the bank of the bit map memory L is selected,
In S111, the above calculation result is input to the bit map memory L via the CPU bus 22. In FIG. 37 (a), the CPU DAT
The data is written from the A 616L to the bit map memory from the 604L via the driver 578L. The address control is the same as that described above, and will not be described. This is repeated for all points on the circumference (S113), and the designation of the circular area ends.

Instead of inputting while calculating with the CPU 20 as described above, the template information for the previously input two points of information is stored in the ROM 11, and the two points are directly specified without calculation by designating with a digitizer. The data may be written in the bitmap memory L.

(Oval area specification) Pressing the key 1005 in P003 moves to P007. The following
This will be described with reference to the flowchart in FIG.

First, in step S202, two diagonal points of the largest rectangular area inscribed in the ellipse are designated by the digitizer 58. Hereinafter, for the circumferential portion, S206 to S212 are performed in the same manner as in the case of specifying the circular area.
Is written to the bit map memory L by the following procedure.

Next, the linear portion is written in the memory L in the steps S214 to S220, and the area designation is completed. As in the case of a circular shape, it can be stored in advance in the ROM 21 as template information.

(R rectangle area designation) This is the same as the designation method in the case of writing an ellipse in both the memory writing and the description is omitted.

Although the case of a circle, an ellipse, and an R rectangle has been described above as an example, it is needless to say that other non-rectangular areas can be specified based on the same template information.

In P006, P008, P010, and P102, when the clear key (1009 to 1012) is pressed after each shape input, partial deletion on the bit map memory can be performed.

Therefore, even if you make a specification mistake,
Only point designation can be cleared and only two point designations can be performed again.

In addition, it is possible to continuously specify a plurality of areas. In the case of specifying a plurality of areas, the processing of the area specified later is prioritized in performing each processing on the overlapping area. However, for this, the priority may be given to the one specified earlier.

FIG. 57 shows an output example in which trimming is performed on an ellipse with the above settings.

<Operation Procedure for Character Synthesis> The operation setting procedure for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When the character synthesis key 1114 on the main body operation unit is pressed, the liquid crystal display unit 1109 is displayed as P020. When the character document 1201 to be synthesized is placed on the document table and the touch key 120 is pressed, the character document is read, binarized, and the image information is stored in the bit map memory shown in FIG. Since the specific means of the processing has been described above, duplication is avoided. To specify the range of the image to be stored at this time, press the touch key 1021 in P020 to go to the screen of P021, place the character document 1201 on the above-mentioned digitizer 58, and specify the range with two points using the digitizer's point pen. I do. When the specification is completed, the display unit becomes P022, and selects whether to read in the range specified by the touch keys 1023 and 1024 (trimming) or to read outside the specified range (masking). In addition, it is difficult to extract a character portion in a character document during the above-described binarization processing for some character documents.
Use the middle touch key 1022 to move to the screen of P023, and change the slice level of the binarization processing to the touch key 1025 and the touch key.
It can be adjusted in 1026.

As described above, the slice level can be manually adjusted, so that appropriate binarization processing can be performed according to the color and thickness of the characters of the document.

Further, by pressing the touch key 1027 and designating an area with P024 'and P025', it is possible to partially change the slice level at P026 '.

In this way, by specifying the area and changing the slice level only for that part, even if there is, for example, a yellow character in a part of the black character original, separate appropriate slice levels are set for each of the black and yellow characters By doing so, good binarization processing can be performed on the entire character.

In this case, it goes without saying that such processing can be performed according to the non-rectangular area information stored in the binary memory L of FIG.

When the reading of the text original is completed, the display unit 1109 displays the P024 in FIG. 61.
become that way.

To select the color skipping process, press the touch key 1027 in P024 to move to the screen of P025, and select the color of the character to be synthesized from the displayed colors. In addition, the color of the text can be changed partially.In that case, press the touch key 1029 to move to the screen of P027, specify the area, and then
Select the text color on the screen. Further, a color bordering process can be added to the border of the character to be synthesized. In this case, the screen is shifted to the screen of P032 by the touch key 1031 in P030, and the color of the border portion is selected. At this time, the color can be adjusted in the same manner as in the color conversion. Plus Touch Key 10
Press 33 to adjust the border width on the screen of P041.

Next, a case will be described in which a color covering process is added to a rectangular area including a character to be combined (hereinafter, referred to as a mud process). P024
Press the middle touch key 1028 to move to the screen of P034 and specify the area. Mado processing is performed in the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen shifts to P039, and the color of the mud is selected.

In the above color selection, for example, on the screen of P025, by pressing the color adjustment key of the touch key 1030,
Screen, and the color tone of the selected color can be changed.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an output example when the setting is actually performed.

In the area specification, a non-rectangular area as described above can be specified in addition to the rectangular area specification.

<Texture processing setting procedure> Next, the texture processing will be described with reference to FIG.

When you press the texture key 1129 on the main body operation unit 1000,
The display 1109 displays like P060. To apply texture processing, press the touch key 1060 to highlight this key. When the image pattern for texture processing is read into the above-mentioned texture image memory (113g in FIG. 32), the touch key 1061 is pressed. At this time, if the pattern is already in the image memory, the display is P061 if it is not displayed, as in P062. By placing the original of the image to be read on the original platen and pressing the touch key 1062, the image data is stored in the texture image memory. At this time, in order to read any part of the original, press the touch key 1063, and on the P063 screen,
Specify with 58. The specification can be made by inputting a pen with one point at the center of the reading range, 16 mm × 16 mm.

Reading of the texture pattern by specifying one point as described above can be performed as follows.

Without touching the pattern, press the touch key 1060 to set the texture processing, and
00 or another mode key (1110-1143) or touch key
When trying to escape the P064 screen with 1064 etc., the display section
Give a warning as shown on page 065.

The reading range can also be configured so that the operator can specify the length in the vertical and horizontal directions using the numeric keypad of the operation unit 1000.

FIG. 63 (b) shows the state when reading the texture pattern.
3 shows a flowchart of the CPU 20.

First, when you enter the texture mode, the digitizer
From 58, it is determined whether or not the coordinates of the center point of a portion to be used as a texture pattern on the document (a square is taken as an example in the present embodiment, but another figure such as a rectangle) is input (s1). At that time, the coordinate input is as shown in S1 '
It is grasped by the (χ, y) coordinates of the input point. If there is no coordinate input, the input waits. If there is an input, the horizontal, memory write start, and memory write end addresses are calculated (s2 ') and set in a vertical counter (s2). At this time, a rectangular pattern can be obtained by making the lengths a of the sides different in the horizontal direction and the vertical direction. Next, scanning is performed by the scanner unit A, the image data is read, and the image data at the predetermined position is written in the texture memory 113g (FIG. 32). This completes the texture pattern storage operation.
A normal copying operation is performed by the method described above (s4), and a texture pattern is synthesized.

According to the present embodiment, the texture pattern can be read by designating one point on the digitizer, and there is an excellent effect that the operability is remarkably improved.

<Procedure for Setting Mosaic Processing> FIG. 64A is a diagram illustrating a procedure for setting mosaic processing.

Press the mosaic key 1128 on the operation panel to display P1
It is displayed as 00. To apply a mosaic process to the original, press the touch key 1400 and highlight this key.

To change the mosaic size at the time of performing the mosaic processing, press the touch key 1401 to perform the change on the P101 screen. The change of the mosaic size can be set independently in both the vertical (Y) direction and the horizontal (X) direction.

FIG. 64 is a diagram showing a flow of setting the mosaic size described above. When set to mosaic mode, CPU20
Is the mosaic size from the LCD touch panel 1109 (X, Y)
It is determined whether or not has been input (s1). If it is not input, it waits for input. If it is input, the mosaic processing register (No. 34) in the digital processor.
(X, Y) parameters are set in (FIG. 402g). Based on this, the mosaic processing is performed in the size of the horizontal Xmm and the vertical Ymm by the above-described method.

As described above, in the present embodiment, since the mosaic size can be identified independently in the vertical and horizontal directions, it is possible to meet the needs of various image editing processes. Especially, it is considered to be widely used in the field of design.

<Regarding the * mode operation procedure> FIG. 65 is a diagram for explaining the * mode operation procedure.

Pressing the * key 1130 on the main body operation unit 1000 enters the * mode, and the display unit 1109 is displayed as P110. Touch key
The 1500 enters a color registration mode for registering color information used in paint user's color, color conversion, color characters, and the like. A touch key 1501 turns on / off a function of correcting an image missing by the printer. A touch key 1502 is a key for entering a mode memory registration mode. The touch key 1503 enters a mode for specifying a manual feed size. Touch key 1504 enters program memory registration mode. Touchy key 1505
Is a key for entering a mode for setting a default value of the color balance.

(About the color registration mode) Pressing the touch key 1500 when P110 is displayed enters the color registration mode. The display section is as shown in P111, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and adjust the values of the yellow, magenta, cyan, and black components on the screen of P117 in 1% increments. be able to.

To register an arbitrary color on the original, touch
Press 1507, select the registration destination number on the screen of P118, specify using the digitizer 58, set the original on the platen at the time of the screen of P120, and press the touch key 1510 to register.

(About manual feed size specification) As shown on page 112, the manual feed size can be specified for both standard and non-standard sizes.

For an irregular shape, both the horizontal (X) direction and the vertical (Y) direction can be specified in units of 1 mm.

(Regarding Mode Memory Registration) The mode set as shown in P113 can be registered in the mode memory.

(Regarding Program Memory Registration) As shown in P114, a series of programs for performing area designation and predetermined processing can be registered.

(About color balance registration) As shown in P115, color balance can be registered for each of Y, M, C, and Bk.

<Regarding the Program Memory Operation Procedure> The registration operation to the program memory and its use procedure will be described below with reference to FIGS. 66 and 67.

The program memory is a memory function for storing an operation procedure related to the setting and reproducing the procedure. It is possible to connect necessary modes and skip unnecessary screens. As an example, a program memory is used to perform a procedure of performing image repetition by scaling a certain area in a document.

Press the * mode key 1130 on the operation panel of the main unit, display the screen of P080 on the liquid crystal display, and press the program memory key of the touch key 1200. In this embodiment, four programs can be registered. Select the number to be registered on the screen of P081. Thereafter, the mode shifts to the program registration mode. In the program registration mode, for example, a screen 1301 shown in FIG. The skip key of the touch key 1302 is specified when the user wants to skip the current screen.
The clear key of the touch key 1303 is used to stop the registration up to now while registering the program memory and to restart the registration from the beginning. The end key of the touch key 1304 bypasses the registration mode of the program memory, and registers it in the memory of the number determined first.

First, a trimming key 1124 in the main body operation unit is pressed, and an area is designated by a digitizer. The display unit displays P084, but if no more area is to be set here, the user depresses the touch key 1202 to specify that this screen should be skipped. (The screen becomes P085.) Next, when the zoom key 1110 on the main body operation unit is pressed, the display unit becomes P086. Here, set the magnification, and touch
Pressing 03 changes the display to P087. Finally, press the image repeat key 1126 on the operation panel of the main unit, set the image repeat on the screen of P088, and then touch the
To register in the first of program memory.

To call the program registered in the above procedure, the program memory 1 call key 1140 on the main body operation unit is pressed. The display unit displays P091, and waits for an input of an area.
Here, when the area is input using the desiccator, the display unit displays P092, and further proceeds to next P093. When the touch key 1210 is pressed after setting the magnification here, the display becomes P094, and image repeat can be set. When the touch key 1211 is pressed, the mode using the program memory (called the trace mode) is exited. Until the program memory is called up and finished, each key of the edit mode (11
10-1143) are invalidated, and operations can be performed according to the registered program.

FIG. 69 shows a program memory registration algorithm. Turning the screen in S301 means rewriting the display on the display unit with a key or a touch key. If the user presses the touch key 1302 to specify that the currently displayed screen is to be skipped (S303), the information is set on the recording table when the next screen is turned (S305). Then, a new screen number is set in the recording table in S307. When the clear key is pressed, the entire recording table is cleared (S309, S31
1) In other cases, return to S301 and move to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen turning in S401, it is determined whether or not the new screen is a standard screen (S403). In the case of the standard screen, the process proceeds to S411, in which the next screen number is set from the recording table. If the screen is not the standard image, the new screen number is compared with the screen number scheduled in the recording table (S405). Is S4
Move to 09, if there is a skip flag, skip S411 and S4
Return to 01. If they are not equal, a recovery process is performed (S407), and the screen is turned.

Next, means for outputting an image by switching the printing resolution according to the present invention will be described. This means is configured to switch the printing resolution based on the resolution switching signal 140 generated according to the character portion and the halftone portion separated by the character image separation circuit I described above, This corresponds to the driver shown in FIG. In the present embodiment, a character portion is printed at a high resolution of 400 dpi and a halftone portion is printed at 200 dpi. The details will be described below. The PWM circuit 778 which is a part of the driver shown in FIG. 2 is included in the printer controller 700 of the printer 2 shown in FIG.
Receiving the video data 138 which is the final output of the whole circuit diagram and the resolution switching signal 143, the lighting control of the semiconductor laser FIG. 76 711L is performed.

Hereinafter, the details of the PWM circuit 778 which is a part of the driver of FIG. 2 and supplies a signal for outputting a laser beam will be described.

FIG. 73 (A) is a block diagram of the PWM circuit, and FIG. 73 (B).
Shows a timing chart.

The input VIDEO DATA138 is VCLK1
Latched at the rise of 17 and synchronized with the clock. (See (B) FIGS. 800 and 801) The VIDEO DATA 138 output from the latch is subjected to gradation correction by a LUT (lookup table) 901 composed of ROM or RAM, and D / A (digital / analog) converter 902 performs D / A conversion. A / A conversion is performed to generate one analog video signal, and the generated analog signal is input to the next-stage comparators 910 and 911 and compared with a triangular wave described later. Signals 808, 80 input to the other side of the comparator
Reference numeral 9 denotes a triangular wave ((B) FIGS. 808 and 809) which is synchronized with VCLK and individually generated. That is, 2 of VCLK801
The triangular wave WV1 generated by the triangular wave generating circuit 908 according to the triangular wave generating reference signal 806 divided into two by the JK flip-flop 906, for example, and the other triangular wave generating circuit according to 2VCLK. 90
This is the triangular wave WV2 generated in 9. Note that 2VCLK117 'is VCLK
It is generated from a multiplier circuit (not shown) based on 117. Each triangle wave 8
08,809 and VIDEO DATA138 As shown in FIG.
All are generated in synchronization with VCLK. Further, HSYNC inverted to be synchronized with HSYNC 118 generated in synchronization with VCLK
However, the circuit 906 is initialized at the timing of HSYNC. By the above operation, signals having a pulse width as shown in FIG. 3C are obtained at the outputs 810 and 811 of the CMP1 910 and the CMP2 911 according to the value of the input VIDEO DATA 138. That is, in this system, when the output of the AND gate 913 in the figure (A) is "1", the laser is turned on, a dot is printed on the print paper, and when the output is "0", the laser is turned off, and nothing is printed on the print paper. Not done. Therefore, turning off is controlled by the control signal LON (805) from the CPV 20. FIG. 3C shows a state where the level of the image signal Di changes from left to right from "black" to "white". PWM
Since the input to the circuit is “FF” for “white” and “00” for “black”, the output of the D / A converter 902 changes like Di in FIG. On the other hand, the triangular wave is WV1,
In (ii), since the output is like WV2, the output of CMP1 and CNP2 has a narrower pulse width as it goes from black to white like PW1 and PW2, respectively. Also as is apparent from the figure, when selecting PW1, dots of the print paper is P ₁
→ formed at intervals of P _2, the variation of the pulse width has a dynamic range of W1. On the other hand, when PW2 is selected, the dot becomes P
It is formed at intervals of ₃ → P ₄ → P ₅ → P ₆ , and the dynamic range of the pulse width is W2, which is each half the PW1.
By the way, for example, the printing density (resolution) is about 200 at PW1.
Set to about 400 lines / inch for lines / inch, PW2. As is clear from this, when PW1 is selected, the gradation is improved about twice as compared with PW2, while when PW2 is selected, the resolution is remarkably improved. Therefore, for example, if a high resolution is required, PW2 is provided from the reader unit (FIG. 1) so that PW1 is selected if a high gradation is required. That is, 912 in FIG. 73 (A) is a selector and LCHG1
When 43 is "0", the A input is selected, that is, when PW1 is "1", PW2 is output from the output terminal. The laser is turned on by the finally obtained pulse width, and dots are printed.

LUT901 but is a table conversion ROM for gradation correction, 812 to the _{address', C 2, C 1,} C 0, 814 table switching signal of 812 and 813, 815 a video signal is input, VIDEO corrected from the output DATA is obtained. For example, LCHG to select PW1
When 143 is set to "0", the outputs of the binary counter 903 are all "0", and the correction table for PW1 in 901 is selected. Also
C ₀ , C ₁ , C ₂ are switched according to the color signal to be output. For example, when C ₀ , C ₁ , C ₂ = “0,0,0”, yellow output, “0,1,0”
Magenta output, “1,0,0” cyan output, “1,1,0”
Black output when. This is the same as in the above-described masking. That is, the gradation correction characteristic is switched for each color image to be printed. This compensates for differences in gradation characteristics due to differences in image reproduction characteristics due to the colors of the laser beam printer. Also the combination of C ₂ and C _0, C ₁ it is possible to perform a more extensive gradation complementarity. For example, the gradation conversion characteristics of each color can be switched according to the type of the input image. Next, when the LCHG143 is set to “1” to select PW1, the binary counter 903 outputs the line synchronization signal. Count and outputs “1” → “2” → “1” → “2” →... To address 814 of the LUT. In this way, the gradation complementarity table is switched for each line, thereby further improving the gradation.

This will be described in detail with reference to FIG. 54 and subsequent figures. The curve A in FIG. 9A selects, for example, PW2 and sets the input data to “FF”, that is,
7 is a characteristic curve of input data versus print density when changing from “white” to “0”, that is, “black”. Normally, the characteristic is desirably K. Therefore, B, which is the inverse characteristic of A, is set in the gradation complementarity table. FIG. 9B shows the gray level complementarity characteristics A and B for each line when PW1 is selected.
By making the pulse width in the main scanning direction (laser scanning direction) variable with the above-mentioned triangular wave, and having two gradations in the sub-scanning direction (image feeding direction) as shown in the figure, further improving the gradation characteristics Let it. That is, in the portion where the density change is steep, the characteristic A
Becomes dominant and steep reproducibility is achieved, and gentle gradation is reproduced by the characteristic B. Therefore, even when PW2 is selected as described above, a certain degree of gradation is ensured at high resolution, and when PW1 is selected, very excellent gradation is ensured. The selection of PW1 and PW2 is exemplified in the present invention as switching between a high resolution line number image forming output and a high gradation line number image forming output. That is, as will be described later, the circuit shown in FIG. 73 (A) performs 400 dpi printing as a high resolution line frequency image forming output,
It is exemplified that a 200 dpi process is performed as a high gradation line frequency image forming output.

The video signal converted into the pulse width as described above is applied to the laser driver 711L via the line 224, and modulates the laser light LB.

The signals C ₀ , C ₁ , C ₂ , and LON in FIG. 74A are output from a control circuit (not shown) in the printer controller 700 in FIG.

Here, consider a case in which processing is performed on a color document including a character area. Returning to the overall circuit diagram of FIG. 2, the processing procedure will be described. That is, the input character and halftone mixed image data pass through an input circuit (A block), and one of them receives a LOG conversion (C) for obtaining an appropriate image.
The other is input to a color complementarity (D) circuit, and the other is input to a detection circuit (I) for separating a character and a halftone area, and a detection signal MjAR corresponding to the character area and the halftone area.
(124) to SCRN (127) are output. Among these detection signals, MjAR (124) is a signal indicating a character portion, and based on this signal, the character image complementing circuit E generates a resolution switching signal LCHG (FIGS. 140 and 21). Things already mentioned. As shown in FIG. 2, the LCHG 140 is sent to the printer unit in parallel with the multi-valued video signals 113, 114, 115, 116 and 138. As described above, the character unit has a high resolution output (400 dpi), and the halftone unit has a high gradation. Output (200dpi)
Switching signal.

 Subsequent processing is performed as described above.

(Image forming operation)

Now, the laser beam LB modulated according to the image output data 816 is rotated by the polygon mirror 712 rotating at high speed.
High-speed scanning is performed horizontally at the width of the arrow AB, and the f / θ lens 713 is scanned.
And an image on the surface of the photosensitive drum 715 through the mirror 714,
Dot exposure corresponding to image data is performed. One horizontal scan of the laser light corresponds to one horizontal scan of the original image, and in this embodiment, corresponds to a width of 1/16 mm in the feed direction (sub-scan direction).

On the other hand, since the photosensitive drum 715 is rotating at a constant speed in the direction of arrow L in the figure, the above-described scanning of the laser beam is performed in the main scanning direction of the drum, and the photosensitive drum 715 is scanned in the sub-scanning direction of the drum. Since the rotation is performed at a constant speed, the planar image is sequentially exposed to form a latent image. From the uniform charging by the charger 717 prior to the exposure, the above-described exposure → and the toner development by the developing sleeve 731 form toner development. For example, if development is performed using yellow toner on the developing sleeve 731Y in response to the first document exposure scan in the color reader, a toner image corresponding to the yellow component of the document 3 is formed on the photosensitive drum 715.

Next, the photosensitive drum 715 is placed on the paper sheet 754 having the leading end carried by the gripper 751 and wound around the transfer drum 716.
A yellow toner image is transferred and formed by a transfer charger 729 provided at a contact point between the toner image and the transfer drum 716. The same process is repeated for the M (magenta), C (cyan), and BK (black) images, and each toner image is superimposed on the sheet 754 to form a full-color image using four-color toner. You.

Thereafter, the transfer paper 791 is peeled off from the transfer drum 716 by the movable peeling claw 750 shown in FIG. 1, is guided to the image fixing unit 743 by the conveyor belt 742, and is heated to the fixing unit 743 by the hot-press rollers 744 and 74.
5, the toner image on the transfer paper 791 is fused and fixed.

In this embodiment, the driver for printing drives the color laser beam printer.
The present invention can be applied to a thermal transfer type color printer or a color image copying apparatus that obtains a color image such as an ink jet color as long as it has a function of switching the resolution according to the image.

In this embodiment, means for performing high-resolution processing on a character image to be combined, means for performing high-gradation processing on a color image to be combined, and a character part to be combined with a color image part to be combined By providing means for prioritizing high-resolution processing in an area where the overlapping occurs, it is possible to obtain an optimal combined image suitable for the properties of the combined image.

Here, in this embodiment, 400 dpi printing is used as the high-resolution processing, and 200 dpi printing is used as the high gradation processing. However, the processing means is not limited to this. That is, the resolution can be freely set. Further, not only two-stage switching but also multi-stage switching such as three-stage switching may be employed.

As described above, according to the present embodiment, high resolution processing is performed when the composite image is a character, and high gradation processing is performed when the composite image is a color image.
Since high-resolution processing is performed on a portion where types of composite images overlap, a high-quality and high-definition composite image that is not affected by a reflection original can be obtained.

<Effects of the Invention> According to the present invention, when a binary image such as a character and another multi-valued color image are combined and output, a high-resolution line-number image forming output based on the binary image before the combination is performed. Since the switching is performed between the high gradation image forming output and the high gradation image forming output, a method of switching between the high resolution line image forming output and the high gradation line image forming output by judging the attribute of the image after combining the two is adopted. In comparison, it is possible to switch between the two outputs with high accuracy, especially in the low density area of the binary image. Further, the attribute of the image is also determined for the multi-valued color image, and based on the determination, switching between the high resolution line number image forming output and the high gradation line number image forming output is performed. The processing can be switched with high accuracy in accordance with, and the quality of the output composite image can be improved.

Further, since the composition is performed based on the density information, the composition can be performed well.

[Brief description of the drawings]

1 is an overall view of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a circuit diagram of image processing according to an embodiment of the present invention, FIG. 3 is a diagram showing a color reading sensor and a driving pulse, 4 is a circuit diagram for generating ODRV118a and EDRV119a, FIG. 5 is a diagram for explaining a black correction operation, FIG. 6 is a circuit diagram for shading correction, FIG. 7 is a color conversion block diagram, and FIG. FIG. 9 is a block diagram of a color conversion circuit, FIG. 10 is a diagram showing a specific example of color conversion, FIG. 11 is a diagram for explaining logarithmic conversion, FIG. 12 is a circuit diagram of a color correction circuit, FIG. FIG. 13 is a diagram showing an unnecessary transmission area of the filter, FIG. 14 is a diagram showing an unnecessary absorption component of the filter, FIG. 15 is a circuit diagram of a character image area separation circuit, and FIG. 16 explains a concept of contour regeneration. Fig. 17, Fig. 17 illustrates the concept of contour regeneration, Fig. 18 is a circuit diagram for contour regeneration, Fig. 19 Is a contour regenerating circuit diagram, FIG. 20 is a timing chart of EN1 and EN2, FIG. 21 is a block diagram of a character image correcting unit, FIG. 22 is an explanatory diagram of addition / subtraction processing, FIG. 23 is a switching signal generating circuit diagram, FIG. 24 is a circuit diagram of the remaining color removal processing, FIG. 25 is a diagram for explaining the remaining color removal process, addition and subtraction processing, etc. FIG. 26 is a diagram showing edge enhancement, FIG. 27 is a diagram showing smoothing, FIG. Is a diagram for explaining processing and modification processing by a binary signal, FIG. 29 is a diagram showing characters and image synthesis, FIG. 30 is a block diagram of an image editing circuit, FIG. 31 is a diagram showing texture processing, FIG. The figure is a circuit diagram of texture processing, FIG. 33 is a circuit diagram of mosaic, scaling, taper processing, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram for explaining mosaic processing, etc., and FIG. 36 is a line. FIG. 37 is a circuit diagram of a memory address control unit. Explanation diagram, Fig. 38 shows address, Fig. 39 shows specific example of mask, Fig. 40 is circuit diagram of address counter, Fig. 41 is timing chart of enlargement / reduction, Fig. 42 is enlargement FIG. 43 is an explanatory diagram of a binarization circuit, FIG. 44 is a timing chart of an address counter, FIG. 45 is a diagram showing a specific example of bit map memory writing, and FIG. FIG. 47 is a diagram showing a specific example of characters and image synthesis, FIG. 47 is a circuit diagram of distribution switching, FIG. 48 is a diagram showing a specific example of a nonlinear mask, FIG. 49 is a circuit diagram of a region signal generation circuit, and FIG. FIG. 51 shows an area designation by a digitizer, FIG. 51 is an interface circuit diagram with an external device, FIG. 52 is a truth table of a selector, FIG. 53 is a diagram showing an example of a rectangular area and a non-rectangular area, and FIG. 54. Is an external view of the operation unit, FIG. 55 is a diagram for explaining the procedure of the color conversion operation, and FIG. FIG. 57 is a diagram illustrating a procedure for specifying a trimming area, FIG. 57 is a diagram illustrating an algorithm for specifying a circular area, and FIG. 59 is a diagram illustrating an algorithm for specifying a circular area and an R rectangle. Diagram showing the algorithm, FIG. 60 is an explanatory diagram of the operation procedure of character composition, FIG. 61 is an explanatory diagram of the operation procedure of character composition, FIG. 62 is an explanatory diagram of the operation procedure of character composition, FIG. 63 is a texture process FIG. 64 is a diagram illustrating the procedure of the mosaic processing, FIG. 65 is a diagram illustrating the procedure of the * mode operation, FIG. 66 is a diagram illustrating the procedure of the program memory operation, FIG. Figure illustrates the procedure for operating the program memory, Figure 68 illustrates the procedure for operating the program memory, Figure 69 illustrates the algorithm for registering the program memory, and Figure 70 illustrates the operation after recalling the program memory. Shows the algorithm, the 71 figure illustrates the the format of the recording table, the 72 figure is a diagram showing an image processed and edited. FIG. 73 is a diagram showing a part of a driver of a color laser beam printer and a timing chart, FIG. 74 is a diagram showing contents of a gradation correction table, and FIG. 75 is a perspective view showing an appearance of the laser beam printer. .

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI B41J 29/38 B41J 3/12 G (72) Inventor Mitsuru Kurita 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (56) References JP-A-59-170864 (JP, A) JP-A-62-277855 (JP, A) JP-A-63-124674 (JP, A) JP-A-62-116959 (JP, A) JP-A-57-102364 (JP, A) JP-A-63-197173 (JP, A) JP-A-60-172885 (JP, A)

Claims (4)

(57) [Claims] 1. A superimposition / synthesis output unit for superimposing and synthesizing a binary image and another multi-valued color image in accordance with a given instruction, and a binary image before being synthesized by the superimposition / synthesis output unit. Control means for controlling the superimposing and synthesizing output means so as to switch between a high-resolution line number image forming output and a high-gradation line number image forming output for the image after synthesis based on Image processing device. 2. The image processing apparatus according to claim 1, wherein the control unit is configured to output a high-resolution line to an area of the binary image in the image output by the synthesis output unit based on the binary image before being synthesized by the superimposition synthesis output unit. A number image is formed and output, and a line number image for high gradation is formed and output in the area of the other multi-valued color image. A line for high resolution is formed in an area where the binary image and the other multi-valued color image overlap. 2. The image processing apparatus according to claim 1, wherein the control unit is a control unit for forming and outputting several images. 3. The image processing apparatus according to claim 2, further comprising: a judging means for judging an image attribute of said another multi-valued color image to be synthesized by said synthesizing output means. The image processing apparatus according to claim 1, wherein: 4. An image processing apparatus according to claim 1, wherein said composite output means is means for converting said other multi-valued color into density information and then compositing with said binary image.