JPH02295355A - Picture processor - Google Patents

Abstract

PURPOSE:To discriminate a character area and a picture area at real time by providing means to calculate average values in the plural masks with difference sizes of an emphasized picture signal, to compare the average values with each other and to decide whether the area is a picture part or not. CONSTITUTION:A means to emphasize a high frequency component with a space frequency to an input picture signal, plural average value calculating means to respectively calculate the average values in the plural matrixes in the different sizes of the emphasized picture signal, and the means to decide it by comparing the plural average values with each other whether the area is the picture part or not are provided. Thus, it can be discriminated to the inputted picture data by simple circuit configuration whether the area is the picture part or a character part. Then, processing to simultaneously reproduce a smooth picture and a sharp character can be executed in real time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, such as a digital color copying machine,
Related to color image scanners, color printers, etc.

[Conventional technology]

Conventionally, for example, in a digital color copying machine, a document is irradiated with a halogen lamp or the like, and the reflected light is converted into, for example, R (red) by an optical means such as an optical filter or a prism.
．． Decomposes into G (green) and B (blue) and converts them into CO
After performing photoelectric conversion using a charge-coupled device such as D, converting it into a digital signal, and performing predetermined processing, an image is formed using a recording device such as a laser beam printer, liquid crystal printer, thermal printer, or inkjet printer. There is.

There has been a high demand for such digital color copying machines to produce smooth images and sharp characters, lines, etc., and various companies have been conducting various studies.

[Problem to be solved by the invention]

However, in the area gradation method, which secures the gradation of the image by dot area, the gradation of the output image and the high resolution are contradictory, and different processing is performed for the image part and the character part. is required. Many methods have been announced so far, but most of them involve complex processing using software, and methods that perform real-time processing are
The circuit size made it extremely expensive, making it impossible to use it in products.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a low-cost image processing device with a small circuit scale, which discriminates character areas and image areas in real time, and performs different processing for each area. With the goal.

[Means and operations for solving the problems] In order to solve the above problems, the image processing device of the present invention includes means for emphasizing high frequency components at a spatial frequency with respect to an input image signal, and a size of the emphasized image signal. The present invention is characterized by comprising a plurality of average value calculation means for calculating average values within a plurality of masks having different values, and a means for determining whether or not it is an image portion by comparing the plurality of average values.

゛(Re′) 〔Example〕 Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows an example of a schematic internal configuration of a digital color image processing system according to the present invention. As shown in the figure, this system includes a digital color image reading device (hereinafter referred to as a color reader) 1 at the top and a digital color image printing device (hereinafter referred to as a color printer) 2 at the bottom. This color reader 1 includes color separation means and C
A light amount conversion element such as an OD reads the color image information of the original for each color and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots.

First, an overview of the color reader I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a rotor for condensing the reflected light image from the document exposed and scanned by the halogen exposure lamp 10 and transmitting the image to the 1-magnification full-power color sensor 6. It is a door array lens, 5, 6,
7. 10 as a document scanning unit 1l integrally performs exposure scanning in the direction of arrow A1.

The color separation image signals read every line without exposure scanning are amplified to a predetermined voltage by the sensor output signal amplification circuit 7, and then inputted to a video processing unit to be described later via a signal line 501, where they are processed. . Details will be described later. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-strength color sensor 6, and all necessary drive pulses are generated within the video processing unit l2. 8
, 9 are a white plate and a black plate for white level correction and black level correction of image signals, which will be described later, and when irradiated with a halogen exposure lamp 10, signals of predetermined densities are produced, respectively.
You can get the level, white level correction of the video signal,
Used for black level correction. 13 is a control unit having a microcomputer, which is connected to the bus 50
8, the display on the operation panel 20, key manual control, and control of the video processing unit 12; position sensors Sl, S2 detect the position of the original scanning unit 11 via signal lines 509, 510; Stepping motor drive circuit control that pulse-drives the stepping motor l4 to move the halogen exposure lamp 10 via the signal line 504, ON/OFF control of the halogen exposure lamp 10 by the exposure lamp driver via the signal line 504, light amount control, and control via the signal line 505. It controls all parts of the color reader part 1, such as the digitizer l6, internal keys, and display unit. The color image signal read by the above-mentioned exposure scanning unit 11 during original exposure scanning is sent to the video processing unit l via the amplifier circuit 7 and the signal line 501.
2, undergoes various processes to be described later within this unit 12, and is sent to the printer part 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color reader 1 into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. do.

In addition, 711 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

726 is a developer unit that develops the electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure; 731Y, 731M, 731C, and 731Bk are developing sleeves that directly develop the photosensitive drum 715;
0Y, 730M, 730C, and 730Bk hold spare toner (a toner hoverer), and 732 is a screw that transports the developer, and these sleeves 731Y~
73tBk,} A developing unit 726 is constituted by the inner hoppers 730Y to 7308k and the screw 732, and these members are arranged around the rotation axis P of the developing unit. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing device unit 72
6 is rotated around the axis P in the figure, and the developing sleeve 731M in the magenta developing device is disposed at a position in contact with the photoreceptor 715. Cyan and black development work in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 7l9 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is adjacent to this actuator plate 719. 725 is a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger. These members 71
9, 720, 725, 727, and 729 are arranged around the transfer roller 716.

On the other hand, 735 and 736 are paper feed cassettes that store paper (paper sheets), and 737 and 738 are cassettes 735 and 736.
paper feed rollers for feeding paper from 739, 740,
Reference numeral 741 denotes a timing roller that takes the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wrapped around the transfer drum 716 while the leading edge is carried by a gripper (to be described later), forming an image. Shift to the formation process.

Further, 550 is a drum rotation motor, and the photosensitive drum 7
15 and a transfer drum 716 are rotated in synchronization. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is a conveyor belt that is conveyed by the conveyor belt 742. The image fixing unit 743 is an image fixing unit that fixes the paper that has been received.

The image processing circuit according to the present invention will be described in detail with reference to FIG. 2 and subsequent figures. This circuit exposes a full-color original with an illumination source such as a halogen lamp or fluorescent lamp (not shown), captures a reflected color image with a color image sensor such as a CCD, and sends the obtained analog image signal to an A/D converter. A color image copying device that processes and processes the digitized full-color image signal and outputs it to a thermal transfer color printer, inkjet color printer, laser beam color printer, etc. (not shown) to obtain a color image, or a color image copying device that obtains a color image by processing the digitized full-color image signal It is applied to color image output devices that input color image signals from computers, other color image reading devices, color image transmitting devices, etc., perform processing such as compositing, and output them to the color printer mentioned above. be.

The document is first irradiated by an exposure lamp (not shown), and the reflected light is separated into colors for each image and read by a color reading sensor 500a, and amplified to a predetermined level by an amplifier circuit 501a. 533a is a COD driver that supplies a pulse signal for driving the color reading sensor, and the necessary pulse source is generated by a system control pulse generator 534a.

FIG. 3 shows the color reading sensor and drive pulses. Figure 3(a) shows the color reading sensor used in this example, which reads by dividing the main scanning direction into five (63
．． Assuming that 5 μm is one pixel (4 dots/inch (hereinafter referred to as dpi)), there are 1024 pixels, that is, 1 pixel is divided into three by G, B, and R in the main scanning direction as shown in the figure, so a total of 1024X3 = 3072 effective pixels. It has the number of pixels. On the other hand, each of the chips 58 to 62 is formed on the same ceramic substrate, and the chips 1, 3, . 5th (
58a, 60a, 62a) are on the same line LA,
The 2nd and 4th lines are 4 lines apart from LA (63.5 μm x 4 =
254 μm) on the line LB, and scans in the direction of the arrow AL when reading the document.

1, 3 out of each 5 CCDs. The fifth one is for the drive pulse group ODRV118a, and the second and fourth are for the EDRV119a.
are driven independently and synchronously.

OOIA, 002A, OR included in ODRVI18a
EOIA, EO2A, included in S and EDRVI19a,
ERS is a charge transfer clock and a charge reset pulse within each sensor, respectively; 1, 3. fifth and second
, and the fourth, and due to noise limitations, they are generated completely in synchronization so that there is no jitter with each other. For this reason,
These pulses are generated from a single reference oscillator source OSC 558a (FIG. 2).

Figure 4(a) shows ODRV118a and EDRV119a.
FIG. 4(b) is a timing chart of the circuit block that generates the pulse generator 534a of FIG. 2, which is included in the system control pulse generator 534a of FIG. Clock K obtained by dividing the original clock CLKO generated from a single OSC558a
0135a is a clock that generates reference signals SYNC2 and SYNC3 that determine the timing of generation of ODRV and EDRV, and SYNC2 and SYNC3 correspond to the set values of resettable counters 64a and 65a set by the signal line 22 connected to the CPU bus. The output timing is determined accordingly, and SYNC2 and SYNC3 are connected to the frequency divider 66a,
67a and drive pulse generators 68a, 69a
Initialize. In other words, the HS input to this block
Based on YNC118, all with one oscillation source OSC55
Since it is generated by the CLKO output from 8a and the divided clocks that are all generated synchronously, the ODR
Each pulse group of V118a and EDRV119a is obtained as a synchronized signal without any jitter, and it is possible to prevent signal disturbance due to interference between sensors.

Here, the sensor drive panores ODRV18a obtained in synchronization with each other are 1, 3. Fifth sensor 58a
, 60a, 62a, the EDRV 119a is supplied to the second and fourth sensors 59a, 61a, and each sensor 58a
, 59a, 60a, 61a, and 62a independently output video signals V1-V5 in synchronization with the drive pulse.
Independent amplifier circuit 50 for each channel shown in FIG.
1-1 to 501-5 to a predetermined voltage value and passed through the coaxial cable 101a to 0081 29 in FIG. 3(b).
At timing a, signals V1, V3, and V5 are sent out, and at timing EOS134a, signals V2 and V4 are sent out and input to the video image processing circuit.

The color image signal obtained by dividing the original input into the video image processing circuit into five parts is processed by the sample hold circuit S/H502a in three colors of G (green), B (blue), and R (red). separated into

Therefore, after S/H, signals are processed in 3×5=15 systems.

The analog color image signals sampled and held for each color R, G, and B by the S/H circuit 502a are as follows:
The next stage A/D conversion circuit 503a digitizes each channel from 1 to 5, and each channel from 1 to 5 is independently connected in parallel.
Output to the next stage.

Now, in this embodiment, as described above, 4 lines (63.
5 μm x 4 = 254 μm) in the sub-scanning direction, and the manuscript is read using five staggered sensors divided into five areas in the main scanning direction. , 3, and 5, the reading position is shifted. Therefore, in order to connect these lines correctly, a shift correction circuit 504a having memory for a plurality of lines corrects the shift.

Next, using FIG. 5(a), the black correction/white correction circuit 506
The black correction operation in a will be explained. As shown in FIG. 5(b), when the amount of light input to the sensor is small, the black level outputs of channels 1 to 5 vary greatly between chips and between pixels. If this is output as is and an image is output, streaks and unevenness will occur in the data portion of the image. Therefore, it is necessary to correct the output variation in the black portion, and this correction is performed using a circuit as shown in FIG. 5(a). Prior to the original reading operation, the original scanning unit is moved to the position of a black plate having uniform density that is placed in a non-image area at the tip of the original table, the halogen is turned on, and a black level image signal is input to this circuit.

Regarding the blue signal BIN, one line of this image data should be stored in the black level RAM78a.
Select A with the selector 82a (■), close the gate 80a (■), and open 81a. That is, the data line is 151a
→Connected to 152a-+153a, while RAM78a
The address 155a is initialized with HSYN,
The output 154a of the address counter 84a that counts VCLK should be input.■ is output to the selector 83a, and the black level signal for one line is R A M 7
8a (hereinafter referred to as black reference value import mode).

When reading an image, the RAM 78a is in a data read mode, and each line and l pixels are read out and input to the B input of the subtracter 79a via the data line 153a→157a. That is, at this time, the gate 81a is closed (
■), 80a opens (■). In addition, the selector 86a is
This becomes the output. Therefore, the black correction circuit output 1 56a is BI N (i) −DK (i)”Bout(
i) (referred to as black correction mode). Similarly, green GINI and red RIN are 77aG, 77a
Similar control is performed by R.

In addition, the control lines of each selector gate for this control
, ■, ■, ■ are performed under CPU control by latch 85a assigned as I/O of CPU 22 (FIG. 2). Note that the selectors 82a, 83a, 86a are
RAM 7 by the CPU 22 by selecting
8a becomes accessible.

Next, white level correction (shading correction) in the black correction/white correction circuit 506a will be explained with reference to FIG. White level correction corrects variations in sensitivity of the illumination system, optical system, and sensor based on white data obtained when the document scanning unit is moved to the position of a uniform white plate and irradiated. The basic circuit configuration is shown in FIG. 6(a). The basic circuit configuration is shown in Figure 5 (
This is the same as a), but the only difference is that the black correction uses a subtracter 79a, whereas the white correction uses a multiplier 79'a, so a description of the same parts will be omitted.

CCD (500a
) is at the reading position (home position) of a uniform white plate, that is, before a copying operation or a reading operation, an exposure lamp (not shown) is turned on and image data of a uniform white level is stored in the correction RAM 78'a for one line. Store. For example, if it has a width in the A4 longitudinal direction in the main scanning direction, 16 pej! /mm = 47
52 pixels, or at least the RAM capacity is 4752
Bytes, and as shown in FIG. 6(b), if the i-th pixel white board data Wi (i=1 to 4752), the RAM 78
As shown in FIG. 6(c), 'a' stores data for the white plate for each pixel.

On the other hand, for Wi, the read value Di of the normal image of the i-th pixel is corrected data Do=DiXFFH/Wi
It should be. Therefore, from the CPU 22, the latch 85
Gate 80'a for 'a■',■',■',■'
, 81' a, and selector 82' a,
83'a and 86'a are output so that B is selected, and RAM78'a is made accessible to the CPU.

Next, in the procedure shown in FIG. 6(d), the CPU 22 sequentially calculates F F H / Wo for the first pixel WO, F F / W 1 . . . for W H, and performs data replacement. Once the blue component of the color component image is completed (Fig. 6(d) Step B), the green component (Step B) is
pG), red component (StepR), and thereafter,
Do=DiXFF for the input original image data Di
Gate 80'a is open so that H/Wi is output (■
'), 81' a is closed (■'), selector 83' a,
A is selected for 86'a, and coefficient data FFl4/Wi read from RAM 78'a is connected to signal line 153a.
→1 It passes through 57a, is multiplied by the original image data 151a input from one side, and is output.

As described above, the black level and white level are corrected based on various factors such as the black level sensitivity of the image input system, the dark current variation of the CCD, the sensitivity variation between each sensor, the optical system light amount variation, and the white level sensitivity. Image data B uniformly corrected for each color, both white and black, in the scanning direction.

U. 101, GolJ, 102, Rou1l0
3 is obtained. The white and black level-corrected color separation image data obtained here are processed by detecting pixels on the image having a specific color density or a specific color ratio according to instructions from an operation unit (not shown). The data is sent to a color conversion circuit B which converts the data into another color density or color ratio specified by the unit.

<Color Conversion> FIG. 7 is a block diagram of color conversion (gradation color conversion and density color conversion). The circuit in Figure 7 is an 8-bit color separation signal RIN.
+ G IN + BIN (11) to 3b), a color detection unit 5b that determines an arbitrary color set in the register 6b by the CPU 20, and an area signal Ar4b that performs color detection and color conversion for a plurality of locations. , a line memory 10b that performs processing to spread a signal indicating that the color is a specific color (hereinafter referred to as a hit signal) outputted by the color detection section in the main scanning and sub-scanning directions (in the example of FIG. 7, only the sub-scanning direction).
~llb, OR gate 12b, expanded hit signal 3
4b and non-rectangular signals (including rectangular) Color conversion enable signal 33b generated from BHi 27b, enable signal 33b and input color separation data (RINI G INr B
tpt Ib to 3b), line memories 13b to 16b for synchronizing area signal Ar4, and delay circuit 1
7b to 20b, enable signal 33b1 Synchronized color separation data (R IN + G IN + B
IN' 2lb to 23b), area signal Ar' 24
b and the CPU 20, the color conversion unit 25b performs color conversion based on the color data after color conversion set in the register 26b.1 Color separation data (R out
+ G OIJT I B OUT 28b~30
b), ROUT + . GOUT r Hit signal H output in synchronization with BOtJT. Consists of UT3lb.

Next, we will outline the algorithms for gradation color determination and gradation color conversion. Here, gradation color judgment and gradation color conversion mean color judgment and conversion of the same hue in order to save the density value and perform color conversion for colors of the same hue when performing color judgment and color conversion. It is to perform a transformation.

It is known that for the same color (certain hue), for example, a red signal R1, a green signal G1, and a blue signal B have the same ratio.

Therefore, data M1 of one of the colors to be converted (maximum value color, hereinafter referred to as principal color) is selected, and the ratio between it and the data of the other two colors is determined. For example, and the input data R+
, G+, B+, M1 X γ1 ≦R
．． ≦M,

Furthermore, the data after color conversion (R21 G21 B2) is also
Data M of the main color (in this case, the maximum value color) within that data
2 and the data of the other two colors.

For example, when G2 is the main color, M 2 = G 2, and for the main color M1 of input data, if the data is a color conversion pixel, if it is not a color conversion pixel, then (RI.GI , BI).

As a result, all parts of the same hue with gradation are detected,
It becomes possible to output color conversion data according to gradation.

FIG. 8 is a block diagram showing an example of a color determination circuit. This part is a part that detects pixels to be color-converted.

In this figure, 50b is RIN bL GIN
b2, B, N Smoothing section that smooths the input data of b3, 5lb is one of the outputs of the smoothing section (
Selectors 52bR, 52bG, 52b for selecting the main color)
8 is the output of selector 5lb and fixed value RO+co+B
Selector for selecting one of o, 54bR, 54bo, 5
4b8 is an OR gate, 63b, 64b R, . 6
4b, , 64b8 are area signals ArlO, respectively.
, selector 5lb, 52bR, 52 based on Ar20
b,, selector for setting the select signal to 52bB, 56bR, 56b,, 56b8 and 57bR,
57b, 57b are multipliers that calculate the respective upper and lower limits.

In addition, the upper limit ratio registers 58b R, 58b o, 58b , and the lower limit ratio registers 59b R, 59b 0, 59 set by the CPU 20
b 8 can each set data for color detection for a plurality of areas based on the area signal Ar 30.

Here, ArlO, Ar20, and Ar30 are signals created based on Ar4b in Fig. 7, and each has the required number of stages of D.
Contains F/F. Also, 6lb is an AND gate, 62
b is an OR gate, and 67b is a register.

Next, we will explain the actual movement. R,N bl,G,N
The selector 5lb selects one of the data R'G'B' obtained by smoothing b2, B, and Nb3, respectively, using the select signal S1 set by the CPU 20, and the main color data is selected. Here, CPU2
0 indicates different data A in registers 65b and 66b.
, B are set, and the selector 63b selects either A or B according to the ArlO signal and inputs it as the S signal to the selector 5lb.

In this way, prepare two registers, 65b and 66b,
By inputting different data to A and H of the selector 63b and selecting one of them using the area signal ArlO, separate color detection can be performed for a plurality of areas. This area signal ArlO may be a signal for not only a rectangular area but also a non-rectangular area.

In the next selectors 52bR, 52b, 52b8, CP
R set by U20. , Go, Bo or the main color data selected by the selector 5lb is selected by a select signal generated by the outputs 53ba to 53bc of the decoder 53b and the fixed color mode signal S2. Note that the selectors 64bR, 64b, and 64b8 can detect different colors in a plurality of areas by selecting either A or B according to the area signal Ar20, as in the case of the selector 63b. ing. Here, Ro, Go, Bo are conventional color conversion (
(fixed color mode) and the main color in gradation color determination, and the main color data is selected when the main color is a color other than the main color in gradation color conversion.

Note that the operator can freely select between fixed color determination and gradation color determination from the operation section. Alternatively, it is also possible to change it by software using color data (color data before color conversion) input from an input device such as a digitizer.

These selectors 52bR, 52b, 52b
From the output of B, upper limit ratio registers 58bR, 58bG, 58b8, and lower limit ratio registers 59bR, 59b, 59bB set by the CPU 20, the upper and lower limit values of R'G'B' are determined by the multipliers 56bR, 56b, respectively. ,, 56bB and 57bR, 5
7bo and 57b8, and set as upper and lower limit values in window comparators 60bR, 60b0, and 60b8.

Window comparator 60bR, 60bG, 60bB
It is determined by the AND game 6lb whether the data of the main color is within a certain range and the two colors other than the main color are within a certain range. The register 67b can set "BI" regardless of the judgment signal by the enable signal 68b of the judgment section. In this case, the color to be converted exists in the part where "l" is set.

The above configuration enables fixed color determination or gradation color determination for a plurality of areas.

FIG. 9 is a block diagram of an example of a color conversion circuit.

? The circuit selects the color-converted signal or the original signal based on the output 7b of the color determining section 5b.

In FIG. 9, the color conversion unit 25b includes a selector lllb, registers 112bR, 112bR, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , .
ll2bo,, 112bB, 112b8,
, ll2b8■, multiplier 113bR, ll3b,,
113bB, selector l14bR, 114bo, 1
14b8, selector 115bR, l15b0, II5b
8, AND gate 32b, Fig. 7 area signal Ar 2
Ar50, Ar60, Ar70 generated based on 4
The data set by the CPU 20 is selected by the selector l.
llb, multiplier 113bR, 113bc, 113b
B, selector 114bR, 114b,, 114b8
Selector l1.7b, 112bR,1 to set to
12b,, 112b8, l16bR, 116bo
, l16b8, and a delay circuit 118b.

Next, we will explain the actual movement.

The selector 11lb receives input signals R, N2lb, G
, N' 22b, B , 1 of N' 23b
One (main color)? The selection is made according to the selection signal S5. Here, the signal S5 indicates that the area signal Ar40 switches the selector l17b to A, for the two data set by the CPU20.
This occurs by selecting either B. In this way, color conversion processing for multiple areas becomes possible.

The signal selected by selector lllb is sent to multiplier 113.
Multiplication with the register value set by the CPU 20 is performed in bR, 113bo, and 113b8.

Here again, the area signal Ar50 has two register values 112
bR, @112bR2. 112b,, -112
By selecting b, 2, 112bB, .multidot.112b8■ by selectors 112bR, 112b, . . . 112bB, different color conversion processing can be performed for a plurality of areas.

Next selectors l14bR, 114bo, 114
In b8, the multiplication result and the two fixed values set by the CPU 20 Ro'*Ro'Go'aGo' Bo
'6BO, one of the fixed values C) selected by the selectors 116bR, 116bo, and 116bB by the area signal Ar70 is selected by the mode signal S6. Is this also a mode? The signal S6 is selected by the area signal Ar60 in the same manner as S5.

Finally, selector 115bR, 115b, 115bB selects RINGIN I using select signal S8.
BIN (RIN I GIN I BIN delayed and timing adjusted) and selector 114bR, 11
4b,, 1I4b8 is selected, and R
oUT, Gol. It is output as IT and BooT. Also hit signal H. UT is also R. U■, Go. J■. BOU
■Output in synchronization with.

Here, the selector signal SR is the ANDed result of the color determination result 34b and the color conversion enable signal BHi34b, which is delayed. If a non-rectangular enable signal such as the dotted line in FIG. 10 is input as the BHi signal, color conversion processing can be performed on a non-rectangular area. In this case, the area signal is an area like the one-dot chain line, that is, the top left (Figure 10a), the top right (B) on the right, the bottom left (C in Figure 10), and the bottom left determined from the dotted lines. (Fig. 10, d). Also, non-rectangular area belief? BHi is input from an input device such as a digitizer.

When performing color conversion using this non-rectangular enable signal,
Since the enabled area can be specified along the boundary of the area to be converted, the threshold for color detection can be expanded compared to conventional color conversion using rectangles. Therefore, the detection ability is further improved, and an output image subjected to gradation color conversion with high accuracy can be obtained.

From the above, color conversion with brightness according to the main color of the color judgment unit 5b (for example, when converting red to blue, light red is converted to light blue and dark red is converted to dark blue) or fixed value color conversion You can freely perform any of the following for multiple areas.

Furthermore, as will be described later, the hit signal H. Mosaic processing based on U■ only for specific color areas (non-rectangular or rectangular)
Texturing processing, trimming processing, masking processing, etc. can be performed.

Then, as shown in FIG. 2, the output 103 of the color conversion circuit B,
104 and 105 are a logarithmic conversion circuit C for converting image data proportional to reflectance into density data; External device interface M for communicating data between the system and external devices via cables 135, 136, 137
will be sent to.

Next, the color image data proportional to the input light amount is
The signal is input to a logarithmic conversion circuit C (FIG. 2) which performs processing to match the luminosity characteristics of the human eye.

Here, white = 00M and black = FFH are converted as much as possible, and the image sources input to the image reading sensor are, for example, a normal reflective original, a transparent original such as a film projector, and even the same transparent original as a negative film or positive. Since the input gamma characteristics differ depending on the film or film sensitivity and exposure conditions,
As shown in (b), there are a plurality of LUTs (look-up tables) for logarithmic conversion, which are used depending on the purpose. Switching is done using signal line 12 go, j! gl,
1 g2, and as the I/O port of the CPU 22, it is performed by inputting instructions from the operation unit, etc. (Figure 2)
. Here, the data output for each B, G, and R corresponds to the density value of the output image, and B (blue)
, G (green), R (red) signals, Y (yellow) . M (magenta), C (cyan)
The image data after this corresponds to the amount of toner.
Correspond to yellow, magenta, and cyan.

Next, the color correction circuit D performs color correction as described below on each color component image data from the original image obtained by logarithmic conversion, that is, yellow component, magenta component, and cyan component. As shown in Fig. 13, the spectral characteristics of the color separation filters arranged for each pixel in the color reading sensor have unnecessary transmission areas such as the shaded areas, and on the other hand, for example, the color transferred to the transfer paper Toner (Y, M, C)
It is also well known that the absorbent components have unnecessary absorption components as shown in FIG. 14. Therefore, each color component image data Yi, Mi,
Masking correction is well known in which color correction is performed by calculating a linear equation for each color for Ci. Furthermore, by Yi, Mi, Ci, Min (Yi, Mi, Ci) (Yi, M
(minimum value of i, Ci), set this as black and then add black toner (smearing);
An undercolor removal (UCR) operation is also performed to reduce the amount of each coloring material added depending on the added black component. In Figure 12(a),
The circuit configuration of a color correction circuit D that performs masking, smearing, and UCR is shown. The characteristics of this configuration are: ■ It has two masking matrices, and can be switched at high speed with one signal line "l/0". ■ One signal line "I" with and without UCR /O" can be switched at high speed. (2) It has two circuits for determining the amount of smear, and can be switched at high speed with "l/0."

First, prior to image reading, a desired first matrix coefficient M1, a desired second matrix coefficient M1, a desired second matrix coefficient M1, a desired first matrix coefficient M1, a desired second matrix coefficient M1, a desired second matrix coefficient M1, a desired first matrix coefficient M1, a desired second matrix coefficient M1, a desired first matrix coefficient M1, a desired second matrix coefficient M1, a desired first matrix coefficient M1, a desired second matrix coefficient M1, a desired first matrix coefficient M1, a desired second matrix coefficient, etc. RM 2 is set via the bus connected to the CPU 22. In this example, M1 is stored in registers 87d to 95d, and M2 is stored in registers 96d to l.
It is set to 04d.

Also, llld~122d, 135d, 131
d and 136d are selectors, which select A when the S terminal is "1" and select B when the S terminal is "0". Therefore, when selecting matrix M, the switching signal MARE
When A364="1" and matrix M2 is selected "
0”.

Further, 123d is a selector, and a selection signal C O +
C, (366d), 367d), outputs a, b, and c are obtained based on the truth table of FIG. 12(b). Selection signal C. , C1 and C2 correspond to color signals to be output, for example Y. In the order of M, C, Bk (C
2. C.I. Co) = (0, 0.0), (
0, 0. 1), (0, 1. 0), (1,
0. 0), and further as a monochrome signal (D, 1.
1), a desired color-corrected color signal is obtained. Now (Co, CI, C2) = (0, 0.
0) and MAREA="1", selector 12
The outputs (a, b, c) of 3d have registers 87d
, 88d, 89d, therefore (aye, -b
Me, -Cc. ) is output. On the other hand, the input signal Yi,
Min (Yi, Mi, C
i) The black component signal 374d calculated as =k is 13
7d undergoes a linear transformation of Y=ax-b (a, b are constants), and B of subtractors 124d, 125d, 126d
entered into the input. In each subtractor 124d to 126d, Y=Yi-(ak-b),
M = M i - (ak - b),
C = C i - (ak - b) is calculated, and multipliers 127d, 128d, 128d, for masking operation are calculated via signal lines 377d, 378d, 379d.
129d.

Multipliers 127d, 128d, and 129d each have (a y+ , − b Ml
l − C c+ ), and the B input has the above-mentioned (Yi
- (ak-b), Mi - (ak-b), Ci
- (ak-b)) = (Yi, Mi, Ci
] is input, so as is clear from the figure, the output D0.1 has the condition of C2=0 ( Y o r M o
r C ) and Y. l. l1? iX (av+) +Mi
X (-bMt) +CiX (-Cc+) is obtained,
Yellow image data that has been subjected to masking color correction and undercolor removal processing is obtained. Similarly, MoU7 = YiX (-ay2) + MiX (-bMz)
+CiX(-CC2)C■ UT=Yix(-ay3)
+MiX (-bM3)+CiX (-CC3) is D. I
Output to JT. Color selection is controlled by the CPU 22 according to the table in FIG. 12(b) using (Co, C, , C2) according to the order of output to the color printer. Registers 105d to 107d and 108d to 110d are registers for monochrome image formation, and based on the same principle as the masking color correction described above, MONO=k, Yi+I
．． It is obtained by weighted addition for each color using H Mi + ml Ci.

Further, when outputting Bk, C2 (368) is input as a switching signal to the selector 131d, so that C2=11, so the signal undergoes a linear conversion such that Y=cx-d in the primary converter 133d, and is output from the selector 131d. Also, Bk
MJ110 is a black component signal output to the outline of a black character based on the output of a character image area separation circuit (2) to be described later. Color switching signal C.

CI*C2' 366 to 368 are set from the output port 501 connected to the CPU bus 22, and
AREA 364 is output from the area signal generation circuit 364.

The gate circuits 150d to 153d output a signal C when DHi="L" based on a non-rectangular area signal DHil22 read from a binary memory circuit (bitmap memory) L537, which will be described later. + CI + c2==“l, 1,
This is a circuit that controls so that data for a mono image is automatically output.

Character image area separation circuit Next, the character image area separation circuit I uses the read image data to determine whether the image data is a character or an image, and whether it is chromatic or achromatic. This is a circuit that determines whether The flow of the process will be explained using FIG. 15.

Red (R) 103, green (G) 104, and blue (
B) 105 is a minimum value detection circuit M, N(,R,
G, B) 101I and maximum value detection circuit Max (R
, G, B) is input to 102I. In each block, the maximum value and minimum value are selected from the three types of input luminance signals R, G, and B. The difference between the selected signals is determined by a subtraction circuit 104I.

The difference is large, that is, the input R, G, and B are evenly distributed.
If it is not, it is not a signal close to an achromatic color that indicates black and white, but a chromatic color that is biased toward some color.

Naturally, if this value is small, it means that the R, G, and B signals are at approximately the same level, and it can be seen that the signal is an achromatic signal and not a signal that is biased towards any color. This difference signal is output to the delay circuit Q as a gray signal GR124. In addition, this difference is calculated between the threshold value arbitrarily set in the register 111I by the CPU and the comparator 11.
2I, and the comparison result is sent to the gray judgment signal GRBil2.
6 and output to the delay circuit Q. These GR125
, GRB port 26 is phase-aligned with other signals in a delay circuit Q, and then input to a character image correction circuit E, which will be described later, and used as a processing determination signal.

The minimum value signal obtained by M, N (R, G, B) IOII is also input to the edge emphasis circuit 1031. The edge emphasis circuit performs the following calculation using the front and rear pixel data in the main scanning direction. Edge enhancement is performed.

DOUT: Image data Di after edge enhancement
: i-th pixel data Note that edge enhancement is not necessarily limited to the above method, and other known techniques may be used. The image signal edge-enhanced in the main scanning direction is then
Average value calculation within 5 and 3 x 3 windows is 5 x 5
Average 1091, 3x3 average 110I. Line memories 1051 to 108I are delay memories in the sub-scanning direction for performing averaging processing. The 5×5 average value calculated by the 5×5 average 1091 is then added to an offset value independently set in an offset section connected to CPUBUS (not shown) and adders 115I, 119I,
It is added at 1241. The added 5×5 average value is input to limiter 1 113I, limiter 2 1181, and limiter 3 1231. Each limiter is connected to a CPU bus (not shown), and is configured so that the limiter value can be set independently.
If the average value is greater than the set limiter value, the output will be clipped at the limiter value. The output signal from each limiter is
Comparator 1 1161, comparator 2 respectively
1211, input to comparator 3 126I. First, the comparator 1 ] 16I compares the output signal of the limiter 113T with the output from the 3×3 average 110I. Compared comparator l 1
The output of 16I is sent to a delay circuit 117I in order to match the phase with an output signal from a halftone area discrimination circuit 122I, which will be described later.
is input. This binarized signal is binarized using an average value to prevent distortion and skipping due to MTF at a certain density or higher, and the halftone dots of the halftone image can also be binarized. A 3×3 low-pass filter is used to cut high frequency components of the halftone image so that they are not detected. Next, the output signal of comparator 2 (121I) is
2 with through image data to detect high frequency components of the image
Valuation is being carried out. In the halftone dot area discrimination circuit 1 221, since the halftone image is composed of a collection of dots, the dots are detected from the direction of the edge, and the number of dots around the dots is counted. .

A detailed explanation of the halftone dot area discriminating circuit 1 22I will be omitted since it is not the gist of this patent.

The results determined by the halftone dot area discriminating circuit and the signal from the delay circuit 117 are used in an OR gate 1291.
After removing the erroneous judgment, the erroneous judgment removal circuit 1 301 removes the erroneous judgment and outputs it to the AND gate 132I.

This false judgment removal circuit 130I takes advantage of the characteristics that characters, etc. are thin and images have a wide area, and first narrows the image area of the binarized signal and removes isolated image areas. Take. Specifically, for the center pixel xij, the surrounding 1
When even one pixel other than the image exists within the mm square area, the central pixel is determined to be outside the image. ．． After removing the image area of the isolated point in this way, thickening processing is performed to restore the thin image area to its original size. Similarly, the halftone discrimination circuit 122
The output of I is directly input to the erroneous determination removal circuit 131r, where thinning processing and thickening processing are performed. Here, the mask size for the thinning process is the same as the mask size for the fattening process, or by making the mask size for the fattening process larger, the determination results when fattening are made to cross each other. Specifically, the false determination removal circuit 1301. 1311 and 17X
After thinning with a 17 pixel mask, further thinning is performed with a 5×5 mask, and then thickening processing is performed with a 34×34 pixel mask. The output signal SCRN signal 127 from the misjudgment removal circuit 1311 is a discrimination signal for smoothing only the halftone dot determination section in a character image correction circuit E, which will be described later, to prevent moiré in the read image.

Next, the output signal from the comparator 3 1261 must be processed to sharpen the characters in the subsequent stage (extracting the outline of the input image signal). As an extraction method, the output of the binarized converter 3 126I is thinned and thickened in 5 x 5 blocks, and the difference area between the fattened signal and the thinned signal is contoured. shall be. The contour signal extracted by such a method must match the phase with the mask signal output from the false judgment removal circuit 1301. After passing through the delay circuit 128I, the contour signal is determined as a mask signal and an image by an AND gate 132I. The contour signal in the part where the characters are printed is masked, and only the contour signal in the original character part is output. The output from AND gate 1321 is then output to contour regenerator 1 331.

<Contour regeneration section> The contour regeneration section 133I processes pixels that are not determined to be character contours to become character contours based on information of surrounding pixels, and as a result, converts MjArl24 into character image correction circuit E. and perform the processing described below.

Specifically, as shown in Figure 16, bold letters ((a) in the same figure)
, the character determination unit determines the dotted line part in (b) as a character and performs the processing described below.
Regarding C)), the character part becomes as shown in the dotted line part in FIG. 3(d), and if the processing described below is performed, it may become unsightly due to erroneous determination. In order to prevent this, processing is performed to treat parts that are not determined as characters based on surrounding information.

Specifically, by making the diagonal line part the character part, the character part becomes as shown in the dotted line part (e) in the same figure, which reduces misjudgments even for characters that are so thin that they are difficult to detect, leading to improved image quality. .

FIG. 17 is a diagram showing how surrounding information is used to regenerate a pixel of interest into a character portion.

(a) to (d) are 3 x 3 blocks, with the pixel of interest as the center, and both vertical, horizontal, and diagonal text portions (both SI and S2 are "l")
When , the pixel of interest is set as a character portion regardless of the information of the pixel of interest. On the other hand, (e) to (h) are 5 x 5 blocks, with one pixel centered around the pixel of interest, and both vertical, horizontal, and diagonal text parts (both Sl and S2 are "1") are of interest regardless of the information of the pixel of interest. The pixel is used as a character part. Like this 2
The structure of tiered blocks (multiple types of blocks) makes it possible to handle a wide range of errors.

FIGS. 18 and 19 are circuits for realizing the process shown in FIG. 17. The circuits in FIGS. 18 and 19 use line memories 164i-167i and (1') DF/F104i to 126i to obtain information around the pixel of interest.
, FIG. 17(a) to (h).

Figure 17 (
The information of S, , S2 in a) to (h) is extracted. Furthermore, 1 4 6 i = I 5 3 i is (a) ~ (h
) registers 1551 to 1551 corresponding to each process.
1621, enable and disable can be controlled independently.

AND circuits 146i to 153i and FIG. 17(a) to (
The correspondence relationship in h) is as follows.

Figure 20 C, Line l Mo'IJ 164i-167i
(7) This is a timing chart of WE (ENI) and RE (EN2). This means that ENI and EN2 appear at the same timing when the size is the same, or when it is enlarged (for example, 200% to 3
00%), W1 is written once in the thinned out 2 lines.

This expands the size of FIGS. 17(a) to (h).

This is because when enlarging, the information that comes in here comes as an image enlarged only in the sub-scanning direction, so by increasing the size of (a) to (h), processing can be done with the same size image even when enlarging. Is going.

Character Image Correction Circuit> The character image correction circuit E performs the following processing on black characters, color characters, halftone images, and halftone images, respectively, based on the determination signal generated by the character image area separation circuit I described above.

[Processing 1] Processing related to black characters (1-1) Signal Bk obtained by black-mark extraction as video
Using Mjll2 (1-2) Y, M, C data are multivalued achromatic chromaticity signals GR
125 If << performs subtraction according to the set value. On the other hand, Bk
The data is added according to the multi-valued achromatic chromaticity signal GR125 or the set value (1-3) Edge emphasis is performed (1-4) Black text is printed out at 400 lines (400 dpi) (1-5) Color Perform residual removal processing [Processing 2] Processing related to colored characters [2-1] Perform edge emphasis (2-23 Print out colored characters at 400 lines (400 dpi) [Processing 3] Processing related to halftone images [ 3-1] Smoothing to prevent moire (main scan 2
[Processing 4] Processing related to halftone images [4-1 3 Smoothing (two pixels each in the main scanning direction) or through can be selected.

Next, a circuit that performs the above processing will be explained.

FIG. 21 is a block diagram of the character image correction section E.

The circuit of FIG.
A selector 6e that selects Mj 112, an AND game that generates a signal that controls the selector; 6e' a block 16e that performs residual color removal processing, which will be described later; an AND gate 16e that generates an enable signal for the same processing; and a GR signal 12.
5 and I/. A multiplier 9e' that multiplies the set value 10e of the O port, a selector lie that selects the multiplication result 10e or the set value 7e of the I/O port, and a multiplier 15e that multiplies the output 13e of the selector 6e and the output 14e of lle.
. A delay circuit 32e for synchronization of signals, a selector 42e for selecting the result of edge emphasis or a result of smoothing, a delay circuit 36e and an OR gate 39e for synchronization of control signals of the selector, AND
Gate 41e, 400 lines (dpi) for character determination section
Inverter circuit 4 for outputting a signal (“L” output)
4e, an AND circuit 46e, an OR circuit 48e, and a delay circuit 43e for synchronizing the video output 113 and the LCHG 49e. Also, character image correction section E
is connected to the CPU bus 22 via the I/O port le.

Below is [1] Color residual removal processing that removes the color signal remaining around the edge of the black text area, and a certain percentage is subtracted from the Y, M, and C data of the black text area determination section, and a certain percentage is subtracted from the Bk data. [2] Edge enhancement for the text part, smoothing for the halftone judgment part, and part where through data is selected for other gradation images, [3] L for the text part.
The process is divided into three parts, each of which is a part where the CHG signal is set to "L" (printed at 400 dpi), and each part will be explained.

(1) Remaining color removal processing and addition/subtraction processing In this case, the processing is performed on the edge portion of the black character and its surrounding area, where both the signal GRBil26 indicating that it is an achromatic color and the signal MjAR124 indicating that it is a text portion are active. The Y, M, and C components protruding from the edges of black characters are removed, and the edges are filled in.

Next, a detailed explanation of the operation will be given.

This process is subject to character part determination (MjAR124="1"
), this is performed only when the character is black (GRBil26="l") and the mode is color mode (DHil22-"0"). Therefore, ND (black and white) mode (DHi="
1”) and color characters (GRBi="0").

When scanning a document for recording color Y, M, or C, the video manual 111 selects it with the selector 6e (I/
O-6 (set to 5e by 10''). At 15e, 20e, 22e, and 17e, data to be subtracted from video 8e is generated.

For example, if "0" is set in I/O-312e, selector output data 13e
Multiplying by the value set in I/O-17e is performed by multiplier 1.
It takes place in 5e. Here, data 18e is generated that is O-1 times as large as data 13e. By setting 1 to registers 9e and 25e, the two's complement data of 18e becomes 17e,
Generated at 20e and 22e. Finally, adder/subtractor 24
Since addition 23e of 8e and 23e in e is a two's complement number, 17e-8e is actually subtracted and output from 25e.

When "B" is set in I/O-312e, B data is selected in selector lie.

At this time, the value set at I/O-210e is set at 9e for the multi-value achromatic signal GR125 (a signal that takes a large value if it is close to an achromatic color) generated by the character image area separation circuit I. The multiplied value is used as the multiplier of 13e. When this mode is used, the coefficients can be changed independently for each of the colors Y, M, and C, and the amount of subtraction can be changed depending on the achromatic degree.

When scanning recording color Bk, selector 6e selects BkMj1.
12 is selected (I/O-6 5 e has “l”
set). 15e, 20e, 22e,
At 17e, data to be added to video 17e is generated. The difference from the above Y, M, and C cases is I/O-4, 9e.
By setting “0” to 2 3 e =
8e, C i = O, and 17e+8e is output from 25e. The method of generating the coefficient 14e is Y,
The same is true for M and C. Also, I/O-312e! ．． :
When the mode is set to "1", the coefficient changes depending on the degree of achromatic color. Specifically, when the degree of achromatic color is high, the amount of addition is large, and when the degree of achromatic color is small, the amount of addition is small.

This process is illustrated in FIG. 22. (a) and (c) are enlarged views of the shaded portion of the black letter N.

For Y, M, and C data, subtraction from the video is performed when the character signal part is "1" (see (b) in the same figure), and for Bk data, where the character signal part is "l". is added to the video ((d) in the same figure). In this figure l 3e
= l 8e The Y, M, and C data of the block character part are 0,
In this example, Bk data is twice as large as the video.

Through this processing, the outline of black characters is printed in almost a single black color, but the Y, M, and C data outside the outline signal (see Figure 22 (b)
) The * mark shown in ) remains around the letters as residual color, making it unsightly.

The color removal process removes the remaining color.

This processing extends to the area of the text area,
In addition, processing to take the minimum value of 3 or 5 pixels before and after pixels where the video data 13e is smaller than the comparison value set by the CPU, that is, outside the character area, where there is a possibility of color remaining. It is.

Next, the explanation will be supplemented using a circuit.

Figure 23 shows a character area expansion circuit that works to expand the character area.
ND gate 69e, 71e, 73e, 75e,
It is composed of an OR gate 77e.

All I/O ports 70e, 72e, 74e, 76e
When MjArl24 is set to "1", the signals expanded two pixels forward and backward in the main scanning direction are output to I/O ports 70e, 75e "O", 71e, 73e "1".
”, the signal spread by l pixels front and back in the main scanning direction is Sig2
It is output from 18e.

Next, the remaining color removal processing circuit 16e will be explained.

FIG. 24 is a circuit diagram of residual color removal processing.

In FIG. 24, 57e is a 3-pixel min select circuit that selects the minimum value of the pixel of interest and 1 pixel before and after it in response to the input signal 13e; Select the maximum value of a total of 5 pixels. A 5-pixel min select circuit 55e is a converter that compares the magnitude of the input signal 13e and the I/O-18 (54e), and outputs 1 if 54e is larger. 61e, 62e are selectors, 53e, 53'
e is an OR gate, and 63e is a NAND gate.

In the above configuration, the selector 60e selects 3 pixels min or 5 pixels based on the value of I/O-19 from the CPU bus.
Select pixel min. With 5 pixels min, the effect of color residual removal is greater. This can be selected by manual setting by the operator or automatic setting by the CPU.

The selector 62e is configured so that the output of the NAND gate 63e is “0”.
", that is, the comparator 55e determines that the video data 13e is smaller than the register value 54e, and it is within the range of expanding the character signal, and 17'e is 1.
If so, side A is selected, otherwise side B is selected. (However, at this time, registers 52e and 64e are "1"
, register 52'e is "0") When the B side is selected, through data is output as 8e.

The EXCON 50e can be used in place of the comparator 55e when, for example, a binary luminance signal is input.

FIG. 25 shows the area where the above two processes have been applied. 25(a) is the black character N, and FIG. 25(b) is the area determined to be a character in the Y, M, and C data, which is the density data of the shaded area, that is, the character determination part (Kaoru 2, Ku 3
, yi 6, -X-7) becomes O by subtraction processing, yi 1,
Straw 4 is straw l←+0, +4 due to color residue removal process
←The result is 5, which results in O, and Figure 25 (C) is obtained.

On the other hand, for B and data as shown in Figure 25(d),
Character judgment part (So8, Jk9, Ao10, Cloud1
Only addition processing is applied to 1), resulting in an output with a black ring as shown in FIG.

Regarding colored characters, please refer to section. No changes are made as shown in Figure 25(f).

[2] Edge Emphasis or Smoothing Process Here, processing is performed to output edge emphasis for the character determination section, smoothing for the halftone dot section, and outputting through for the rest.

Character part → MjAR124 is “B, so 25e, 2
The output of the 3×3 edge emphasis 30e generated from the three line signals of 7e and +29e is sent to the selector 42.
It is selected at e and output from 43e. Note that the edge enhancement here is obtained from a matrix and calculation formula as shown in FIG.

Halftone part - SCRN35e is "1", M j A R 2
Since 1e is "0", the smoothing 31e applied to 27e is the selector 33e, 42
It is output at e. Note that smoothing is the 27th
As shown in the figure, when the pixel of interest is vN (V N +V
This is a process of converting N4-1)/2 into data of (2), that is, smoothing of two pixels in the main scan. This prevents moiré that may occur in the halftone dot area.

Other→Other portions refers to processing for areas that are neither character portions (character outlines) nor halftone dot portions, specifically, midtone portions. At this time, MjAR124 and SCRN35e
Since both are "ON", the data of 27e is output as is from the video output 43e.

When the characters are colored characters, the above two processes are not performed even in the character determination section.

In the embodiment, an example was shown in which color residual removal was performed only in the main scanning direction, but color residual removal processing may be performed in both the main scanning and sub-scanning directions.

[3] Text section 400 lines (dpi) output processing video output 1
13, LCHG140 is output from 48e. Specifically, the inverted signal of MjARl24 is output in synchronization with 43e. When it is a character part, LCHG is 20, and for other parts, it is 200/400="1".

As a result, the character part determination part, specifically the character outline part, is 4
00 line (dpi), and the others are printed at 200 line (dpi).

Next, the character image synthesis circuit F will be explained.

FIG. 28(a) is a block diagram of a circuit for processing and modifying images using binary signals in this apparatus. Color image data 138 input from the image data input section is input to the V input of the 3t01 selector 45.

The other two operators A and B of the 3tol selector 45f contain lower parts (An, B) of the data read out from the memory 43f.
B,) Of the 555f, A has An and B has Bn.
is latched by VCLKI17 in latch 44f and input. Therefore, the output Y of the selector 45f has the selection power X. , X,, Jl, J
Based on 2, either V, A, or B is output (1
14).

Data Xll is the upper 2 bits of the data in the memory in this embodiment, and serves as a mode signal for determining processing and modification. 139 is a code signal output from the area signal generation circuit.
It is controlled to switch in synchronization with K117, and the memory 43
It is input as the address of f.

That is, for example, (X
+o. A+o. Boo) = (01, A, o,
B. ), and as shown in FIG. 29(b), code signal 1 is written in synchronization with the scanning of line l in the main scanning direction.
39, “lO” from point P to point Q and “1O” from point Q to point R.
0'', data xI1=(0
, l) are read out, and at the same time, data (AI., BIQ) is latched and output to (An, B, l). The truth table of the 3tol selector 45f is shown in Figure 28 (C
) as shown in (, (X ,, Xo) = (0.
1) is the case of (B), and if Jl is "Bi," input A is set to Y, therefore, Y is set to constant A, and J1 is set to "0".
If so, ①input is set to Y, which means that the input color image data is output as is to the output 114. In this way, for example, so-called tweezers character synthesis of a character portion having a value of (A1o) is realized for a color image of an apple as shown in FIG. 29(b). Similarly (X
l + Xo) = (t, o), and the 29th
When a signal like Jl in figure (C) is input, the FIFO
47f to 49f, and circuit 46f (details in Fig. 28 (
b)), a signal like J2 in the same figure is generated, and the second
If the truth table in Figure 8 (C) is followed, characters will be output with frames in the apple image (outline or envelope characters) as shown in the same figure.

Similarly, in FIG. 28(D), the rectangular area inside the apple is (
The characters inside are output with a density of (AI,). In the same figure (A), (X1, XO) =
(0, O), i.e. for any Jl, J
Depending on the binary signal, there is a control that does not perform anything even for a change of 2.

The signal with expanded width input to J2 is shown in Fig. 28(b).
According to , the size is expanded by 3×3 pixels, but it is easy to increase the size even further by adding a hardware circuit.

In addition, Co, Cl (366, 367) output from the I/O port 501 in FIG. 2 in association with the output colors (Y, M, C, Bk) to be printed are stored in the memory 4.
It is input to the lower 2 bits of the address of 3f, and therefore "0, 0", corresponding to the output of Y, M, C, Bk.
It changes as “0. 1”, “i, o”, “1, 1”, so for example when yellow (Y) is output, it changes as 0, 4,
8,12. 16...Address, magenta (M) is 1
, 5, 9, 13.17... address, cyan (C
) is 2, 6, 10, 14. 18... Address, black (Bk) is 3, 7, 11, 15.
Number 19... ground is selected. Therefore, according to the operation instructions on the operation panel, which will be described later, the area code signal 139 that determines the area and the corresponding memory address within the area and the corresponding address 2, for example x1 to x4 = "1. 1" (
AI, A2, A3, A4) = (α1, α2, α3, α
4), (B1, B2, B3, B4) = (βl,
β2, β3, β4), and when the 11 signal changes as shown in FIG. 29 (D), J1 becomes “LO”.
The interval is (Y, M, C, Bk) = (α1, α2, α
3, the color is determined by α4), and J1 is “Hi”
When (Y, M, C, Bk) = (βl, β2, β3
, β4). In other words, the output color can be arbitrarily determined based on the memory contents. On the other hand, on the operation panel described later, Y, M, C, and Bk are each adjusted or set in percent (%). That is, each gradation is 8 bits
Since the value is 00 to 255, it is 1%
The fluctuation is a digital value of 2.55.

The setting value is (Y, M, C, Bk) = (Y%, m%, C%
, k%), the values to be set (i.e., the values written to memory) are (2.55y, 2.55y), respectively.
m, 2.55c, 2.55k), and in reality, the rounded integer is written into a predetermined memory. Furthermore, if the adjustment mechanism is used to adjust in %, an addition of 2.55△ (concentration
All you have to do is write the value obtained by subtracting (thinning) or subtracting (thinning) into memory.

In the truth table of FIG. 28(C), the i column is a human output table of characters, image gradation, and resolution switching signal LCHG149, and x, , Xo. Jl, J21. :When A, B, and B are output to output Y, the output is "0", and when V is output to Y, the input is output as is. LCHG14
9 is a signal that switches the print density during printing, for example, when LCHG="0", for example, 400d.
When pi, LCHG = "1", print at 200 dpi. Therefore, when A or B is selected, LCHG=0
This means that the inner area of the synthesized characters is 400 dp.
This means that areas other than the i1 character are printed at 200 dpi, and the characters are controlled to maintain high resolution, sharp halftone parts, and high gradation, and are output smoothly.

As mentioned above, the LCHG140 uses the character image correction circuit E based on MJAR, which is the output of the character/image separation circuit (■).
That is why it is output from .

Image processing and editing circuit> Next, image signal 1 after receiving color balance adjustment at P
15 and the gradation resolution switching signal LCHG141 are input to the image processing and editing circuit G. A rough schematic diagram of the image editing processing circuit G is shown in FIG.

Input image signal 115, gradation resolution switching signal LC
HGl41 is first input to the texture processing section 101g. The texture processing section is roughly divided into a memory section 103g that stores texture patterns, memories RD and WR that control them, an address control section 104g, and an arithmetic circuit 105g that performs modulation processing on input image data according to the stored pattern. It consists of The image data processed by the texture processing section 101g is then input to a scaling, mosaic, and taper processing section 102g. The variable magnification, mosaic, and taper processing section 102g has a double buffer memory 105g, 1
06g and a processing/control unit 107g, various processes are independently performed and output by the CPU.

Here, the texture processing section 101g and the scaling, mosaic, and taper processing section 102g receive GHil (119), which is an enable signal for each process sent from the switching circuit N.
and GHi2 (149) are configured to perform texture processing and mosaic processing on independent areas.

Further, the gradation resolution switching signal LCHG signal 141 input together with the image data 155 is processed in various processes while matching the phase with the image signal.

The image processing/editing circuit G will be explained in detail below.

Texture Processing Unit> Texture processing is a process of cyclically reading out a pattern written in memory and applying modulation to the video. ) to generate an output image as shown in (c) of the same figure.

FIG. 32 is a diagram illustrating the texture processing circuit.

Below, modulation data 2 to texture memory 113g
18g writing section and 113g texture memory
216g of data and 215g of image data (
Texture processing) will be explained separately.

[Data writing section to texture memory 113g] When writing data, masking, undercolor removal, and smearing are performed, and data is input from 201g. This data is selected by selector 202g. On the other hand, selector 208
At g, data 220g is selected and memory 113g is selected.
W1 and the enable signal of the driver 203g. The memory address is generated by a vertical counter 212g that counts up in synchronization with the horizontal synchronization signal HSYNC, and a horizontal counter 211g that counts up in synchronization with the image clock and VCK.B is selected by the selector 210g, and the address of the memory 113g is generated. Enter.

In this way, the density pattern of the input image is stored in the memory 11.
Written to 3g. Typically, this pattern is an input device,
For example, it is located and written using a digitizer.

[Writing data by CPU] CPU data is selected by the selector 202g.

On the other hand, A is selected by the selector 208g, and the memory 11
It is input to the enable signal of the driver 3g and the driver 203g. As the memory address, A is selected by the selector 210g and inputted to the address of the memory 113g. thus,
An arbitrary density pattern is written into memory.

[Calculation unit for texture memory 113g data 216g and image data 215g] This calculation is realized by a calculation unit 215g. This arithmetic unit here consists of a multiplier. Data 216g and 201 only where enable signal 128g is active
An operation with g is performed, and when the disable is enabled, the signal 201 becomes a through state.

Also, 300g and 301g are XOR and OR gates, respectively, and register 304 is a part that generates an enable signal using MJ signal 308g, that is, a character synthesis signal.
When g"1" 305g is set to "0" in the register, texture processing is applied to areas other than those containing composite character signals. On the other hand, register 304g is “0” and register 305g is “0”.
When ' is set in the register, texture processing is applied only to the part that contains the composite character signal.

302g is a portion that generates an enable signal using a GHil signal 307g, that is, a non-rectangular signal. When the register 306g is ``0'', texture processing is performed only where the GHil signal is enabled. Enable 1 at this time
If 28 is kept active, non-rectangular texture processing is performed that is not influenced by non-rectangular signals, that is, synchronized with HSNC.If enable signal GHil and enable 128 are made the same, texture processing is performed that is synchronized with non-rectangular signals. Become.

For example, if a 3 lb bit signal is used for GHil, texture processing can be performed only on a certain color.

The LCHG, N signal 141g is a gradation resolution switching signal, which is delayed by the amount of delay in the arithmetic unit 215g.
Output from u1350g.

<Mosaic, scaling, and taper processing unit> Next, the general operation of the mosaic, scaling, and taper processing unit G12 of the image processing/editing circuit G will be described using FIG. 33.

Image data 1 26g and LCHG signal 350g input to the mosaic, scaling, and taper processing section 102g are as follows:
First, it is input to the mosaic processing unit 401g. The mosaic processing unit 401g uses the Mj signal 145 output from the character synthesis circuit F and the area signal GHi 214 from the switching circuit N.
9. After the mosaic clock MCLK from the mosaic processing control unit 402g determines whether or not to perform mosaic processing, the size of the mosaic in the main scanning direction, character composition, etc.
It is input to the to2 selector 403g. Here, the main scanning direction size for mosaic processing is the mosaic clock MC.
It is made variable by controlling LK. Control of the mosaic clock MCLK will be explained in detail later.

1 to2 selector-403g, HSYNCI18
The input image signal and LCHG signal are output to either Y1 or Y2 by the line memory select signal LMSEL whose frequency is divided by the D flip-flop 406G.

1 Output from Y1 of to2 selector-403g is output from line memory A404g and 2tol selector-407
Connected to A of g. Also, the output from Y2 is line memory B405g and 2tol selector 407.
Connected to B of g. When an image is sent from selector 403g to line memory A, line memory A
404g is in write mode and line memory 8
405g is in read mode. Similarly, when an image is sent to the line memory 8405g from the selector 403g, the line memory B is in the write mode and the line memory A 404g is in the read mode. In this way, the image data read out alternately from line memory A 404g and line memory B 405g is 2to
1 Selector-407g TeD 7 Rip Flop 406
g (7) Output as continuous image data while being switched by an inverted signal of the output LMSEL signal. 2to
The output image signal from the l selector 407g is then subjected to predetermined enlargement processing in an enlargement processing section 414g and then output.

Next, write/read control of these memories will be described. First, when writing or reading, line memory A
404g The address given to the 1-line memory B 405g is synchronized with HSYNC, which is the reference for one scan, and is synchronized with the image C
Up/down counters 409g, 41 to increment and decrement in synchronization with LK.
It is composed of 0g. A counter enable signal output from the line memory address control unit 413g,
The operation of the address counters (409g, 410g) is controlled by a control signal WENB for controlling a write address and a control signal RENB for controlling a read address generated from the scaling control section 415g. These controlled address signals are input to 2to1 selectors 407g and 408g, respectively. The 2t01 selectors 407g and 408g provide a read address to the line memory A 404g and a write address to the line memory 8405g when the line memory A 404g is in the read mode, using the aforementioned line memory select signal LMSEL. When the line memory A 404g is in write mode, the opposite operation is performed.

Next, memory write pulses WEA and WEB to line memory A and line memory B are outputted from the variable magnification control section 415g. Memory write pulses WEA and WEB are used when reducing the input image and when the mosaic processing control unit 4
Mosaic processing is controlled by a mosaic length control signal MOZWE in the sub-scanning direction output from 02g.

Next, a detailed explanation of these operations will be given below.

Mosaic Processing> Mosaic processing is basically realized by repeatedly outputting one image data.

This mosaic processing operation will be explained using FIG. 34.

First, a mosaic processing control unit 402g independently performs main scanning and sub-scanning mosaic processing control.

First, set the variable corresponding to the desired mosaic size to CPU
The CPU sets the latch 501g (for main scanning) and the latch 502g (for sub-scanning) connected to US. First, mosaic processing in the main scanning direction is performed by writing the same data to multiple addresses in the line memory consecutively, and mosaic processing in the sub-scanning direction is
Writing to the line memory within the mosaic processing area is performed by thinning out every predetermined line.

(Main scanning direction mosaic processing) A variable corresponding to the mosaic width in the main scanning direction is set in the latch 501g by the CPU. The latch 501g is connected to the main scanning mosaic width control counter 504g,
The setting value is loaded by the HSYNC signal and the ripple carry of the counter 504g.

The counter 504g loads the value set in the latch 501g for each HSYNC, counts a predetermined value, and outputs the ripple carry to the NOR game}502g and the AND game}509g.

Mosaic clock MCL from AND gate 509g
K is a signal obtained by multiplying the image clock CLK by the ripple carry from the counter 504g, and MCLK is output only when the ripple carry occurs.

MCLK output from the AND game 509g is then input to the mosaic processing section 401g.

The mosaic processing unit 401g operates the flipflop 510 regardless of the two D flipflops 510g and Mj signals.
Output g. When the GHi2 signal 149 is 1 and the Mj signal is O, a signal from the flip-flop 511g controlled by the mosaic clock MCLK is output.

When the Mj signal is 1, the output is a flip-flop 510g
Output the signal from. With this control, it is possible to output a part of the mosaic-processed image in the main scanning direction without performing the mosaic process. In other words, it is possible to perform mosaic processing on only the image without performing mosaic processing on the characters that have been synthesized into an image by the preceding character synthesis circuit F as shown in FIG. The output from the selector 512g is input to the 2tol selector 403g shown in FIG. 33 mentioned above. As described above, mosaic processing in the main scanning direction is performed.

(Sub-scanning direction mosaic processing) Similarly to the main scanning direction, the sub-scanning direction is also controlled by a latch 502g connected to CPUBUS, a counter 505g, and a NOR gate 503g. The sub-scanning mosaic width control counter is the ITOP signal 144, 511g, selector 512g, AND gate 514g, and inverter 513.
It is composed of g. Flip flop 510g, 5
11g contains a gradation resolution switching signal LC in addition to the image signal.
The flip-flop 510g holds the image clock CLK, and the flip-flop 511g holds the image data inputted by the mosaic processing clock MCLK and the LCHG signal. That is, the gradation resolution switching signal LCHG corresponding to one pixel is held in phase in the flip-flops 510g and 511g during each cycle of CLK and MCLK. Each retained image signal and LCHG signal are input to a 2to1 selector-512g. The output is switched by the mosaic area signal GHi2 and the binary character signal Mj signal. The selector 512g generates a ripple carry pulse by counting HSYNC118. The ripple carry pulse is sent to the OR gate 508g as the mosaic area signal GHi2.
149 inverted signal GHi2 and character signal Mj are input. It is input to the sub-scanning mosaic control signal MOZWE415g, and the NAND gate 515g controls the write pulse generated by a line memory write pulse generation circuit (not shown). What is line memory write pulse generation circuit?
This is a circuit that can vary the output clock rate, such as a rate multiplier, which is generally used for variable magnification control. In this embodiment, detailed explanation will be omitted since it differs from the gist of the invention.

The WR pulses controlled by the M O Z W E signal are then alternately outputted from the 1 to 2 selector to WEA and WEB by the switching signal LMSEL signal which changes the switching pulse for each HSYNCI18. With the above control, mosaic area signal GHi2 signal 1
Even when 49 is “l”, when the Mj signal becomes “1”,
Since writing to the memory is performed, it is possible to output a part of the mosaic-processed image in the sub-scanning direction without performing the mosaic process. FIG. 35(a) is a diagram showing the distribution of density values for each pixel for recorded colors when mosaic processing is actually performed. In the mosaic processing shown in FIG. 35, each pixel in a 3×3 pixel block is set to a representative pixel value. In this process, the mosaic process is not performed on the character A1, that is, the pixels in the shaded area, based on the character signal Mj. In other words, when a composite character and a mosaic processing area overlap, priority can be given to the character.

Therefore, even when mosaic processing is performed, an image can be formed so that only the characters can be read. Note that the mosaic area is not limited to a rectangular shape, and mosaic processing can also be performed on a non-rectangular area.

(Italics, Taper Processing) Next, the italics processing will be described first with reference to FIGS. 33 and 36.

FIG. 36 shows the inside of the line memory address control section 413g in FIG. 33. This line memory address control unit 413g has write and read counters 409g, 4
10g enable signal is controlled, and movement, italics, etc. are possible by controlling an address counter to determine which part of the main scanning line is to be written into or read from the line memory. First, using Figure 36,
The enable control signal generation circuit will be explained.

The counter 701g has a counter output of O at HSYNC.
Then, the image clock 117, which is the clock of the counter 701g, is counted. counter 701
The output Q of g is the equisurface comparator 706g, 708g,
It is input in 709g and 710g. The A input side of each comparator other than the comparator 709g is connected to an independent latch (not shown) connected to the CPUBUS, and an arbitrary set value and the counter 70
When the output of 1g matches, a pulse is output. The output of the equilateral comparator 706g is connected to the J of the J-K flipflop 708g, and the comparator 707g is connected to the K input, so that the J-K flipflop is connected from the time when the comparator 706g outputs a pulse until the time when the comparator 707g outputs a pulse. 708g is configured to output l. This output is used as a write address counter control signal, and the write address counter is activated only in the period where it is 1, and generates an address for the line memory. Similarly, the read address counter control signal controls the read address counter. Here, comparator 709g
A selector 703g is connected to the input signal to A in order to make the input value to the comparator different depending on whether or not italic processing is performed. Here, when italic processing is not performed, the value set in the latch connected to CPUBUS (not shown) is input to the A input of selector 703g, and the 8 inputs are similarly output by the select signal output from the latch (not shown). It is output from the selector 703g. The subsequent operation is performed by the comparators 706g and 7 described above.
The operation is similar to 07g. Next, when performing italics, the value input to A of selector 703g is also input to selector 702g as a preset value. When the select signals of selectors 702g and 703g select the B input, the output of selector 702g is sent to adder 70.
At 4g, addition is performed with a value set in a latch, also not shown. Here, this value indicates the amount of change per line due to the oblique angle, and if the desired angle is θ, then t
It is determined by anθ. The addition result is input to the flipflop 708g clocked by HSYNC118, and
The value is retained during the main scan. flipflop 705
The output of g is connected to the B input of selector 702g and the B input of selector 703g. By repeating this addition operation, the output value from the selector to the comparator 709g changes at a constant rate for each scan, so that the start of the read address counter can be varied from HSYNC at a constant rate.

As a result, the reading from the line memories A404g and A8405g is shifted with respect to HSYNC, and italic processing becomes possible. In addition, the amount of change mentioned above can be either positive or negative; if it is positive, the readout will shift away from HSYNC, and if it is negative, it will shift away from HSYNC.
Shifts in the direction of approaching . Also, selector 702g
, 703g in synchronization with HSYNC, partial italics can be made possible.

Regarding enlargement processing methods, generally 0-order, 1-order, SINC
There are methods such as interpolation, but since they are different from the gist of the present invention,
Explanation will be omitted. Taper processing is made possible by changing the magnification in the main scanning direction in synchronization with HSYNC for each scanning line while performing diagonal processing.

In addition, in these processes, the input gradation resolution switching signal is processed while matching the phase with the image signal, and the output image data 114 and the output gradation resolution switching signal LCHG are processed.
142 is output to the edge emphasis circuit.

The conceptual diagram of the italic processing and taper processing explained above is shown in the 35th page.
Figure (b). Shown in (C).

FIG. 37(a) is a block diagram showing details of a mask bitmap memory 573L and its control for restricting an area of arbitrary shape. This memory has a shape as shown in FIG. 37(e), for example, and is used for the aforementioned color conversion, image cropping (non-rectangular trimming), and image filling (
It is used as an ON (process)/OFF (non-process) switching signal for various image processing/editing such as non-rectangular painting).

That is, in FIG. 2, BHil23, DHil22,
FHil21, GHi119, PHil45, AHi
It is supplied via the l48 signal line.

As shown in Figure 38, the mask is configured such that 4x4 pixels are one block and one bit of the bitmap memory corresponds to one block, so for example, 16pe
For an image with a pixel density of l/mm, 297 mm x 420 m
m (A3 size), (297X420X1
6X16)÷1642Mbit, that is, for example I
It can be configured with M bit dynamic RAM and 2 chips.

The signal 132 input to the FIFO 559L in FIG. 37(a) is a data input line for mask generation as described above. For example, the output 421 of the binarization circuit 532 in FIG. When input, first 4×
Count the number of "l" in the block of 4.
, 562L. FIFO559L~562L
As shown in the figure (output of 559L is input to 56OL,
The output of 560L is connected to the input of 561L, and so on, and the output of each FIFO is latched in 4 bits in parallel.
~565L+. :, VCLKil: is latched (see the timing chart in FIG. 37(d)).

FIFO output 615L and latch 563L, 56
4L, 565L outputs 616L, 617L, 61
8L are added by adders 566L, 567L, and 568L (signal 602L), and the CPU 22 compares the magnitude with a value (for example, "12") set via the I/O boat 25L in the comparator 569L. . That is, here, it is determined whether the number of 1's in the 4×4 block is greater than a predetermined number.

In FIG. 37(d), the number of "l"s in block N is "14" and the number of 1's in block (N+1) is "4", so the output of comparator 569L in FIG. 37(a) When the signal 602L is "14", the signal 603L is larger than "12", so when "1" = 4', it is smaller than "12" and becomes "0". Therefore, the latch pulse 605L of FIG. 37(d) The latch 570L latches one 4×4 block once, and the Q output of the latch 570 becomes the DIN input of the memory 573L, that is, the mask creation data. 580L is an H address counter that generates the address in the main scanning direction of the mask memory, and since one address is assigned to a 4×4 block, the pixel clock V
Counting up is performed using a clock obtained by dividing CLK608 by four using a frequency divider 577L. Similarly, 575L is an address counter that generates an address in the sub-scanning direction of the mask memory, and for the same reason, it is counted up by a clock obtained by dividing the synchronization signal HSYNC of each line by 4 by a frequency divider 574L. ■Address operation is 4
It is controlled to be synchronized with the counting (addition) operation of "1" in the ×4 block.

In addition, ■ Output of the lower 2 bits of the address counter, 610
L, 611L is NORed by a NOR gate 572L, and a signal 606 gates a 4-frequency clock 607L.
L is created, and the AND gate 571L is used to divide 1 block into 4×4 blocks as shown in timing chart FIG. 37(C).
The latch signal 605L is applied so that latching is performed only once. Further, 616L is a data path included in the CPU bus 22 (FIG. 2), 613L is an address bus, and a signal 615L is a write pulse WR from the CPU 22. Memory 57 from CPU 22
During WR (write) operation to 3L, the write pulse is “LO”.
'', the games 578L, 576L, and 581L are opened, and the address bus and data path from the CPU 22 are connected to the memory 573L, and predetermined data is randomly written, and WR is sequentially written by the H address counter and ■address counter. (write), when performing RD read, gate 5 connected to I/O port 25
Gate 576' is connected by control lines 76'L and 582L.
L, 582L is opened and sequential addresses are provided to memory 573L.

For example, the output 421 of the binarized output 532 or the CPU
22, if a mask as shown in FIG. 39 is formed, images can be cut out, synthesized, etc. based on the area within the bold line frame.

Further, the bitmap memory shown in FIG. 37(a) can be read by thinning out or interpolation in both the H direction and the ■ direction.

That is, as shown in FIG. 40 in detail of the H or V address counter (580L, 575L) in FIG.
For example, during reduction, the B input of the selector 634L should be selected.<MULSEL 636L is set to "0".

635L is a decimation circuit (rate multiplier) for the input clock 614L, and Fig. 41 (timing diagram)
As shown in (637L), CLK is thinned out so that, for example, CLK is output once every three times (setting is I/O port 641Ll: YOL). On the other hand, 630Ll1m is, for example, ``2
" is set and the outputs 638L and 63 of the address counter 632L are output only when the thinned out output 637L is output.
The value set in OL (for example "2") is added and the result is loaded into the counter. Therefore, as shown in FIG. 41, it advances by "+2" every three clocks in the order of l→2→3→5→6→7→9, etc., resulting in a reduction of 80%. On the other hand, when enlarging, MULSEL="BI" and the 8th input 614L is selected, so the address count is 1 → 2 → 3 → 3 → 4 → 5 → 6 as shown in the timing chart of FIG.
Proceed as →6 →...

Figure 40 shows the H address counter 580L of Figure 37, ■
This is the details of the address counter 575L, and since the hardware circuit is the same, the explanation will be limited to FIG. 37 only.

As a result, enlargement 2 and reduction 1 are generated for the input non-rectangular area 1 as shown in Fig. 42, so once the non-rectangular area is input, no new input work is required. Furthermore, one mask plane can be used to change the magnification according to various magnifications.

Next, the binarization circuit (532 in FIG. 2) and the high-density binary memory circuit K will be explained. In FIG. 43(a), the binarization circuit 532 outputs the video signal 1 from the character image correction circuit E.
13 with a threshold value 141k to obtain a binary signal, the threshold value is set by the CPU bus 22 in conjunction with the operation unit. In other words, the threshold value is the amplitude value of input data =
256, the memory of the operation unit in FIG. 43(c) is set to M(
When specified as the midpoint), it is "128", and as the scale moves in the ten directions, it changes by -30" from the midpoint, and as it moves in one direction, it changes by "+30". Therefore, "Weak → -2 → -1→M→+1→+2→Strong”, the threshold value is “218→188→158→128→98→68→3
It is controlled to change to 8''.

In addition, as shown in FIG. 43(a), CPUBUS
From 22, two threshold values are set, and selector 35
At k, it is switched by the switching signal 151 and set as a threshold value in the comparator 32k. For the switching signal 151, a different threshold value is set only within a specific area set by the Digitiger 58. For example, the threshold value is relatively low for a monochromatic area of the document, and relatively high for a mixed color area. <<It is possible to set this so that a uniform binary signal is always obtained regardless of the color of the original.

The memory circuit K is a memory that stores the signal in which the binarized signal 421 is output to 130 for one page of images, and since this device handles images at A3 and 400 (dpi), approximately 3 It has 2 Mbit.

Details of the memory circuit K will be explained in FIG. 43(b).

The input data D and N130 are gated by the enable signal HE52B when writing to the memory, and are further gated by the IO port 23k controlled by the CPU 20 when writing. /R
When the I output is "old", it is input to the memory part 37k. At the same time, a synchronizing signal HSYNC118 in the main scanning (horizontal scanning) direction is counted from a synchronizing signal ITOP144 in the vertical direction of the image to generate a vertical address. (2) Address counter 35k1} {Counts the image transfer clock VCLK117 from the SYMCI 18, and counts the addresses in the horizontal direction. The H address counter generates an address corresponding to storage of image data.

Memory WP input at this time (write timing signal)
A clock having the same phase as the clock VCLK117 is input as a strobe to the clock VCLK117, and the incoming data Di is sequentially stored in the memory part 37k (timing diagram, No. 4).
Figure 4). When reading data from the memory 37k, set the control signal W/R 1 to "Lo" and read the output data D using exactly the same procedure. UA is read out. However, since data writing and reading are both performed by the HE528, for example, as shown in Figure 44 (HE528
is raised to “Hi” at the input timing of D2, and D.
When it is turned down to "Lo" at the input timing of (2), only the images from D2 to Dffl are input to the memory 37k, and the images after Do, D, and Dm++ are not written.
Data "0" is written instead. The same goes for reading, and data "0" is read out except for the section where HE is "Hi". HE is output from an area signal generation circuit 17, which will be described later. In other words, for example, when a character document as shown in FIG. 45A is placed on the manuscript table, if HE is generated as shown in the figure when writing a binary signal, only the character part becomes binary as shown in A'. Images can be loaded into memory. Similarly, unnecessary characters can also be erased and written into the memory.

Furthermore, since the address counters 35k and 36k that read data from the memory 37k have the same configuration as in FIG. 40 and operate at the same timing as in FIG. 41, the binary data read from the memory 37k is It becomes possible to change the magnification. Therefore, when synthesizing the binary character image shown in (B) of the same figure, which has been previously stored in this memory as shown in Fig. 46, with the image of (A), both of them are reduced as shown in (C). or create a sketch ((A) as shown in (D)).
It is possible to perform composition by enlarging only the character part to be composited without changing the size of the part ).

FIG. 47 shows the data stored at the equivalent of 100 dpi as described above.
Image processing blocks A, B, D, F for data from binary bitmap memory L for non-rectangular masks (Fig. 2) and 400 dpi binary memory K for characters and line images (Fig. 2)
, P, G, and the distribution of the binarized video image to the memories L, K. The mask data for limiting the non-rectangular area stored in the memory is sent, for example, to the color conversion circuit B mentioned above (BHi 123), and for example, as shown in FIG.
) Color conversion is applied only to the inside of the shape. 47th
In the figure, In is an I/O port connected to the CPU bus 22, 8n to l3n are 2 to 1 selectors, and when S = "9", the input is 8, and when S = "0", the B input is set to Y. is configured to print. Therefore, for example, in order to send the output of the 100 dpi mask memory L to the color conversion circuit B as described above, in the selector 9n,
, that is, 28n="1", and 2In manual power="1" in AND gate 3n. Similarly, other signals can be arbitrarily controlled by 16n to 31n. I
/O port nl output, 30n, 31n is the binarization circuit 5
When 30n = “1”, which is the control signal for storing the output of 32 (Fig. 2) in either binary memory L or K,
Binary human power 421 goes to I00dpi memory L, 31n="
1", it will be input to the 400 dpi memory K.

By the way, when AHil48="I", the image data sent from the external device is combined, and when BHil23="B", color conversion is performed as described above, and DHi122-"
l", monochrome image data is calculated and output from the color correction circuit. Hereinafter, FHi 121, PHf145
, GHi119, and GHi2 149 are used for character composition, color balance change, texture processing, and mosaic processing, respectively.

In this way, it has two binary memories, LOODPI memory L and 400dpi memory K, and stores character information in high-density 4-bit memory.
By inputting region information (including rectangular and non-rectangular shapes) into the 100 dpi memory K, character synthesis can be performed in a predetermined region, especially in a non-rectangular region.

Furthermore, by having a plurality of bitmap memories, color mudding processing as shown in FIG. 62 is also possible.

FIG. 49 is a diagram for explaining the area signal generation circuit J. The area refers to, for example, the shaded area in FIG. 49(e), which refers to the area in the sub-scanning direction A+B, where the timing chart in FIG. 49(e) is
It is distinguished from other areas by signals such as . Each area is designated by digitizer 58 in FIG. Figure 49(a)-(d)
), the generation position, section length, and number of sections of this area signal are C
This shows a configuration in which a large number of programs can be obtained using the PU20. In this configuration, one area signal is for the CPU-accessible RAM! For example, n area signals A R E A O - A
In order to obtain R E A n, an n-bit RAM is used.
(Fig. 49(d) 60j, 61j
). Now, the area signal AREAO as shown in FIG.
and AREAn, address x of RAM
Set bit 0 of I+X3 to "l", and set all bits 0 of the remaining addresses to "0". On the other hand, "1" is set in the RAM addresses 1 and X1+X2+x4, and all bits n of other addresses are set to "O". HSYNC
R is synchronized with a constant clock 117 using I18 as a reference.
For example, as shown in FIG. 49(c), when reading AM data sequentially, addresses Xi and X3 are
The data "B" is read out at the point 62j-0 to 62j-n as shown in FIG. 49(d).
Since it is connected to both the J and K terminals of the -K flip-flop, the output toggles, that is, when "l" is read from the RAM and CLK is input, the output changes from "0" to "l".
, "BI" changes to "0", and an interval signal such as AREAO, and therefore an area signal, is generated.Also, if data = "O" across all addresses, no area interval is generated and the area setting is This is not done. Fig. 47(d) shows the circuit configuration, and 60j and 61j are the aforementioned RAMs.

For example, R
While data is being read line by line from the AMA 60j, the CPU 20 (Figure 2) performs memory write operations for setting different areas to the RAMB 61j, thereby alternately generating sections and reading data from the CPU. Switch memory writing. Therefore, Fig. 49(f)
When specifying the shaded area, RAMA and RAMB are switched as A+B→A-B-A, which means (C3.C4,C,) = (0,
1, O), the counter output counted by VCLK 117 is given as an address to RAM 60j through selector 63j (Aa), and gate 66j
The gate 68j is opened, the gate 68j is closed, the data is read from the RAM 60j, and the total bit width, n bits, is input to the JK flip-flops 62j-0 to 62j-n, and the AREAO to AREAn section signals are output according to the set values. generated.

During this time, writing from the CPU to B is via address bus A-
Bus, data bus D-Bus, and access signal R
/W is used. Conversely, when generating a section signal based on the data set in RAMB61j (Ca +
By setting 04 1 06 ) = (LO, l),
It can be done in the same way, and data can be written from the CPU to the RAM 60j.

58 is a digitizer for specifying an area;
Input the coordinates of the specified position from U20 via the ■/○ port. For example, in Figure 50, if you specify two points A and B, A(x + , Y 2 ), B(X2.Yl)
The coordinates of are input.

FIG. 51 shows an interface circuit M for bidirectional communication of image data with an external device connected to this image processing system. lm is an I/O port connected to the CPU bus 22, and each data bus AO to Co, Al
Signals 5m to 9m for controlling the directions of ~C1 and D are output. 2m and 3m are pass buffers having an output dry state control signal E, and 3m can change its direction by inputting D. For 2m and 3m, when the E input is "B", a signal is output, and when it is "0", the output is in an impedance state.For 10m, there are 3 parallel inputs A and B.
, C by selecting one from selection signals 6m and 7m 3
tol selector. In this circuit, basically 1.
(AO, BO, Co) → (AI, Bl, CI), 2.
There is a bus flow of (AI, 81, CI)→D. C as shown in the truth table in Figure 52.
It is controlled by PU20. In this system, as shown in Fig. 53, images input from external devices through AI, A2, and A3 are rectangular, as shown in Fig. 53 (A),
Both non-rectangular and non-rectangular configurations as shown in (B) are possible. When inputting in a rectangle as shown in Figure 53 (A),
A control signal 147 is output from the I/O port 501 in order to set the switching input of the selector 503 in FIG. 2 to "B" so that A is selected.

Corresponds to the area to be combined at the same time. Area signal generation circuit J
The rectangular area signal 129 is generated by writing predetermined data from the CPU to predetermined addresses in the RAMs 60j and 6lj (FIG. 51), as described above. In the area where the image input 128 from the external device is selected by the selector 507, not only the image data 128 but also the gradation and resolution switching signals 140 are switched at the same time. That is,
In the area where an image from an external device is input, a character area signal is generated based on MIAR 124 (FIG. 2), which is detected from the color separation signals of the image read from the document table. Stops the gradation and resolution switching signals and forces “H”
By setting it to "i", the image area from the inserted external device is outputted smoothly with high gradation.

In addition, as explained in FIG. 51, the bit map mask signal AHi 148 from the binary memory L
When selected by signal 147 at 03, Fig. 53 (B)
Image synthesis from external devices such as

Overview of Operation Section> FIG. 54 shows an overview of the main body operation section 1000 of this embodiment. Key 1100 is a copy start key.

Key 1 101 is a reset key that returns all settings on the operation panel to the values when the power was turned on. A key 1102 is a clear stop key, which is used to reset input values such as specifying the number of copies and to cancel a copy operation.

A group of keys 1103 is a numeric keypad and is used to input numerical values such as the number of copies and magnification input. Key l104 is a document size detection key. A key 1105 is a center movement designation key. A key 1106 is an ACS function (black original recognition) key. When ACS is ON, a monochrome black original will be copied in monochrome black. A key 1107 is a remote key, and is a key for passing control to a connected device. Key l108 is a preheating key.

1109 is a liquid crystal screen that displays various information.

The surface of the screen is a transparent touch panel, and when you press it with your finger, the coordinate values are captured.

In the standard state, the magnification, selected paper size, number of copies, and copy density are displayed. While setting various copy modes, the screens necessary for mode settings are displayed one after another. (Setting the cobby mode is done using the keys displayed on the screen.) Also displays the self-diagnosis display screen on the guide screen.

A key 1110 is a zoom key, and is an enter key for entering a mode for specifying the magnification of magnification. A key 1111 is a zoom program key, and is an enter key to a mode in which a magnification ratio is calculated from the original size and copy size. A key 1112 is an enlarged continuous shooting key, and is an enter key for entering enlarged continuous shooting mode.

The key 11l3 is a key for setting inset composition.

A key 1114 is a key set for character composition. key 1
115 is a key for setting color balance. key 1
Reference numeral 116 is a key for setting a color mode such as single color, negative/positive inversion, etc. Key 1117 is a user's color key, and can set any color mode. key 111
8 is a paint key that allows you to set the paint mode. A key 1119 is a key for setting a color conversion mode.

Key 1120 is a key for setting the contour mode. Key 1121 is used to set the mirror image mode. Specify trimming and masking with keys 1124 and l123.

It is possible to specify an area using the key 1122 and set the internal processing differently from other parts. key 1129
is the enter key to enter the mode that performs tasks such as loading texture images. Key 1128 is an enter key for entering a mosaic mode such as changing the mosaic size.

Key l127 is an enter key to a mode for adjusting the edge sharpness of the output image. The key 1126 is a key for setting an image repeat mode in which a specified image is repeatedly output.

A key 1125 is a key for applying italic/taper processing, etc. to an image. Key l135 is a key for changing the movement mode. The key 1134 is used to make settings such as continuous page copying and arbitrary division, and the key 1133 is used to make settings related to the projector. The key 1l32 is an enter key to a mode for controlling optional connected equipment. The key 1131 is a recall key that allows you to recall the settings up to three times ago. Key l130 is an asterisk key.

Keys 1136 to 1l39 are mode memory recall keys.
Used when recalling a registered mode memory. Keys 1140 to 1143 are program memory call keys, which are used to call up registered operation programs.

(Color conversion operation procedure) The procedure of color conversion operation will be explained using FIG. 55.

First, when the color conversion key 1119 on the main body operation section is pressed, the display section 1109 displays P050.

Place the original on the digitizer and use the pen to specify the color before conversion. When the input is completed, the screen of PO51 appears. Here, use the touch keys 1050 and 1051 to adjust the width of the color before conversion, and after completing the settings, press the touch key 1052.
Press. The screen changes to P052, and the touch key 1053 and touch key 1054 are used to select whether to add shading to the converted color.

If you select shading, the color after conversion will have gradation to match the shading of the color before conversion. That is, the above-mentioned gradation color conversion is performed. On the other hand, if you select no shading, the specified color will be converted to the same density. If you select whether or not to have shading, the screen of P053 will appear, allowing you to select the type of color after conversion. If you select 1 055 in P053,
The operator can specify any color to PO54. Further, when the color adjustment key is pressed, the process moves to P055, and color adjustment can be performed in 1% increments for each of Y, M, C, and Bk.

Furthermore, when 1056 is pressed at PO53, the process moves to P056, where the user specifies the desired color of the document on the digitizer with the point pen. Next, the color shading can be adjusted using PO57.

Also, if 1057 is pressed at PO53, the screen moves to P058, where a predetermined registered color can be selected by number.

<Procedure for specifying the trimming area> Below, using Figures 56 and 57, trimming (
The masking is similar, and the area designation method 6 is the same as the partial processing. ) Explain the procedure for specifying an area.

If you press the trimming key 1124 on the main body operation unit 1000 and enter two diagonal points of the rectangle using the digitizer when the display unit 1109 becomes Pool, the screen of P002 will appear, and you can continue to input the rectangular area. can. Also, if you have specified multiple areas, press the area key tool before P001, then press the area key 1002 to select P002.
You can confirm each designated area in the X-Y coordinates as shown in the following.

On the other hand, in this embodiment, it is possible to specify a non-rectangular area using the bitmap memory. POO 1
While displaying the screen, press the touch key 1003 to move to P003. Select the shape here. For circles, ellipses, R rectangles, etc., when the necessary coordinate values are input, the shapes are expanded into the bitmap memory by calculation. In the case of free shapes, coordinate values are input continuously by tracing the desired shape with a point pen using a digitizer, and the values are processed and recorded on a bitmap.

Each non-rectangular area specification will be explained below.

(Circular area designation) When key l004 is pressed at P003, the display section 1109 will display P.
Moving to OO4, a circular area can be specified.

The circular area designation will be explained below using the flowchart of FIG. 58. At SIOI, the center point is input from the digitizer 58 in FIG. 2 (POO4).

Next, the display unit 1109 moves to P005, and in S103 inputs one point on the circumference of a circle having a radius to be specified from the digitizer 58. In S105, the CPU 20 calculates the coordinate values of the input coordinate values on the bitmap memory L (100 dpi binary memory) shown in FIG.

Further, in Sl07, coordinate values of another point on the circumference are calculated.

Next, a bank of the bitmap memory L is selected at 8109, and the above calculation result is input to the bitmap memory L via the CPU bus 22 at Sill. Figure 37(a)
The data is written from CPU DATA 616L to bitmap memory from 604L via driver 578L. Address control is the same as described above, so it will be omitted. This is repeated for all points on the circumference (Sl13) to complete the circular area designation.

In addition, instead of inputting information while calculating it in the CPU 20 as described above, template information for two pieces of information inputted in advance is stored in the ROM 11, and by specifying these two points with a digitizer, the information can be calculated. It is also possible to write directly to the bitmap memory L.

(Specify oval area) P003j: Okay, press key 1005 and POO7i
: Move. The process will be explained below using the flowchart shown in FIG.

First, in S202, the diagonal 2 of the largest rectangular area inscribed in the ellipse
A point is designated by the digitizer 58. For the following circumferential part, do S206 in the same way as in the case of specifying the circular area above.
The data is written to the bitmap memory L in the steps from ~S212.

Next, the straight line portion is written into the memory in steps S214 to S220, and the area designation is completed. As in the case of the circular shape, it is also possible to store the template information in the ROM 21 in advance.

(R rectangular area designation) The method of designation is the same as in the case of an ellipse for memory writing, so the explanation will be omitted.

Incidentally, although the cases of a circle, an ellipse, and an R rectangle have been explained above as examples, it goes without saying that other non-rectangular areas can also be specified based on the same template information.

In POO6, POO8, Polo, and P102, by pressing the clear key (1009 to 1012) after inputting each shape, it is possible to partially erase the bitmap memory.

Therefore, even if a mistake is made in the designation, only the two points can be quickly cleared and the two points can be designated again.

It is also possible to specify multiple areas in succession. When multiple areas are specified, priority is given to processing of the area specified later when processing each of the overlapping areas. However, the one specified first may be given priority.

FIG. 57 shows an output example obtained by trimming with an ellipse using the above settings.

<Operation Procedures for Character Synthesis> The operation setting procedures for character synthesis will be described below with reference to FIGS. 60, 61, and 62. When you press the character synthesis key 1114 on the main body operation section, the LCD display section l109 will display P.
It will be displayed like O20. A character original 1201 to be synthesized is placed on the original table described above, and when the tough key 120 is pressed, the character original is read, binarized, and the image information is stored in the bit map memory shown in FIG. 2 described above. The specific means of processing has been described above, so duplication will be avoided. At this time, to specify the range of the image to be stored, press the touch key 1021 in PO20 to go to the screen of PO21, place the text original 1201 on the digitizer 58, and use the point pen of the digitizer to mark the range with two points. specify.

When the specification is completed, the display section changes to P022, and the user selects whether to read within the range specified by touch key 1023 and touch key 1024 (trimming) or to read outside the specified range (masking). Also,
Depending on the text document, it may be difficult to extract the character portion of the text document during the above-mentioned binarization process. In this case, the touch key 1022 in PO20 moves to the screen of PO23, and the slice level of the binarization process can be adjusted using the touch keys 1025 and 1026.

Since the slice level can be adjusted manually in this way, appropriate binarization processing can be performed depending on the color, thickness, etc. of the characters on the document.

Furthermore, press the touch key 1027, PO24'PO2
By specifying an area with 5', it is possible to partially change the slice level with PO26'.

In this way, by specifying an area and changing the slice level only for that part, even if there is, for example, yellow text in a part of the black text document, separate appropriate slice levels can be set for each of the black and yellow text. By doing so, it is possible to perform good binarization processing on the entire character.

When the reading of the character original is completed, the display section 1109 becomes as shown in FIG. 61, P024.

To select color blank processing, touch key 10 in P024
Press 27 to move to the screen of P025, and select the color of the characters to be combined from among the displayed colors.

It is also possible to partially change the color of the text, in which case the user presses the touch key 1029 to move to the screen of PO27, specifies an area, and then selects the color of the text on the screen of PO30. Furthermore, it is also possible to add color border processing to the edges of the characters to be synthesized, in which case P030
Use the touch key 1031 inside to move to the PO32 screen and select the color of the border. At this time, color adjustment can be performed in the same way as in the case of color conversion described above. Furthermore, touch key 1033
Press to adjust the border width on the screen of P041.

Next, a case in which color number processing is added to a rectangular area containing characters to be synthesized (hereinafter referred to as square processing) will be described. P02
Press the touch key l028 in 4 to move to the screen P034 and specify the area. The processing will be performed within the range specified here. When the area designation is completed, the character color is selected in P037, the touch key 1032 is pressed, the screen moves to P039, and the color of the square is selected.

In the above color selection, for example, on the screen PO25, by pressing the color adjustment key of the touch key 1030, the screen moves to P026, where it is possible to change the tone of the selected color.

Character synthesis is performed according to the procedure described above. FIG. 62 shows an example of the output when the settings are actually made.

In addition to specifying a rectangular area, the area specification can also specify a non-rectangular area as described above.

Texture Processing Setting Procedure> Next, texture processing will be explained using FIG. 63.

When the texture key 1129 on the main body operation section 1000 is pressed, the display section 1109 displays something like PO60.

When applying texture processing, touch key 1060 is pressed to highlight this key. When reading an image pattern for texture processing into the above-mentioned texture image memory (Fig. 32, 113g), press the touch key 106.
Press 1. At this time, if the pattern is already in the image memory, as in P062, if it is not displayed, P
061 will be displayed. By placing the document with the image to be read on the document table and pressing the touch key 1062,
Image data is stored in the texture image memory.

At this time, in order to read any part of the document, the user presses the touch key 1063 and specifies it using the digitizer 58 on the PO63 screen. The specified reading range is 16mmX.
This can be done by inputting with a pen at one point at the center of 16 mm.

Reading of a texture pattern by specifying one point as described above can be performed as follows.

Without reading the pattern, press the touch key 1060, set the texture processing, and press the copy start key 1.
If an attempt is made to escape from the P064 screen using 100, other mode keys (1110-1143), touch key 1064, etc., the display section issues a warning as shown at P065.

Further, the length and width of this range can be specified by the operator.

<Mosaic processing setting procedure> FIG. 64 is a diagram explaining the procedure of mosaic processing setting.

When the mosaic key 1128 on the main body operation section is pressed, the display section displays something like PIOO. To apply mosaic processing to a document, touch key 1400 is pressed to highlight this key.

Furthermore, when performing mosaic processing, the mosaic size is changed by pressing the touch key 1401 on the PIOI screen. The mosaic size can be changed independently in both the vertical (Y) direction and the horizontal (X) direction.

<About the screen mode operation procedure> FIG. 65 is a diagram illustrating the operation procedure in the screen mode.

When the blue key 1130 on the main body operation section 1000 is pressed, the food mode is entered, and the display section 1109 is displayed as PI 10. The touch key 1500 enters a color registration mode for registering color information used in paint user colors, color conversion, color text, and the like. A touch key 1501 turns on/off a function for correcting image defects caused by the printer. Touch key 1502 is a key for entering mode memory registration mode. Touch key 1503 enters a mode for specifying the manual feed size. Touch key 1504 enters program memory registration mode. Touch key 1505 is a key for entering a mode for setting default values of color balance.

(Regarding color registration mode) When P110 is displayed, press touch key l500 to enter color registration mode. The display section looks like Pill, and the type of color to be registered is selected. To change the palette color, press the touch key 1506, select the color you want to change on the screen of P116, and select yellow, yellow, etc. on the screen of P117.
The values of magenta, cyan, and black components can be adjusted in 1% increments.

Also, if you want to register any color on the document, touch key 1.
Press 507, select the registration number on the screen of P118,
Specify using the digitizer 58, set the original on the original table when the screen of P120 is displayed, press the touch key 1510,
Register.

(About specifying the manual feed size) As shown in PI12, the manual feed size can be specified as either a regular size or a non-standard size.

For non-standard shapes, both the horizontal (X) direction and the vertical (Y) direction can be specified in l mm units.

(Regarding mode memory registration) The set mode can be registered in the mode memory as shown in P113.

(Regarding program memory registration) As shown in P114, a series of programs for specifying an area and performing predetermined processing can be registered.

(Regarding color balance registration) As shown on P115, color balance can be registered for each of Y, M, C, and Bk.

<Regarding program memory operation procedure> The registration operation in the program memory and its usage procedure will be explained below with reference to FIGS. 66 and 67.

Program memory is a memory function that stores operating procedures related to settings and reproduces them. It is possible to connect the necessary modes and make settings that go beyond unnecessary screens. As an example, let's program memory the procedure for changing the magnification of a certain area of a document and repeating the image.

Press the hard mode key l130 on the main body operation section, display the screen P080 on the liquid crystal display, and press the program memory key of the touch key l200. In this embodiment, four programs can be registered. Select the number to register on the PO81 screen. After this, move to program registration mode. In the program registration mode, for example, the screen shown in FIG. 68 1300 in the normal mode becomes as shown in l301. The skip key of touch key l302 is designated when the user wants to skip the current screen. The clear key of the touch keys 1303 is used to cancel the current registration in the middle of program memory registration and restart the registration from the beginning.

The end key of the touch keys 1304 exits the program memory registration mode and registers in the memory of the first determined number.

First, press the trimming key 1124 in the main unit operation section,
Specify the area with the digitizer. The display unit is displaying P084, but if no further area settings are to be made at this point, touch key 1202 is pressed to designate skipping this screen. (The screen becomes P085) Next, when the zoom key 1110 on the main body operation section is pressed, the display section becomes P086. Here, the magnification is set and when the touch key 1203 is pressed, the display changes to PO87. Finally, press the image repeat key 1126 on the main body operation section to make settings regarding image repeat on the screen P088, and then register to number 1 in the program memory using the touch key 1204.

To call up the program registered in the above procedure, press the program memory 1 call key l140 on the main body operation section. The display section displays PO9 1 and waits for area input. When an area is input using the digitizer, the display section displays P092, and then moves to the next P093. After setting the magnification here, if the touch key 1210 is pressed, the display section changes to PO94 and image repeat can be set. When the touch key 1211 is pressed, the mode in which the program memory is used (referred to as trace mode) is exited.

Note that from the time the program memory is called until the program is terminated,
Each key (1110-1143) in the edit mode is disabled and operations can be performed according to the registered program.

FIG. 69 shows the program memory registration algorithm. Turning the screen of S301 is a key or touch key. This means changing the display on the display.

If you press the touch key 1302 and specify to skip the currently displayed screen (S303), that information will be set on the recording table when the next screen appears (S303).
305). Then, in S307, a new screen number is set in the recording table. If the clear key is pressed, the record table is completely cleared (3309, S311); otherwise, the process returns to S301 and moves to the next new screen. FIG. 71 shows the format of the recording table. FIG. 70 shows an algorithm representing the operation after calling the program memory.

If there is a screen change in S401, it is determined whether the new screen is a standard screen (S403). If it is a standard screen, the process moves to S411, and the next screen number is set from the recording table; if it is not a standard image, the new screen number is compared with the scheduled screen number in the recording table (S405).
, if they are equal, the process moves to S409, and if there is a skip flag, S411 is skipped and the process returns to S401. If they are not equal, recovery processing is performed (5407) and the screen is turned over.

〔Effect of the invention〕

As explained above, according to the present invention, with a simple circuit configuration, it is possible to determine whether input image data is an image part or a text part, and reproduces smooth images and sharp characters at the same time. Figure 1 is an overall diagram of an image processing apparatus according to an embodiment of the present invention; Figure 2 is a circuit diagram of an image processing apparatus according to an embodiment of the present invention; The figure shows the color reading sensor and drive pulses, Figure 4 is a circuit diagram for generating ODRV118a and EDRV119a, Figure 5 is a diagram explaining black correction operation, Figure 6 is a circuit diagram for shading correction, and Figure 7 is a color conversion block diagram, FIG. 8 is a color detection block diagram, FIG. 9 is a block diagram of a color conversion circuit, FIG. 10 is a diagram showing a specific example of color conversion, and FIG. 11 is a diagram explaining logarithmic conversion. , Figure 12 is a circuit diagram of the color correction circuit, Figure 13 is a diagram showing the unnecessary transmission area of the filter, Figure 14 is a diagram showing the unnecessary transmission area of the filter.
The figure shows unnecessary absorption components of the filter, Figure 15 is a circuit diagram of a character image area separation circuit, Figure 16 is a diagram explaining the concept of contour regeneration, and Figure 17 explains the concept of contour regeneration. Figure 18 is a contour regeneration circuit diagram, Figure 19 is a contour regeneration circuit diagram, Figure 20 is a timing chart of ENI and EN2,
Figure 1 is a block diagram of the character image correction section, Figure 22 is an explanatory diagram of addition/subtraction processing, Figure 23 is a switching signal generation circuit diagram, Figure 24 is a circuit diagram of color residual removal processing, and Figure 25 is color residual removal processing. , Figure 26 is a diagram showing edge emphasis, Figure 27 is a diagram showing smoothing, Figure 28 is a diagram explaining processing and modification processing using binary signals, Figure 29 is a diagram explaining text, Figure 30 is a block diagram of the image editing circuit, Figure 31 is a diagram showing texture processing, Figure 32 is a circuit diagram of texture processing, Figure 33 is a diagram of mosaic, scaling, and tapering processing. A circuit diagram, FIG. 34 is a circuit diagram of mosaic processing, FIG. 35 is a diagram explaining mosaic processing, etc., FIG. 36 is a circuit diagram of the line memory address control section, FIG. 37 is an explanatory diagram of the mask bit memory, Fig. 38 is a diagram showing addresses, Fig. 39 is a diagram showing a specific example of a mask, Fig. 40 is a circuit diagram of an address counter, Fig. 41 is a timing chart for enlargement and reduction, and Fig. 42 is a diagram for enlargement and reduction. Figure 43 is an explanatory diagram of the binarization circuit, Figure 44 is a timing chart of the address counter, Figure 45 is a diagram showing a concrete example of bitmap memory writing, Figure 46 is a diagram showing characters and images. Figure 47 is a diagram showing a specific example of synthesis, Figure 47 is a circuit diagram of distribution switching, Figure 48 is a diagram showing a specific example of a nonlinear mask, Figure 49 is a circuit diagram of a region signal generation circuit, and Figure 50 is a diagram of a region generated by a digitizer. Figure 51 is an interface circuit diagram with external equipment, Figure 52 is a selector truth table, Figure 53 is a diagram showing examples of rectangular areas and non-rectangular areas, Figure 54 is a diagram showing designation.
55 is a diagram explaining the procedure of color conversion operation, FIG. 56 is a diagram explaining the procedure of specifying the trimming area, FIG. 57 is a diagram explaining the procedure of specifying the trimming area, Figure 58 is a diagram showing the algorithm for specifying a circular area.
Figure 9 is a diagram showing the algorithm for specifying areas of ellipses and R rectangles, Figure 60 is an explanatory diagram of the operating procedure for character composition, Figure 61 is an explanatory diagram of the operating procedure for character composition, and Figure 62 is an illustration of the operation procedure for character composition. Figure 63 is a diagram explaining the procedure of texture processing, Figure 64 is a diagram explaining the procedure of mosaic processing, Figure 65 is a diagram explaining the procedure of yellow mode operation, Figure 66 is a diagram explaining the procedure of operation procedure.
Figure 67 is a diagram explaining the program memory operation procedure. Figure 68 is a diagram explaining the program memory operation procedure. Figure 69 is a diagram explaining the program memory registration algorithm. FIG. 70 is a diagram showing the algorithm of the operation after calling the program memory, and FIG. 71 is a diagram showing the format of the recording table.

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Claims (2)

[Claims] (1) Means for emphasizing high frequency components in the spatial frequency with respect to an input image signal, a plurality of average value calculation means for respectively calculating the average value within a plurality of masks having different sizes of the emphasized image signal, An image processing device characterized by comprising: means for determining whether or not an image portion exists by comparing average values. (2) The image processing apparatus according to claim 1, wherein the masks of different sizes are a 3×3 pixel block and a 5×5 pixel block.