JPH10284703A - Semiconductor storage device and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a contact area sufficient, without increasing the resistance by constituting the first and second contact wirings of an upper layer of bit line and a reverse bit line, and extending them at least to the facing edge parts of the lower layer of bit line and the reverse bit line. SOLUTION: Conductive layers 5 and 6 for contact made in contact formation areas A and B are made in the upper layers of conductive wirings 1 (1) and 2 (1), and these conductive layers 5 and 6 for contact are extended to the edge parts 3 and 4 of 1 (2) and 2 (2) of the lower layer. Therefore, for the contact between the upper layer and the lower layer, they are in contact with each other over a wide area, so that it becomes possible to suppress the contact resistance, and this becomes effective in the case where the downsizing of the contact area by minimum wiring design is required. As a result, to the bit line where a feeble current is flowing, this can be sensed with a sense amplifier at high speed and fully, so that a highly reliable product can be supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a bit line pair having a two-layer conductive wiring structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 is a side view of a semiconductor memory device having a twisted bit line pair having a general two-layer conductive layer wiring structure and a sense amplifier connected to the bit line pair. It shows. In FIG. 7, reference numeral 81 denotes a bit line, and 82 denotes an inverted bit line (the inverted bit line may be reversed). These constitute a bit line pair, and these bit line pairs are made of conductive wiring such as polysilicon, tungsten or aluminum. Or a mixed wiring material thereof. One ends of these bit line pairs are connected to a sense amplifier 83. The bit line 81 is an upper bit line 81
(1) and a lower bit line 81 (2), and the inverted bit line 82 is composed of an upper inverted bit line 82 (1) and a lower inverted bit line 82 (2). A two-layer wiring structure is formed with an interlayer insulating film interposed. Upper bit line 81 (1) and upper inverted bit line 82
Each of (1) is led to the lower bit line 81 (2) and the lower inverted bit line 82 (2) in the twist region 80. The twist region 80 will be described later in detail with reference to FIGS. Bit lines 81 and inverted bit lines 82 are provided with conductive wirings 81 (2) and 82
The memory cell 84 is connected to (2). The memory cell 84 comprises a transfer gate 84 (1) connected to a bit line or an inverted bit line and a memory capacitor 84 (2) connected to the transfer gate 84 (1). All the gates of the gate 84 (1) are connected to the word line 86. FIG. 8 is a plan view of the side view shown in FIG. 7. 81 (1) and 82 (1) correspond to the upper bit line and inverted bit line wiring layers, respectively, and 81 (2) and 82 (2) correspond to the lower bit line and inverted bit line wiring layers, respectively. These wiring layers form upper wirings 81 in the twisted region 80.
(1) is connected to the lower wiring 81 (2) by a contact 90, and the upper wiring 82 (1) is connected to the lower wiring 8 (1).
2 (2) and the contact 91. From this plan view, it can be understood that a structure in which the upper layer and the lower layer are exchanged in the twisted region 80 in the bit line pair having the two-layer structure. Further, FIG. 9 is a cross-sectional view taken along the line CC of FIG. 8 showing a plan view, and FIG. 10 is a cross-sectional view taken along the line BB of FIG. 2 explained so far
It seems that the sectional structure of the layer conductive wiring can be understood more clearly. In the cross-sectional structure of FIG. 9, the upper wiring 81 (1)
A lower wiring 82 (2) is formed below the semiconductor device 100 via an interlayer insulating film 101, and the lower wiring 82 (2) is formed on the semiconductor substrate 100 via the insulating film. In the cross-sectional structure of FIG. 10, in addition to FIG.
A cross section 110 of FIG. This contact wiring 11
0 indicates that after the interlayer insulating film 101 is formed on the lower wirings 81 (2) and 82 (2), contact holes are formed at predetermined positions on these lower wirings and a conductive material is buried therein. Upper wirings 81 (1) and 82 (1) are formed.

[0003]

In the formation of the contact 90 in the twisted region 80 according to the prior art, it is difficult to align the mask with the reduction of the bit line width. Large contacts will be required. As a result, high integration becomes difficult. Also,
Along with the high integration, it is necessary to reduce the contact area by a minimum wiring design, and therefore, it is difficult to form a contact with the conventional technology. Further, when the buried contact according to the prior art is used, the number of steps for the lamination step of the buried element increases, which causes a problem in cost. The present invention has been made in view of the above-described problems, and has two types of different signal wirings.
It is an object of the present invention to provide a semiconductor memory device having a contact wiring capable of easily and sufficiently increasing the contact area of each signal wiring by processing one contact hole, and a method of manufacturing the same.

[0004]

According to the present invention, in a structure in a twisted region of a bit line pair having a two-layer conductive wiring structure, a first contact wiring for connecting a lower bit line and an upper bit line is provided. And each of the second contact lines connecting the lower-layer inverted bit line and the lower-layer inverted bit line comprises the upper-layer bit line and the inverted bit line, and these contact lines are formed by the lower-layer bit line and the inverted bit line. Since it extends at least to the opposite edge portion of the bit line, it is possible to supply a contact that can increase the contact area without increasing the resistance.

In the manufacturing method, the lower bit line and the inverted bit line and the upper bit line and the inverted bit line are respectively connected to the interlayer insulating film on the lower bit line and the inverted bit line. After forming a wiring material for forming a bit line and an inverted bit line formed in an upper layer on the interlayer insulating film and in the contact hole, a lower bit line and an inverted bit line are formed. In order to form a contact region by etching away the wiring material existing between the bit line and the bit line, even if a reduction in the contact area due to a minimum wiring design is required due to high integration, the contact Forming processing becomes easy. In addition, the number of contact hole filling steps is reduced as compared with the related art, so that the cost problem can be solved.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. Note that the same reference numerals are used for the same portions. FIG. 1 is a plan view of the side view shown in FIG. 8, and has a twisted region 8 having features of the present invention.
FIG. 7 is a diagram for explaining 0 in detail. Further, FIG.
FIG. 3 is a cross-sectional view taken along a line −A.

Reference numerals 1 (2) and 2 (2) denote lower bit line and inverted bit line wiring layers formed on the semiconductor substrate 100 with the insulating film 8 interposed therebetween, respectively.
(1) is an upper bit line formed in parallel with the lower wiring via an interlayer insulating film 7 on the lower bit line 1 (2) and the inverted bit line wiring layer 2 (2). And an inverted bit line wiring layer.

In the twisted region 80, the upper layer and the lower wiring layer are connected such that the upper layer 1 (1) is connected to the lower layer 1 (2) at the contact area A, and the upper layer 2 (1) is connected to the lower layer 2 (1).
(2) is connected in the contact region B. Contact conductive layer 5 formed in contact formation regions A and B
And 6 are the upper conductive wires 1 (1) and 2
The contact conductive layers 5 and 6 extend to the edge portions 3 and 4 of the lower layers 1 (2) and 2 (2). For this reason, since the contact between the upper layer and the lower layer is in contact with a larger area than in the related art, the contact resistance can be suppressed. This is effective when the contact area needs to be reduced due to the minimum wiring design. In addition, since the contact wiring is constituted by the wiring of the upper layer, it is possible to suppress the contact resistance and the wiring resistance from increasing in this respect as well,
As a result, a bit line through which a small current flows can be sensed at high speed and sufficiently by the sense amplifier, and a highly reliable product can be supplied. Next, steps up to the cross-sectional view of FIG. 2 will be described with reference to FIGS. A conductive material for a lower wiring layer is deposited on a semiconductor substrate with an insulating film 8 interposed therebetween, and then the conductive material is deposited on the lower bit line 1.
Etching is performed to form (2) and the inverted bit line 2 (2). Thereafter, the interlayer insulating film 7 is formed on the insulating film 8,
On lower wiring layers 1 (2) and 2 (2), and lower wiring layer 1
It is formed on the interlayer insulating film 7 between (2) and 2 (2). Thereafter, a resist is deposited on the interlayer insulating film 7 and patterned, and then the contact region C including the contact formation regions A and B is exposed by RIE etching 19 using the patterned resist 20 as a mask. Next, after the resist 20 is stripped, a conductive material 23 for forming an upper wiring layer is laminated on the interlayer insulating film 7 and the lower wiring layers 1 (2) and 2 (2). I do. (Refer to FIG. 4) Next, a resist 25 is deposited on the conductive material 23 and patterned. (Refer to FIG. 5.) Thereafter, the upper wirings 1 (1) and 2 (1) are formed by RIE etching 24, and at the same time, the extra conduction on the interlayer insulating film 7 between the lower wiring layers 1 (2) and 2 (2). The conductive material is removed, and contact formation regions A and B are formed. (FIG. 4
Note that, at this time, it is needless to say that the object of the present invention can be achieved by etching the upper layer wiring after processing the contact region. According to the method of manufacturing the semiconductor memory device described above, the margin of mask alignment increases with the reduction of the bit line width, so that it is not necessary to form a contact region larger than the minimum wiring width in consideration of the shift,
As a result, high integration is possible. In addition, even if a reduction in the contact area due to the minimum wiring design is required due to the high integration, the hole forming diameter can be increased by the manufacturing method of the present invention, and the contact forming processing becomes very easy. Furthermore, in the process of the prior art, since a buried contact is used, the number of processes for the burying element lamination process is increased and a problem of cost arises. However, in the present invention, a process for the buried contact is separately provided. Since it can be formed at the same time as the processing of the upper wiring layer without performing, the problem of high cost due to an increase in the number of steps can also be solved.

[0009]

According to the present invention, it is possible to improve the difficulty in mask alignment due to the reduction in bit line width. Further, it is not necessary to form a contact larger than the minimum wiring width in consideration of the shift. For this reason, high integration is possible.
In addition, even if a reduction in the contact area due to the minimum wiring design is required due to the high integration, the contact formation processing becomes easier as compared with the related art. Furthermore, since the contact region can be formed without increasing the number of steps for stacking the buried elements, the problem of cost increase due to an increase in the number of steps can be improved.

[Brief description of the drawings]

FIG. 1 is a side view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is a sectional view showing a manufacturing process showing a method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process illustrating the method for manufacturing the semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a manufacturing process sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the present invention;

FIG. 6 is a manufacturing process sectional view showing the method of manufacturing the semiconductor memory device according to the embodiment of the present invention;

FIG. 7 is a plan view of a semiconductor memory device having a twisted bit line pair having a general two-layer conductive layer wiring structure.

FIG. 8 is a side view of FIG. 7;

FIG. 9 is a sectional view taken along the line CC in FIG. 8;

FIG. 10 is a sectional view taken along the line BB in FIG. 8;

[Explanation of symbols]

 1 (1) Upper bit line 1 (2) Lower bit line 2 (1) Upper inverted bit line 2 (2) Lower inverted bit line 3, 4 Edge portion in the longitudinal direction of lower wiring 5, 6 Contact wiring Reference Signs List 7 interlayer insulating film 8 oxide insulating film 20, 25 resist 23 conductive material for upper layer 80 twisted region 81 (1) upper bit line 81 (2) lower bit line 82 (1) upper inverted bit line 82 (2) Lower layer inverted bit line 83 Sense amplifier 84 Memory cell 85 Word line 90 Contact 100 Semiconductor substrate

Claims (7)

[Claims] In a semiconductor memory device having a bit line pair having a two-layer conductive wiring structure, a first and a second edge are provided in parallel with a predetermined interval on an insulating film with respect to a longitudinal direction. First and second lower conductive wiring layers having third and fourth edges, respectively, and wherein the first and third edges are formed in opposition to each other;
Formed through an interlayer insulating film on the lower conductive wiring layer,
A third and a fourth upper conductive wiring layer provided in parallel with the first and the second lower conductive wiring layers in a vertical relationship, the first lower conductive wiring layer and the third upper conductive layer; A first contact wiring for connecting to the conductive wiring layer, and a second contact wiring for connecting the second lower conductive wiring layer and the fourth upper conductive wiring layer. , The first and second contact wires are respectively connected to the third
And a fourth upper conductive wiring layer, and extending at least to first and third edges in opposition to the first and second lower conductive wiring layers. Storage device. 2. The first lower conductive wiring layer and the third lower conductive wiring layer
, A bit line is constituted by the upper conductive wiring layer, and an inverted bit line is constituted by the second lower conductive wiring layer and the fourth upper conductive wiring layer. 2. The semiconductor memory device according to claim 1, wherein one bit line pair is formed. 3. The semiconductor memory device according to claim 1, wherein a memory cell is connected to said first conductive wiring and said second conductive wiring via a transfer gate. 4. The semiconductor memory device according to claim 1, wherein the other ends of said first lower conductive wiring layer and said third upper conductive wiring layer are connected to a sense amplifier. 5. A method for manufacturing a semiconductor memory device having a bit line pair having a two-layer conductive wiring structure formed with an interlayer insulating film interposed therebetween. And forming a second lower conductive wire;
On these first and second conductive wirings, the first and second conductive wirings are formed.
Forming an interlayer insulating film between the conductive wires and on the insulating film, and forming a contact hole for connecting an upper conductive wire to each of the first and second conductive wires, The interlayer insulating film on the first and second conductive wirings and the interlayer insulating film between the first and second conductive wirings are removed, and a part of the first and second conductive wirings and Simultaneously exposing the interlayer insulating film between the first and second conductive wires, and forming a conductive wiring material on the surface of the region where the interlayer insulating film has been removed and on the remaining interlayer insulating film. Patterning the resist, and removing the conductive wiring material on the interlayer insulating film between the exposed first and second conductive wirings with the patterned resist. Manufacturing of a semiconductor storage device characterized by the above-mentioned. Method. 6. A first bit line pair comprising a first conductive wiring and a second conductive wiring formed in parallel with an upper and lower positional relationship via an interlayer insulating film; A third conductive wiring formed in the same layer as the wiring, and an interlayer insulating film formed in parallel with the third conductive wiring in a vertical positional relationship with the third conductive wiring, and the same as the second conductive wiring; A second bit line pair including a fourth conductive line formed of one layer, and a first conductive line of the first bit line pair and a fourth conductive line of the second line pair And a contact wiring for connecting a second conductive wiring of the first bit line pair and a third conductive wiring of the second wiring pair, respectively. The first and third conductive wirings of the lower layer are formed on the interlayer insulating film on the first and third conductive wirings. The second of
And a contact hole for connecting the third conductive wiring respectively were formed simultaneously, and a wiring material for forming the second and fourth conductive wirings was formed on the interlayer insulating film and in the contact hole. Thereafter, the wiring material existing between the first and third conductive wirings and the wiring material on the interlayer insulating film are simultaneously etched to form the second and fourth conductive wirings. A method for forming a semiconductor memory device, comprising the steps of: 7. A method of manufacturing a semiconductor memory device having a bit line pair having a two-layer conductive wiring structure formed with an interlayer insulating film interposed therebetween, wherein a first line is formed on the insulating film in parallel with a predetermined interval. And forming a second lower conductive wire;
On these first and second conductive wirings, the first and second conductive wirings are formed.
Forming an interlayer insulating film between the conductive wires and on the insulating film, and forming a contact hole for connecting an upper conductive wire to each of the first and second conductive wires, The interlayer insulating film on the first and second conductive wirings and the interlayer insulating film between the first and second conductive wirings are removed, and a part of the first and second conductive wirings and Simultaneously exposing the interlayer insulating film between the first and second conductive wires, and forming a conductive wiring material on the surface of the region where the interlayer insulating film has been removed and on the remaining interlayer insulating film. Patterning the resist, removing the conductive wiring material on the interlayer insulating film between the exposed first and second conductive wirings with the patterned resist, and removing the conductive property of the upper layer. Simultaneously forming the wiring layer and Method of manufacturing a semiconductor memory device characterized by Bei was.