KR20050067507A - Fabricating method of contact in semiconductor device - Google Patents
Fabricating method of contact in semiconductor device Download PDFInfo
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- KR20050067507A KR20050067507A KR1020030098492A KR20030098492A KR20050067507A KR 20050067507 A KR20050067507 A KR 20050067507A KR 1020030098492 A KR1020030098492 A KR 1020030098492A KR 20030098492 A KR20030098492 A KR 20030098492A KR 20050067507 A KR20050067507 A KR 20050067507A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 상/하부 전도막 간의 콘택 형성방법에 관한 것으로, 상부전도막을 마스크로 사용하며, 상부전도막의 측면을 콘택면으로 이용하여 스케일 다운(scale down)을 가능케한 발명이다. 이를 위한 본 발명은, 반도체 기판 상에 하부 전도막과 층간절연막을 적층 형성하는 단계; 상기 층간절연막 상에 상부 전도막을 형성하는 단계; 상기 상부전도막을 마스크로 사용하여 상기 층간절연막을 관통하여 상기 하부전도막을 노출시키는 콘택홀을 형성하되, 상기 상부전도막의 일 측면에 정렬되는 콘택홀을 형성하는 단계; 및 상기 상부전도막의 측면을 콘택면으로 이용하도록 상기 콘택홀 내부를 전도물질로 매립하는 단계를 포함하여 이루어 진다. 또한, 본 발명은 반도체 기판 상에 하부 전도막과 층간절연막을 적층 형성하는 단계; 상기 층간절연막 상에 상부 전도막을 형성하는 단계; 상기 상부전도막 및 상기 층간절연막을 관통하여 상기 하부전도막을 노출시키는 콘택홀을 형성하는 단계; 및 관통된 상기 상부전도막의 내벽을 콘택면으로 이용하도록 상기 콘택홀 내부를 전도물질로 매립하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact between upper and lower conductive films of a semiconductor device, wherein the upper conductive film is used as a mask and the side of the upper conductive film is used as a contact surface to enable scale down. To this end, the present invention comprises the steps of laminating a lower conductive film and an interlayer insulating film on a semiconductor substrate; Forming an upper conductive film on the interlayer insulating film; Forming a contact hole through the interlayer insulating film to expose the lower conductive film using the upper conductive film as a mask, the contact hole being aligned with one side of the upper conductive film; And embedding the inside of the contact hole with a conductive material to use the side surface of the upper conductive film as a contact surface. In addition, the present invention comprises the steps of laminating a lower conductive film and an interlayer insulating film on a semiconductor substrate; Forming an upper conductive film on the interlayer insulating film; Forming a contact hole through the upper conductive layer and the interlayer insulating layer to expose the lower conductive layer; And embedding the inside of the contact hole with a conductive material to use the inner wall of the upper conductive film penetrated as a contact surface.
Description
본 발명은 상부전도막과 하부전도막간의 인터커넥션 방법에 관한 것으로, 특히 공정순서를 변경하고, 상부전도막의 측면을 콘택면으로 활용하여 반도체 소자의 스케일 다운(scale down)을 가능케한 발명이다.The present invention relates to an interconnection method between an upper conductive film and a lower conductive film. In particular, the present invention enables a scale-down of a semiconductor device by changing a process order and utilizing side surfaces of the upper conductive film as contact surfaces.
도1a 내지 도1c 는 종래기술에 따라 하부 전도막(11)과 상부 전도막(14)을 전기적으로 연결시키기 위한 콘택 형성방법을 도시한 공정단면로서, 이를 참조하여 종래기술을 설명하면 다음과 같다. 1A to 1C are process cross-sectional views illustrating a method for forming a contact for electrically connecting the lower conductive film 11 and the upper conductive film 14 according to the prior art, which will be described below with reference to the related art. .
먼저, 반도체 기판(10) 상에 알루미늄 등의 전도물질을 증착하고 이를 패터닝하여 하부 전도막(11)을 형성하고, 이어서 하부 전도막(11) 상에 층간절연막(12)을 형성한다. First, a conductive material such as aluminum is deposited on the semiconductor substrate 10 and patterned to form a lower conductive film 11, and then an interlayer insulating film 12 is formed on the lower conductive film 11.
다음으로 도1b에서 처럼 층간절연막(12)을 선택적으로 제거하여 하부전도막(11)이 노출되는 콘택홀(13)을 형성한다. Next, as shown in FIG. 1B, the interlayer insulating film 12 is selectively removed to form a contact hole 13 through which the lower conductive film 11 is exposed.
다음으로 콘택홀(13) 내부를 플러그 등의 전도물질로 채운 뒤, 플러그와 접속하는 상부 전도막용 전도물질을 층간절연막 상에 형성하고 이를 패터닝하여 상부 전도막을 완성한다. 또는, 플러그 물질을 사용하는 대신에 상부전도막용 전도물질로 콘택홀 내부를 매립하여 사용할 수도 있다. Next, after filling the inside of the contact hole 13 with a conductive material such as a plug, a conductive material for the upper conductive film to be connected to the plug is formed on the interlayer insulating film and patterned to complete the upper conductive film. Alternatively, instead of using a plug material, the contact hole may be embedded with a conductive material for the upper conductive film.
이와같이 종래기술에서는 하부 전도막 형성 후, 하부전도막을 덮는 층간절연막을 형성하였다. 이후에, 층간절연막을 관통하여 하부전도막과 접속되는 콘택을 형성한 다음, 상부 전도막을 형성하였다.As described above, in the prior art, after the lower conductive film is formed, an interlayer insulating film covering the lower conductive film is formed. Thereafter, a contact was formed through the interlayer insulating film and connected to the lower conductive film, and then an upper conductive film was formed.
도2는 전술한 바와같은 종래기술에 따른 인터커넥션 방법을 도시한 평면도로서 이를 참조하면, 종래기술에서는 각각의 디자인 룰(design rule)이 요구되므로, 레이어간 스페이스가 많이 필요하게 되어(예를 들면, 도2의 콘택 오버랩 마진 : a로 표시) 소자의 스케일 다운 측면 및 이물질 발생측면에서 불리한 점이 많았다.2 is a plan view illustrating an interconnection method according to the related art as described above. Referring to this, since each design rule is required in the prior art, a large amount of space between layers is required (for example, The contact overlap margin of FIG. 2 is indicated by a) There are many disadvantages in terms of scale down and foreign matter generation.
본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 상부 전도막의 일부를 마스크로 사용하며, 상부 전도막의 측면을 콘택면으로 이용하여 스케일 다운을 가능케한 반도체 소자의 콘택 형성방법을 제공함을 그 목적으로 한다. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a method for forming a contact of a semiconductor device using a portion of an upper conductive film as a mask and using a side surface of the upper conductive film as a contact surface. It is done.
상기한 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 하부 전도막과 층간절연막을 적층 형성하는 단계; 상기 층간절연막 상에 상부 전도막을 형성하는 단계; 상기 상부전도막을 마스크로 사용하여 상기 층간절연막을 관통하여 상기 하부전도막을 노출시키는 콘택홀을 형성하되, 상기 상부전도막의 일 측면에 정렬되는 콘택홀을 형성하는 단계; 및 상기 상부전도막의 측면을 콘택면으로 이용하도록 상기 콘택홀 내부를 전도물질로 매립하는 단계를 포함하여 이루어진다.The present invention for achieving the above object comprises the steps of laminating a lower conductive film and an interlayer insulating film on a semiconductor substrate; Forming an upper conductive film on the interlayer insulating film; Forming a contact hole through the interlayer insulating film to expose the lower conductive film using the upper conductive film as a mask, the contact hole being aligned with one side of the upper conductive film; And filling the inside of the contact hole with a conductive material so as to use a side surface of the upper conductive film as a contact surface.
또한, 본 발명은, 반도체 기판 상에 하부 전도막과 층간절연막을 적층 형성하는 단계; 상기 층간절연막 상에 상부 전도막을 형성하는 단계; 상기 상부전도막 및 상기 층간절연막을 관통하여 상기 하부전도막을 노출시키는 콘택홀을 형성하는 단계; 및 관통된 상기 상부전도막의 내벽을 콘택면으로 이용하도록 상기 콘택홀 내부를 전도물질로 매립하는 단계를 포함하여 이루어진다.In addition, the present invention includes the steps of laminating a lower conductive film and an interlayer insulating film on a semiconductor substrate; Forming an upper conductive film on the interlayer insulating film; Forming a contact hole through the upper conductive layer and the interlayer insulating layer to expose the lower conductive layer; And embedding the inside of the contact hole with a conductive material to use the inner wall of the upper conductive film penetrated as a contact surface.
본 발명의 일실시예에서는 하부 전도막과 층간절연막을 차례로 형성한 다음, 콘택을 형성하지 않고 곧바로 상부 전도막을 형성하여 주었다. 이후에, 상부 전도막을 마스크로 사용하여 상부 전도막의 측면을 콘택면으로 이용하는 콘택을 형성하여 상부 전도막과 하부 전도막을 전기적으로 연결시켰다.In one embodiment of the present invention, the lower conductive film and the interlayer insulating film were formed in turn, and then the upper conductive film was formed immediately without forming a contact. Thereafter, using the upper conductive film as a mask to form a contact using the side surface of the upper conductive film as a contact surface to electrically connect the upper conductive film and the lower conductive film.
이와같은 본 발명의 일실시예에 따르면, 상부 전도막의 측면을 콘택면으로 사용하므로, 콘택면의 면적이 증가되며 또한, 콘택 오버랩 마진에 여유가 생기는 만큼, 상부 전도막의 면적을 감소시킬 수 있었다. According to the exemplary embodiment of the present invention, since the side surface of the upper conductive film is used as the contact surface, the area of the contact surface is increased and the area of the upper conductive film can be reduced by increasing the margin of contact overlap.
그리고, 본 발명의 제 2 실시예에서는 상부 전도막까지 모두 형성한 다음, 상부 전도막을 관통하는 콘택을 형성하여 줌으로써, 콘택 오버랩 마진의 변화는 없으나, 콘택면적의 증대를 통해 전기적 특성을 향상시킬 수 있었다. In the second embodiment of the present invention, all the upper conductive film is formed and then the contact penetrates the upper conductive film, so that there is no change in the contact overlap margin, but the electrical properties can be improved by increasing the contact area. there was.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.
도3a 내지 도3c는 본 발명의 제 1 실시예에 따른 콘택 형성공정을 도시한 공정단면도로서, 이를 참조하여 본 발명의 제 1 실시예를 설명하면 다음과 같다.3A to 3C are cross-sectional views illustrating a process for forming a contact according to a first embodiment of the present invention. Referring to this, a first embodiment of the present invention will be described below.
먼저, 도3a에 도시된 바와같이 반도체 기판(20) 상에 하부 전도막용 전도물질을 형성하고 이를 패터닝하여 하부 전도막(21)을 형성한다. 다음으로 하부전도막 (21)상에 층간절연막(22)을 적층형성 한 후, 층간절연막(22) 상에 상부 전도막용 전도물질(23)을 적층 형성한다.First, as shown in FIG. 3A, the lower conductive layer conductive material 21 is formed on the semiconductor substrate 20 and patterned to form the lower conductive layer 21. Next, after the interlayer insulating film 22 is laminated on the lower conductive film 21, an upper conductive film conductive material 23 is laminated on the interlayer insulating film 22.
다음으로 도3b에 도시된 바와같이 적절한 마스크(24)를 이용하여 상부 전도막용 전도물질을 패터닝하여 상부 전도막(23)을 완성한다. Next, as illustrated in FIG. 3B, the upper conductive film 23 is completed by patterning the conductive material for the upper conductive film using an appropriate mask 24.
이어서, 도3c에 도시된 바와같이 상부 전도막(23)을 마스크로 사용하여 층간절연막(22)을 선택적으로 식각하여, 상부 전도막(23)의 측면에 정렬(aligned)되며 하부 전도막(21)을 노출시키는 콘택홀을 형성한다. 다음으로 콘택홀 내부를 전도물질(24)로 채워서 상부 전도막(23)과 하부 전도막(21)을 전기적으로 연결시킨다.Subsequently, as shown in FIG. 3C, the interlayer insulating film 22 is selectively etched using the upper conductive film 23 as a mask to align the side surface of the upper conductive film 23 and the lower conductive film 21. To form a contact hole exposing Next, the inside of the contact hole is filled with a conductive material 24 to electrically connect the upper conductive layer 23 and the lower conductive layer 21.
이와같이 본 발명의 제 1 실시예에서는 상부 전도막(23)의 측면을 콘택면으로 활용하고 있어, 콘택면의 면적을 증가시킬 수 있었다. 통상적으로 알루미늄 등으로 이루어진 금속배선은 그 높이가 상당하기 때문에, 금속배선의 높이에 비례하는 면적을 콘택면으로 이용할 수 있어 콘택면적의 증가를 이룰 수 있었다.As described above, in the first embodiment of the present invention, the side surface of the upper conductive film 23 is used as the contact surface, so that the area of the contact surface can be increased. In general, since a metal wiring made of aluminum or the like has a considerable height, an area proportional to the height of the metal wiring can be used as the contact surface, thereby increasing the contact area.
또한, 본 발명의 제 1 실시예에서는 콘택 오버랩 마진(contact overlap margin)의 여유가 생긴만큼, 상부전도막의 면적을 감소시킬 수 있었다. 이를 도4를 참조하여 설명한다.In addition, in the first embodiment of the present invention, the area of the upper conductive film was reduced as much as there was a margin of contact overlap margin. This will be described with reference to FIG. 4.
도4는 본 발명의 제 1 실시예에 따른 인터커넥션 방법을 도시한 평면도로써 이를 참조하면, 상부 전도막(23)의 일 측면에만 정렬되어 콘택이 형성되고 있기 때문에 요구되는 콘택 오버랩은 종래기술보다 절반으로 감소하였다.4 is a plan view illustrating an interconnection method according to a first exemplary embodiment of the present invention, and since the contact is formed by being aligned only on one side of the upper conductive layer 23, the required contact overlap is more than that of the prior art. Decreased by half.
즉, 종래에는 도4에서 점선으로 표시된 만큼의 너비를 갖는 상부 전도막이 필요하였으나, 본 발명의 제 1 실시예에서는 상부 전도막의 너비를 종래보다 절반으로 감소시킬 수 있어, 전체적인 상부전도막의 면적을 감소시킬 수 있었다. That is, in the related art, the upper conductive film having the width as indicated by the dotted line in FIG. 4 is required. However, in the first embodiment of the present invention, the width of the upper conductive film can be reduced by half than before, thereby reducing the overall area of the upper conductive film. I could make it.
이와같은 본 발명의 기술적 사상을 적용하게 되면, 반도체 소자에 이용되는 금속배선의 면적을 획기적으로 감소시킬 수 있기 때문에, 소자의 스케일 다운 측면에서 큰 도음이 될 것이다.Applying the technical idea of the present invention, since it is possible to significantly reduce the area of the metal wiring used in the semiconductor device, it will be a great help in terms of scale down of the device.
다음으로 도5를 참조하여 본 발명의 제 2 실시예를 설명한다.Next, a second embodiment of the present invention will be described with reference to FIG.
본 발명의 제 2 실시예에서는 상부전도막을 관통하여 콘택을 형성함으로써 콘택 오버랩 마진의 변화는 없으나, 콘택면적을 넓힐 수 있는 발명이다.In the second embodiment of the present invention, the contact overlap margin is not changed by forming a contact through the upper conductive film, but the contact area can be increased.
즉, 도5를 참조하여 본 발명의 제 2 실시예를 설명하면 먼저, 반도체 기판 (30)상에 하부 전도막용 전도물질을 형성하고 이를 패터닝하여 하부 전도막(31)을 형성한다. 다음으로 하부전도막 (31)상에 층간절연막(32)을 적층형성 한 후, 층간절연막(32) 상에 상부 전도막용 전도물질을 적층 형성한다.That is, referring to FIG. 5, the second embodiment of the present invention will be described. First, the conductive material for the lower conductive film is formed on the semiconductor substrate 30 and patterned to form the lower conductive film 31. Next, after the interlayer insulating layer 32 is laminated on the lower conductive layer 31, an upper conductive layer conductive material is formed on the interlayer insulating layer 32.
다음으로 적절한 마스크를 이용하여 상부 전도막용 전도물질을 패터닝하여 상부 전도막(33)을 완성한다. Next, the conductive material for the upper conductive film is patterned using an appropriate mask to complete the upper conductive film 33.
이어서, 하부전도막(31)과 전기적으로 연결되는 콘택홀을 형성하되, 상부전도막(33)을 관통하는 콘택홀을 형성한다. 즉, 도5에 도시된 바와같이 상부전도막(33) 및 층간절연막(32)을 관통하는 콘택홀을 형성한 다음, 콘택홀 내부를 전도물질(34)로 매립한다.Subsequently, a contact hole electrically connected to the lower conductive film 31 is formed, and a contact hole penetrating the upper conductive film 33 is formed. That is, as shown in FIG. 5, a contact hole penetrating the upper conductive film 33 and the interlayer insulating film 32 is formed, and then the inside of the contact hole is filled with a conductive material 34.
본 발명의 제 2 실시예에서와 같이 콘택을 형성하게 되면, 콘택 오버랩 마진의 경우에는 종래기술과 비교하여 변화가 없으나, 대신 콘택면적이 크게 늘어나는 장점이 있다. When the contact is formed as in the second embodiment of the present invention, there is no change in the case of the contact overlap margin as compared with the prior art, but there is an advantage in that the contact area is greatly increased.
이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
본 발명을 적용하면, 스케일 다운된 소자 특히, 텅스텐실리사이드 워드라인과 텅스텐 비트라인과의 콘택에서 비트라인과 워드라인간의 콘택저항값이 급격히 증가하는 현상을 방지할 수 있어 신뢰성 있는 소자 제작이 가능하다. 특히, 최근 열공정의 변화에 따라 콘택 저항값이 급격히 변화하는 사례에 직접적으로 적용이 가능하다. According to the present invention, it is possible to prevent a sudden increase in the contact resistance value between the bit line and the word line in the contact between the scaled-down device, in particular, the tungsten silicide word line and the tungsten bit line, thereby making it possible to manufacture a reliable device. . In particular, it can be directly applied to the case where the contact resistance value changes rapidly with the recent change of the thermal process.
도1a 내지 도1c는 종래기술에 따른 상/하부 전도막간의 콘택 형성방법을 도시한 공정단면도,1A to 1C are cross-sectional views illustrating a method for forming a contact between upper and lower conductive films according to the prior art;
도2는 종래기술에 따른 인터커넥션 방법을 도시한 평면도,2 is a plan view illustrating an interconnection method according to the prior art;
도3a 내지 도3c는 본 발명의 제 1 실시예에 따른 상/하부 전도막 간의 콘택 형성방법을 도시한 공정단면도,3A to 3C are cross-sectional views illustrating a method for forming a contact between upper and lower conductive films according to a first embodiment of the present invention;
도4는 본 발명의 제 1 실시예에 따른 콘택 형성방법을 도시한 평면도,4 is a plan view showing a contact forming method according to a first embodiment of the present invention;
도5는 본 발명의 제 2 실시예에 따른 콘택 형성방법을 도시한 단면도.5 is a sectional view showing a contact forming method according to a second embodiment of the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
20 : 기판20: substrate
21 : 하부전도막21: lower conductive film
22 : 층간절연막22: interlayer insulating film
23 : 상부전도막23: upper conductive film
24 : 콘택24: Contact
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2003-0098492A KR100538814B1 (en) | 2003-12-29 | 2003-12-29 | Fabricating method of contact in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2003-0098492A KR100538814B1 (en) | 2003-12-29 | 2003-12-29 | Fabricating method of contact in semiconductor device |
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| KR20050067507A true KR20050067507A (en) | 2005-07-05 |
| KR100538814B1 KR100538814B1 (en) | 2005-12-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9111998B2 (en) | 2012-04-04 | 2015-08-18 | Samsung Electronics Co., Ltd | Multi-level stack having multi-level contact and method |
| US9287162B2 (en) | 2013-01-10 | 2016-03-15 | Samsung Austin Semiconductor, L.P. | Forming vias and trenches for self-aligned contacts in a semiconductor structure |
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2003
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9111998B2 (en) | 2012-04-04 | 2015-08-18 | Samsung Electronics Co., Ltd | Multi-level stack having multi-level contact and method |
| US10566234B2 (en) | 2012-04-04 | 2020-02-18 | Samsung Austin Semiconductor, Llc | Multi-level stack having multi-level contact and method |
| US9287162B2 (en) | 2013-01-10 | 2016-03-15 | Samsung Austin Semiconductor, L.P. | Forming vias and trenches for self-aligned contacts in a semiconductor structure |
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| KR100538814B1 (en) | 2005-12-23 |
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