JPH10284696A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the leakage of charge stored in the gate of an MOS-FET and enable the long term self-holding of data by a method, wherein a 1st bipolar transistor and a 2nd bipolar transistor are formed in a wide-gap semiconductor region. SOLUTION: An N-ch. MOS-FET 1 and a 1st N-P-N bipolar transistor 3 and a 2nd N-P-N bipolar transistor 2, which are formed in a wide gap semiconductor region, are provided. The collector of the 1st bipolar transistor 3 and the emitter of the 2nd bipolar transistor 2 are connected to the gate of the MOS-FET 1. The charging/discharging into/from the gate of the MOS-FET 1 is performed by the control of electrically continuity/discontinuity states between the collectors and emitters of the 1st bipolar transistor 3 and the 2nd bipolar transistor 2 for writing or erasing data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MOSFET (M
The present invention relates to a semiconductor memory device that stores data by accumulating electric charges in a gate of an OS type field effect transistor).

[0002]

2. Description of the Related Art As a conventional semiconductor memory device, for example, there is a DRAM having a circuit configuration shown in FIG. 4 is an Nch MOSFET formed on a silicon substrate.
101 and an Nch MOSFET 102. MO
The source of the SFET 101 is connected to the Vss terminal, and the drain is connected to the node Z. MOSFET102
One of the source or drain of the MOSFET 101
And the other is connected to the node X. The gate of the MOSFET 102 is connected to the node Y. The node Z is connected to a sense amplifier (not shown) via a bit line, and the node X is connected to a word line.

In the conventional semiconductor memory device shown in FIG.
The charge is stored in the gate of the OSFET 101, and the MOSFE
Data is stored by controlling on / off of T101.

When writing data, a Vdd potential is applied to a node Y to turn on the MOSFET 102 and a Vdd potential is applied to a node X. As a result, MOSFET
The electric charge is charged to the gate of the MOSFET 101 and the MOSFET 101
Is turned on.

On the other hand, when erasing data, a potential Vdd is applied to the node Y to turn on the MOSFET 102,
In addition, a Vss potential is applied to the node X. As a result, MO
The charge of the gate of the SFET 101 is discharged, and the MOSFE
T101 is turned off.

When reading data stored in the MOSFET 101, a Vss potential is applied to the node Y to
By turning off the FET 102 and selecting the node Z by a decoder circuit (not shown), the MOSFET 101
Is determined via a sense amplifier.

[0007]

In the storage device shown in FIG.
The MOSFET 102 is off except when writing data to the MOSFET 101 or erasing data. However, the gate charge of the MOSFET 101 flows out as a leak current of the PN junction constituting the MOSFET 102. Therefore, it is usually necessary to perform refresh once every 1 to 100 ms or once every 10 to 100 ms. For this reason, it cannot be used as a nonvolatile storage device, and of course, there is a problem that the refresh operation must be performed frequently and the circuit operation becomes complicated.

An object of the present invention is to provide a semiconductor memory device capable of holding data for a long time by itself.

[0009]

[Means for Solving the Problems]

(1) An embodiment will be described with reference to FIGS. 1 to 3 showing an embodiment.
1 and the first N formed in the wide gap semiconductor region.
The semiconductor device includes a PN-type bipolar transistor 3 and a second NPN-type bipolar transistor 2 formed in a wide-gap semiconductor region. The collector of the first bipolar transistor 3 and the emitter of the second bipolar transistor 2 are connected to the gate of the MOSFET 1. Then, by controlling the conduction / non-conduction state between the collector and the emitter of the first bipolar transistor 3 and the second bipolar transistor 2 to charge the gate of the MOSFET 1 or discharge the charge to write data, or At the time of erasing and holding data without writing and erasing data, the non-conductive state is established between the collector and emitter of the first bipolar transistor 3 and between the collector and emitter of the second bipolar transistor 2. The above Target is achieved. (2) The invention according to claim 2 is an Nch MOSFET
1, a diode 5 formed in the wide gap semiconductor region, and an NPN formed in the wide gap semiconductor region.
A bipolar transistor 3 having a collector connected to one end of the diode 5 so as to be forward with respect to the conduction direction between the emitter and the collector of the bipolar transistor 3. Is connected to the gate of the MOSFET 1 to control the conduction / non-conduction state between the collector and the emitter of the bipolar transistor 3 and the conduction / non-conduction state of the diode 5 to charge or discharge the gate of the MOSFET 1. At the time of writing or erasing data and holding data without writing or erasing data, the above-mentioned object is achieved by making the collector-emitter of the bipolar transistor 3 and the diode 5 non-conductive. . (3) According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the MOSFET 1 is formed in a silicon substrate. (4) The invention according to claim 4 is the first Nch MOS
An FET 7 and a second Nch MOSFET 6 formed in the wide gap semiconductor region.
Either the source electrode or the drain electrode of ET6 is connected to the gate of the first MOSFET 7, and the second
Of the first MOSFET 6 by controlling the source and drain of the second MOSFET 6 and controlling the other potential of the source electrode or the drain electrode of the second MOSFET 6.
Data writing or erasing is performed by charging or discharging the charge of the gate of T7, and at the time of holding data without writing or erasing data, a non-connection between the source and drain of the second MOSFET 6 is established. The above-described object is achieved by setting the conductive state. (5) The invention according to claim 5 is the semiconductor memory device according to claim 4, wherein the first MOSFET 7 is formed in a silicon substrate. (6) According to a sixth aspect of the present invention, in the semiconductor memory device according to any one of the first to fifth aspects, any one of GaAs, SiC, and thin-film diamond is used as the wide gap semiconductor region. .

In the section of the means for solving the above-mentioned problems, which explains the configuration of the present invention, the drawings of the embodiments of the present invention are used for easy understanding of the present invention. However, the present invention is not limited to this.

[0011]

According to the first aspect of the present invention, since the first bipolar transistor and the second bipolar transistor are formed in the wide gap semiconductor region, it is possible to suppress the leakage of the charge stored in the gate of the MOSFET. . According to the second aspect of the present invention, since the diode and the bipolar transistor are formed in the wide gap semiconductor region, it is possible to suppress the leakage of the charge accumulated in the gate of the MOSFET. According to the third aspect of the present invention, since the MOSFET is formed in the silicon substrate, the MOSFET can be easily formed. According to the fourth aspect of the present invention, since the second MOSFET is formed in the wide gap semiconductor region, the first MOSFET is formed.
Leakage of charges accumulated in the gate of the ET can be suppressed.
According to the fifth aspect of the present invention, since the first MOSFET is formed in the silicon substrate, the first MOSFET can be easily formed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment Hereinafter, a first embodiment of a semiconductor memory device according to the present invention will be described with reference to FIG.
An embodiment will be described.

In FIG. 1, reference numeral 1 denotes an Nch MOSF formed in a silicon semiconductor region or a wide gap semiconductor region having a wider band gap than the silicon semiconductor.
ET, 2 and 3 are NPN bipolar transistors formed in the wide gap semiconductor region. Here, as the wide gap semiconductor, for example, GaAs, S
iC, thin film diamond, or the like can be used.

As shown in FIG. 1, the source of the MOSFET 1 is connected to the Vss terminal, and the drain of the MOSFET 1 is connected to the node C. The collector of the bipolar transistor 2 is connected to the node D, and the base of the bipolar transistor 2 is connected to the node A.

The collector of the bipolar transistor 3 is connected to the emitter of the bipolar transistor 2, the emitter of the bipolar transistor 3 is connected to Vss, and the base of the bipolar transistor 3 is connected to the node B. Further, the emitter of the bipolar transistor 2 (collector of the bipolar transistor 3) is connected to the gate of the MOSFET 1. The node C is connected to a sense amplifier (not shown) via a bit line, and the node D is connected to a high potential terminal such as a Vdd terminal.

The operation of the semiconductor memory device according to the first embodiment configured as described above will now be described. First
In the semiconductor memory device according to the embodiment, data is stored in the gate of the MOSFET 1 and the MOSFET 1 is turned on (when charge is stored) or off (when charge is not stored). Is stored.

First, a method of turning on the MOSFET 1 to store data will be described. The Vdd potential is applied to the node A and the Vss potential is applied to the node B. Then, the bipolar transistor 2 is turned on, and the bipolar transistor 3 is turned off. Therefore, MOSFE
The gate potential of T1 is charged to the gate until the "Vdd-V _F" [v]. Therefore, the MOSFET 1 is turned on, and the data is stored. In addition,
"V _F" is a base-emitter voltage of the bipolar transistor 2, which is about 0.7 [V].

Next, a method for erasing data by turning off the MOSFET 1 will be described. It applies a potential Vss to node A, to apply a V _F potential at node B. Then, the bipolar transistor 2 is turned off, and the bipolar transistor 3 is turned on. Therefore MOSF
Since the electric charge stored in the gate of ET1 is discharged through the bipolar transistor 3, the gate potential of the MOSFET 1 decreases. Then, the potential of the node B is set to Vss.
When the voltage is lowered to the potential, the gate potential of the MOSFET 1 also becomes Vss.
The potential becomes the potential, and the MOSFET 1 is turned off. Therefore, the data is erased.

Next, a method of reading data stored in the MOSFET 1 will be described. The node A and the node B are set to the Vss potential, the node C is selected by a decoder circuit (not shown), and the MOSFET 1 and the sense amplifier are connected. The state of the MOSFET 1 is turned on in accordance with the stored data of the MOSFET 1 (presence / absence of a charge on the gate),
It is either off, but is read out via a sense amplifier.

Next, in the semiconductor memory device of the first embodiment, the reason why the refresh interval of the stored data can be extended or the refresh is not actually required will be described.

While data is being written to MOSFET 1, the gate potential of MOSFET 1 is "Vd
d−V _F ”[v]. After the data writing, both the node A and the node B are set to the Vss potential, so that the emitter-base junction of the bipolar transistor 2 and the collector-base junction of the bipolar transistor 3 are both reverse biased with respect to the gate of the MOSFET 1. Connected to. Therefore, the charge stored in the gate of MOSFET 1 flows out as a leak current at these junctions.

Generally, the leak current density of a PN junction is expressed by the following equations (1) to (3).

(Equation 1)

From [0023] Equation (1) to (3), as the value of the band gap E _G is greater, by the value of the intrinsic carrier density n _i is small, the leakage current density Js also decreases. For example, when a wide-gap semiconductor bipolar transistor 2 and a bipolar transistor 3 is formed of SiC, the value of E _G so is 3.2 [eV], the equation (3), the value of n _i is the case of the Si comparison Then 4.2
× 10 ^-18 times. Similarly if the wide-gap semiconductor is a thin film diamond, the value of E _G is 5.5 [eV]
Therefore, the value of n _i is 2.6 × 10 compared with the case of Si.
^-37 times.

Therefore, according to the equations (1) and (2), in the wide gap semiconductor, the leakage current at the PN junction is
Is significantly smaller than in the case of. Therefore, MOSF
The charge stored in the gate of the ET1 disappears very slowly, and the data stored in the MOSFET 1 is less likely to be destroyed. That is, the refresh interval of the stored data can be made very long. Or, in practice, there is no need to refresh and the device can be handled as a nonvolatile memory. For example, a DRAM having a Si PN junction normally refreshes every 10 to 100 [ms].
In contrast, the leakage current of the PN junction in the wide-gap semiconductor is 10 in the case of the PN junction of Si ^- reducing the ¹⁰ times (ETL News, September 1995, 548 No.,
P. 1 to P.P. Then, in the first embodiment, the refresh interval may be 3 to 30 years.

The storage device of the first embodiment is a conventional DR device.
Since charge and discharge of gate charge is performed through a semiconductor device in the same manner as AM or SRAM, it is compared with memories such as EEPROM and flash memory which charge and discharge gate charge by tunnel effect or hot electrons or drive a booster circuit. As a result, data writing and erasing can be performed at a speed as high as that of a conventional DRAM or SRAM. Therefore, the storage device of the first embodiment can be used as a working memory of the CPU, like the conventional DRAM and SRAM. In addition, in this case, even when an unexpected stop of the power supply voltage or the like occurs, the data in the working memory at that time can be retained, so that the operation of the CPU can be resumed and continued after the power supply voltage is restored. .

Unlike a ferroelectric memory, a material that is not easily used in a silicon process is not used, so that there is no disadvantage that a manufacturing process becomes extremely complicated or other semiconductor devices are adversely affected.

In the first embodiment, the MOSFET
1 need not necessarily be formed in a wide gap semiconductor, but may be formed in a normal silicon substrate. In a wide gap semiconductor, it may be difficult to form a MOSFET due to a difficulty in forming a high-quality gate oxide film or a large number of interface states at an interface between the gate oxide film and the substrate. Such a difficulty can be avoided if it is formed inside. Also, M
Since the leakage of the charge of the gate of the OSFET 1 is related to the PN junction of the bipolar transistor 2 and the bipolar transistor 3, if these bipolar transistors 2 and 3 are formed in a wide gap semiconductor, the MOSFET 1 is formed in a silicon substrate. In this case, the same performance as that of the first embodiment can be obtained.

As shown in FIG. 2, a diode 5 may be formed in a wide gap semiconductor in place of the bipolar transistor 2. Connect the anode of diode 5 to node A
By connecting the cathode of the diode 5 to the gate of the MOSFET 1 and the collector of the bipolar transistor 3, respectively, data can be stored and read in the same manner as in the storage device of the first embodiment. Also in this case, the bipolar transistor 1 and the diode 5 are formed in the wide gap semiconductor, so that the MOSFET 1 caused by the leakage current of the PN junction
Of the gate of the semiconductor device is suppressed.

Second Embodiment Hereinafter, a second embodiment of the semiconductor memory device according to the present invention will be described with reference to FIG.
An embodiment will be described.

In FIG. 3, reference numeral 6 denotes an Nch MOSFET formed in the wide gap semiconductor region, and 7 denotes an Nch MOSFET formed in the silicon substrate or in the wide gap semiconductor region. Either the source or the drain of the MOSFET 6 is connected to the gate of the MOSFET 7,
The other is connected to node E, respectively, and the gate of MOSFET 6 is connected to node D.

The source of the MOSFET 7 is connected to the Vss terminal, and the drain is connected to the node C. Node C is connected to a sense amplifier (not shown) via a bit line.

In the second embodiment, as in the first embodiment, the MOSFET 7 is turned on by accumulating electric charges in the gate of the MOSFET 7. And MOSFET
By controlling the on or off state of 7,
Store the data.

First, a method of storing data while the MOSFET 7 is kept on will be described. When the Vdd potential is applied to the nodes D and E to turn on the MOSFET 7, the gate potential of the MOSFET 7 becomes "Vd
Charges are accumulated in the gate until the voltage becomes d−Vth [v] ”. Here, “Vth” is the threshold voltage of the MOSFET 6.

Next, a method of erasing data while the MOSFET 7 is kept off will be described. V to node D
The dd potential is applied to turn on the MOSFET 6, and the Vss potential is applied to the node E. Then MOSFET7
Becomes the Vss potential, and the MOSFET 7 is turned off.

Next, a method of reading data stored in the MOSFET 7 will be described. Node D to Vs
s potential to turn off the MOSFET 6 and select a node C by a decoder circuit (not shown) to
The SFET 7 and the sense amplifier are connected. And MOS
The stored data (ON state or OFF state) of the FET 7 is read by the output of the sense amplifier.

The device of the second embodiment can also increase the refresh interval of the stored data for the same reason as in the first embodiment. Alternatively, the refresh is not actually required. That is, the node D is set to the potential Vss except when data is written or erased, so that the MOSFET 6 is turned off. For this reason, the electric charge stored in the gate of the MOSFET 7 flows as a leak current of the MOSFET 6, but the MO formed in the wide gap semiconductor
The leak current of the PN junction constituting the SFET 6 is extremely small as compared with the case of the PN junction using the silicon substrate as described in the first embodiment. For this reason, MOSFE
Since the speed at which the charge of the gate of T7 disappears becomes very slow,
The refresh interval can be lengthened, or the refresh becomes unnecessary. In addition, the first advantage is that high-speed writing and erasing operations can be performed, and manufacturing can be performed without using complicated processes.
This is the same as the embodiment.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing a modification of the storage device of the first embodiment.

FIG. 3 is a diagram illustrating a semiconductor memory device according to a second embodiment;

FIG. 4 is a diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

 1 MOSFET 2 Bipolar transistor 3 Bipolar transistor 5 Diode 6 MOSFET 7 MOSFET

Claims (6)

[Claims] An Nch MOSFET, a first NPN bipolar transistor formed in a wide-gap semiconductor region, and a second NPN bipolar transistor formed in a wide-gap semiconductor region; The collector of the transistor and the emitter of the second bipolar transistor are connected to the MO
And a continuity between a collector and an emitter of the first bipolar transistor and the second bipolar transistor.
Controlling the non-conducting state to charge the gate of the MOSFET, or writing or erasing data by discharging the charge, and at the time of holding data without writing and erasing the data, A semiconductor memory device, wherein the collector and the emitter of the first bipolar transistor and the collector and the emitter of the second bipolar transistor are non-conductive. 2. An Nch MOSFET, a diode formed in a wide gap semiconductor region, and an NPN type bipolar transistor formed in a wide gap semiconductor region, wherein a collector of the bipolar transistor is an emitter / collector of the bipolar transistor. One pole of the diode is connected so as to be in a forward direction with respect to the conduction direction between the bipolar transistor and the collector of the bipolar transistor is connected to the gate of the MOSFET, and the conduction and non-conduction between the collector and the emitter of the bipolar transistor are connected. A state of the diode and a conduction / non-conduction state of the diode are controlled to charge the gate of the MOSFET or discharge the charge to write or erase data, and to write and erase the data. To the time of data holding is not performed, the semiconductor memory device characterized by a non-conductive state between the collector and emitter and the diode of the bipolar transistor. 3. The semiconductor memory device according to claim 1, wherein said MOSFET is formed in a silicon substrate. 4. A first Nch MOSFET and a second Nch MOS formed in a wide gap semiconductor region.
An FET, wherein one of a source electrode and a drain electrode of the second MOSFET is connected to a gate of the first MOSFET, and the source and drain of the second MOSFET are electrically connected to each other. Controlling the potential of the other of the source electrode and the drain electrode of the
Writing or erasing data by charging or discharging the gate of the MOSFET, and holding the data without writing or erasing the data.・
A semiconductor memory device in which a drain is made non-conductive. 5. The semiconductor memory device according to claim 4, wherein said first MOSFET is formed in a silicon substrate. 6. The wide gap semiconductor region,
6. The semiconductor memory device according to claim 1, wherein one of GaAs, SiC and thin-film diamond is used.