JPH10284505A - Heterojunction bipolar transistor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an HBT having improved high-speed characteristics. SOLUTION: This method comprises the following steps. An epitaxial wafer is fabricated by sequentially forming a C-doped p-InGaAs base layer 204 and an InP layer 205 as uppermost layers on a semi-insulating InP substrate 200 by the organometallic vapor phase growth method. Next, the epitaxial wafer is annealed under the atmosphere of inert gas and a desired region of the base layer 204 is selectively exposed. A WSix film 222 is formed on the exposed portion of the base layer 204 to form a base electrode. Using the WSix film 222 as a mask, an InP emitter layer 206 is selectively grown on the InP layer 205.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a heterojunction bipolar transistor (hereinafter, referred to as HBT).

[0002]

2. Description of the Related Art In preparation for the coming of a multimedia society and an electronic society, it is necessary to increase the speed of a trunk optical communication network, which is the foundation of the society, to enable transmission of a larger amount of information. In order to realize a gigabit-class ultra-high-speed optical communication system for large-capacity data transmission, an ultra-high-speed electronic device used for an optical transceiver is indispensable. As an ultra-high-speed electronic device, HBT using a compound semiconductor has been put into practical use as a next-generation high-speed electronic device after HEMT,
In particular, a GaAs-based HBT has attained the performance as a 10 gigabit class device for the first time, and research and development are being conducted with the aim of further improving the characteristics.

As a promising structure for exhibiting the high-speed characteristics of the HBT, there is known a self-aligned HBT in which the distance between the emitter electrode and the base electrode can be reduced as much as possible. This self-alignment process will be described with reference to FIGS.
InP-based H that can be expected to have higher speed than GaAs-based
A description will be given using BT as an example. The steps are as follows. That is, 1) First, the emitter electrode 111 is formed on the n-InGaAs cap layer 103 of the epitaxial wafer (FIG. 2A). 2) Next, using this emitter electrode 111 as a mask,
The InP emitter layer 102 and n
An emitter mesa including the -InGaAs cap layer 103 is formed, and the p-InGaAs base layer 101 is exposed (FIG. 2B). At this time, an undercut portion 111a is generated immediately below the emitter electrode 111, and the emitter electrode 11
1 overhangs like "Hisashi". 3) Next, a base metal is vapor-deposited using the undercut portion 111a to form a base electrode 112 (FIG. 2C). When the base electrode 112 is formed in this manner, the InP emitter layer 102 and the base electrode 11 are formed.
2 can be avoided, and the distance between the base electrode 112 and the emitter electrode 111 can be narrowed in a self-aligned manner.

[0004]

However, the above-described InP-based HBT has the following problems. That is, 1) The etching shape of the semiconductor differs depending on the plane orientation of the crystal. Since only a specific crystal orientation can be formed as shown in FIG. 2, depending on the orientation different from that,
Since the emitter electrode and the base electrode are short-circuited, or the length of the hessian depends on the adhesion between the semiconductor and the electrode, it becomes difficult to control the width of the emitter layer, and the emitter resistance is not stable. There was a problem.

2) In recent years, in order to improve the high-speed characteristics of the HBT, a GaAs-based HBT uses carbon (C) as a dopant for the p-InGaAs base layer, realizes high-concentration doping, and increases the carrier density. , Has succeeded in lowering the base resistance. On the other hand, InP-based H
The study of BT was started later than GaAs,
The study was started based on the idea that C was effective as a dopant for the p-InGaAs base layer as in the case of the GaAs system. By the way, during the vapor phase growth of the C-doped InGaAs layer, H ions generated by the decomposition of a methyl group or the like in the source gas are taken into the InGaAs layer, and the C content becomes 5%.
Since a phenomenon (Hydrogen passivation) occurs in which holes released into the position of the group atom are reduced, it is not easy to increase the carrier density. This phenomenon becomes more remarkable when growing an InP-based p-InGaAs base layer than in the case of a GaAs base not containing In, and there is a problem that it is difficult to increase the carrier density of the base layer. .

[0006]

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is provided by a metal organic chemical vapor deposition method.
Carbon-doped p-In as an uppermost layer on an InP substrate
Producing an epitaxial wafer in which a GaAs base layer and an InP layer are sequentially laminated, then annealing the epitaxial wafer in an inert gas atmosphere, then selectively exposing a desired region of the base layer, a base electrode by laminating WSi _X film on the exposed portion of the base layer, then the WSi _X film as a mask, the in
A method for manufacturing an HBT, comprising a step of selectively growing an emitter layer on a P layer.

Conventionally, the mesa formation by etching has been repeated after the entire vertical structure of the HBT has been grown to expose the contact region, thereby forming each electrode. However,
If it becomes possible to form the base electrode first and then use it as a mask material to form the emitter layer by regrowth, a self-aligned process that can control the width of the emitter layer and bring the base electrode and emitter electrode closer together is possible. Becomes
The present invention is based on such an idea. However, in order to realize this method, epitaxial growth on an epitaxial wafer with electrodes is required.
There is a problem that the diffusion of the electrode material into the semiconductor and the deposition of the epitaxial raw material on the electrode are not easy.

The present invention is based on new findings obtained experimentally. That is, when a semiconductor layer is grown in vapor phase a WSi _X (tungsten silicide) layer serving as a heat electrode as a mask, rather than the raw material of the deposition occurs on the mask, also, WSi _X be diffused into the semiconductor layer There is no. Further, the sputtering method by using, it is possible to obtain a WSi _X film made of very good surface flatness. Therefore, as described above, selectively exposing the desired area of the base layer, the base electrode by laminating WSi _X film therein,
Then, as the WSi _X film mask, the selective growth of the emitter layer on an InP layer, it is possible to self-aligned processes which can be brought close to the base and emitter electrodes, also controls the emitter layer width, an emitter resistor Can be stable.

The present invention is based on other new findings. That is, when an InP layer is stacked on a C-doped p-InGaAs layer and then annealed in an inert gas atmosphere, the InP layer functions as a protective layer, and the p-In
H ions trapped in the GaAs layer are expelled,
The hole generated when C enters the position of group V atom is activated (ac
tivation) and regenerate to increase carrier density. Therefore, as described above, C-doped p-InGaAs
An s base layer and an InP layer are sequentially laminated to produce an epitaxial wafer having an uppermost layer, and then the epitaxial wafer is annealed in an inert gas atmosphere to obtain p-type.
The carrier density of the InGaAs base layer can be increased, the base resistance can be reduced, and the high-speed characteristics of the HBT can be improved.
In the present invention, the InP layer having a function of protecting the p-InGaAs base layer during annealing in an inert gas atmosphere eventually constitutes a part of the emitter layer.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A to 1E are process explanatory diagrams of one embodiment of a method for manufacturing an HBT according to the present invention. The steps are as follows. That is, 1) First, 100 nm is formed on the semi-insulating InP substrate 200.
Thick InP buffer layer 201, 500 nm thick n-In
GaAs sub-collector layer 202, 300 nm thick InG
aAs collector layer 203, 70 nm thick C-doped p-I
An nGaAs base layer 204 and a 20 nm thick n-InP emitter layer 205 are epitaxially grown by a metal organic vapor deposition method (FIG. 1A). 2) Next, the epitaxial wafer is annealed in a nitrogen atmosphere at 500 ° C. for 5 minutes to obtain C-doped p-InGa.
Activate the As base layer 204. 3) then pattern the resist using known lithography techniques to expose only the desired areas;
The n-InP emitter layer 205 is partially removed with a wet etchant using the resist as a mask. 4) Next, a 20 nm thick WS is formed on the entire surface by sputtering.
The i ₂ layer 222 is laminated, and then immersed in acetone to lift off the unnecessary WSi ₂ layer 222 on the resist to form an epitaxial wafer with the WSi ₂ layer 222 and the n-InP emitter layer 205 exposed on the surface. (Figure 1
(B)). 5) Next, on the epitaxial wafer, WSi ₂
The n-InP emitter layer 206 and the n-InGa
The As cap layer 207 is selectively grown by MOCVD (FIG. 1C). 6) Next, the n-InP emitter layer 205 and the n-InP
Emitter layer 206 and n-InGaAs cap layer 2
The sub-collector layer 202 is partially exposed by performing etching using a wet etchant while masking the emitter region made of 07 and a part of the WSi ₂ layer 222 (FIG. 1D). 7) Next, a silicon nitride film 211 is formed on the entire surface, and HB
In order to form a Ti / Pt / Au electrode on each layer of T, a resist is applied to the entire surface of the wafer, and the resist on the n-InGaAs cap layer 207, the WSi ₂ layer 222, and the subcollector layer 202 is lithographically applied. And the silicon nitride film 221 is partially removed with a wet etchant using the remaining resist as a mask. After that, Ti / Pt / Au is vapor-deposited on the entire surface and then immersed in acetone to form Ti / Pt / Au on the resist.
Pt / Au is lifted off and the collector electrode 221a,
A base electrode 221b and an emitter electrode 221c are formed (FIG. 1E). The base electrode 221b is finally made of WSi ₂ / Ti / Pt / Au.

The high-frequency characteristics of the HBT manufactured as described above were measured. As a result, in the element of the emitter size of 4 [mu] m × 10 [mu] m, the current gain cutoff frequency f _t and the maximum oscillation frequency f _max, respectively f _t = 80G
Hz and f _max = 110 GHz. As a comparative example, a conventional non-self-aligned HBT without selective growth was manufactured using an epitaxial wafer having the same epitaxial laminated structure. F _t of the HBT is = 4
0GHz, f _max was 50GHz. As described above, the high-speed characteristics of the HBT of this embodiment surpassed those of the comparative example. Note that the above embodiment is an example in which the present invention is embodied, and does not limit the technical scope of the present invention.

[0012]

According to the structure of the present invention, there is an excellent effect that an HBT having improved high speed characteristics can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1E are process explanatory diagrams of an embodiment of a method for manufacturing an HBT according to the present invention.

2 (a) to 2 (c) are process explanatory views of a conventional HBT manufacturing method.

[Explanation of symbols]

Reference Signs List 200 InP substrate 201 InP buffer layer 202 n-InGaAs sub-collector layer 203 InGaAs collector layer 204 p-InGaAs base layer 205 n-InP emitter layer 206 InP emitter layer 207 n-InGaAs cap layer 211 silicon nitride film 222 WSi ₂ layer 221a collector Electrode 221b Base electrode 221c Emitter electrode

Claims (1)

[Claims] 1. An epitaxial wafer in which a carbon-doped p-InGaAs base layer and an InP layer are sequentially laminated as an uppermost layer on an InP substrate by a metal organic chemical vapor deposition method, and the epitaxial wafer is then inert gas. annealed in an atmosphere, then, the desired region of the base layer is selectively exposed, then the base electrode by laminating WSi _X film on the exposed portion of the base layer, then mask the WSi _X film A method of selectively growing an emitter layer on the InP layer.