JPH10283782A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can shorten reading- out time without increasing an electric current nor the occupying area of memory cells remarkably. SOLUTION: In a first step, the data stored in one of memory cells M1-Mn are selected and held in a latch circuit MF1 and, in a second step, column address transfer gates TCA and TCB are simultaneously turned on and the data held in the latch circuit MF1 are written in a buffer circuit B1 through a sense amplifier S1. In a third step, the data stored in a buffer circuit E1 are read out and supplied to an output processing circuit S through a data line O1. In parallel with the operations in the third step in a column block BL1, another column block BL2 is made to make the operations in the second step. Similarly, data are continuously read out from the buffer circuit of each column block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which the order of addresses to be read is determined.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional semiconductor memory device. This semiconductor memory device includes memory cells M1 to Mn and M having a latch circuit for storing data.
1 ′ to Mn ′ and the data of the respective memory cells M1 to Mn and M1 ′ to Mn ′ are digit lines D1, D1B,
Transfer gate T for propagation to D2 and D2B
1A to TnA, T1B to TnB, T1A 'to TnA',
T1B 'to TnB' and digit lines D1, D1B, D
2, a column address transfer gate TCA for transmitting the data of D2B to the sense amplifiers S1 and S2,
TCB, TCA ', TCB' and sense amplifiers S1, S
And an output processing circuit S for selecting any one of the data from No. 2 and outputting the final output data S0.

[0003] Transfer gates T1A to TnA, T1
B to TnB, T1A 'to TnA', T1B 'to TnB'
Are signals (hereinafter referred to as row address signals) R1 to R
n, and is switched by R1 'to Rn'. Also,
Column address transfer gates TCA, TCB, T
CA ′ and TCB ′ are switched by signals (hereinafter, referred to as column address signals) C1 and C2.

In this semiconductor memory device, memory cell M1
To Mn and M1 'to Mn' are selected by one of the row address signals R1 to Rn or R1 'to Rn', and digitized from one of the memory cells M1 to Mn and M1 'to Mn'. Lines D1, D1B, D2, D2B
, Or row address signals R1 to Rn or R1 ′ to Rn ′.

Further, digit lines D1, D1B, D2,
The data of D2B is propagated by selecting one of the column transfer gates TCA and TCB by the column address signal C1, and selecting one of the column transfer gates TCA 'and TCB' by the column address signal C2. The data delayed by the above operation is read out and amplified by the sense amplifiers S1 and S2, and then supplied to the output processing circuit S via the data lines O1 and O2, thereby obtaining final output data S0. Is read.

[0006]

In this conventional semiconductor memory circuit, to perform high-speed reading, the sense amplifier S1 is used.
And S2 need to be increased in speed, and for that purpose, a large amount of current needs to flow through the sense amplifiers S1 and S2. However, even in that case, a read time corresponding to the processing time of the sense amplifiers S1 and S2 after the column selection and the time required for the processing of the output processing circuit S occur.

In order to shorten the read time, when the same data is simultaneously written into two memory cells and the method of simultaneously reading from two memory cells is employed, the speed can be increased. The area occupied by the memory cell is required to be twice as large as that of a normal memory cell, which is the same result as doubling the transistor capacity of the memory cell.

Therefore, in the conventional semiconductor memory circuit, it is difficult to avoid a large increase in the area occupied by the memory cell or an increase in the current used by any of the above methods.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor memory circuit capable of shortening a read time without increasing current or significantly increasing a memory cell occupation area.

[0010]

According to the present invention, in order to achieve the above object, data from one of a plurality of memory cells designated by a read address is output to a data line through a switching element and a sense amplifier. Do
In a semiconductor memory device in which the order of read addresses is predetermined, data previously read from one memory cell specified by a read address among a plurality of memories based on a read address after a current read address. Has a holding means for holding one of the input side and the output side of the sense amplifier, and reads and outputs data from the holding means.

According to the present invention, after data is output from the memory cell specified by the current read address, the data of the memory cell at the next read address which is pre-read and held by the holding means is immediately read from the holding means. be able to.

According to another aspect of the present invention, there is provided a block configured to output data from one of a plurality of memory cells designated by a read address to a data line through a switching element and a sense amplifier. In the semiconductor memory device in which the read address order is predetermined in which the number of columns is provided, each of the blocks is designated by the read address among the plurality of memories based on the read address after the current read address. A plurality of blocks each including: holding means for holding data read earlier from one memory cell on one of an input side and an output side of the sense amplifier; and output means for reading and outputting data from the holding means. Perform alternately the holding operation by the holding means and the output operation by the output means, It is obtained so as to output the data continuously from the output means using the clock unit.

According to the present invention, after the data of the block specified by the current read address is output, the data of the block of the next read address which is pre-read and held by the holding means is immediately read from the holding means. it can.

Further, according to the present invention, blocks of a structure configured to output data from one memory cell designated by a read address among a plurality of memory cells to a data line through a switching element and a sense amplifier are provided by the number of columns. In the semiconductor memory device in which the order of the read addresses is predetermined, each of the blocks precedes one memory cell specified by the read address among the plurality of memories based on the read address after the current read address. A latch circuit for holding the read data on the input side of the sense amplifier, and a buffer circuit for outputting the output data of the sense amplifier to which the data from the latch circuit is input to the data line at the same timing. Having multiple blocks of data read from one memory cell A first step of holding data by the latch circuit, a second step of reading data held in the latch circuit and writing the data to the buffer circuit through a sense amplifier, and a step of reading data written in the buffer circuit to a data line based on a current address. The three stages are sequentially and cyclically performed, and each of three blocks out of the plurality of blocks performs the first stage, the second stage, and the third stage simultaneously and separately in parallel. Data is continuously output to the

According to the present invention, the read processing is performed in three stages, so that the influence of the processing time of the sense amplifier can be minimized.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a main part of an embodiment of a semiconductor memory circuit according to the present invention. As shown in the figure, in this embodiment, column blocks BL1 and BL2 are connected to an output processing circuit S for outputting final output data S0 via data lines O1 and O2, respectively.

The column block BL1 includes a memory cell M1 to Mn having a latch circuit for storing data, and a digit line D which stores data of each of the memory cells M1 to Mn.
1. Transfer gates T1A to TnA, T1B to TnB, which are switching elements for propagating to D1B
A latch circuit MF1 for temporarily storing data of the memory cells M1 to Mn, switching elements TF and TFB for transferring data to the latch circuit MF1, a sense amplifier S1, and a sense amplifier for digitizing the data of the digit lines D1 and D1B. It has column address transfer gates TCA and TCB for propagating to S1, and a buffer circuit B1 for outputting data from the sense amplifier S1 at the same timing.

The column block BL2 is also a column block B.
A memory cell M1′-Mn ′ having a latch circuit for storing data,
The data of each of 1 ′ to Mn ′ is converted to digit lines D2 and D2.
Transfer gates T1A 'to TnA' and T1B 'to TnB', which are switching elements for propagating to 2B.
A latch circuit MF2 for temporarily storing data of the memory cells M1 'to Mn', switching elements TF 'and TFB' for passing data to the latch circuit MF2, a sense amplifier S2, and digit lines D2 and D2B. It has column address transfer gates TCA 'and TCB' for transmitting data to the sense amplifier S2, and a buffer circuit B2 for outputting data from the sense amplifier S2 at the same timing.

Transfer gates T1A to TnA, T1
B to TnB, T1A 'to TnA', T1B 'to TnB'
Are signals (hereinafter referred to as row address signals) R1 to R
n, and is switched by R1 'to Rn'. Also,
Column address transfer gates TCA, TCB, T
CA ′ and TCB ′ are switched by signals (hereinafter, referred to as column address signals) C1 and C2. The latch circuits MF1 and MF2 are connected to the intermediate potential control signal E1.
And E2. Switching elements TF and TFB and TF 'and TFB' are switching-controlled by transfer control signals F1 and F2. Further, the buffer circuits B1 and B2 are controlled to be switched between an input waiting state and a data output state by the control signals BC1 and BC2.

Normally, each column block BL1 and BL2
Are provided in the same configuration by the number of columns. FIG. 1 is an example when there are two columns.

At this time, it is assumed that data is output from the final output stage in three stages. Of these three stages, the first stage is the initial preparation stage of the column block,
The second stage is a processing stage of the sense amplifier, and the third stage is a final output preparation stage.

Next, the operation of this embodiment will be described with reference to FIG.
This will be described with reference to the timing chart of FIG. First,
In the first stage, after the data near the threshold value of the memory cell is latched so that the sense amplifier S1 in the column block BL1 does not affect the digit lines D1 and D1B, the row address signal R1 To Rn, only one row address signal selected in the next period is activated. Here, the row address signal R1
Only active (on). At this time, the transfer control signal F1 is activated, and the intermediate potential control signal E1 and the column address signal C1 are turned off.

As a result, data stored in the memory cell M1 schematically shown in FIG. 2A is selected from the memory cells M1 to Mn, and the transfer gate T1A,
Propagated through digit lines D1 and D1B via T1B and further input to latch circuit MF1 via transfer gates TF and TFB, and the data is transferred to the same data as memory cell M1 as schematically shown in FIG. Rewrite to
The above is the first stage.

Next, in the second stage, when the column address signal C1 is turned on, the column address transfer gates TCA and TCB are simultaneously turned on, so that the same data as the memory cell M1 held in the latch circuit MF1 is stored in the column. Address transfer gate TCA, TCB
Through the column output data lines D1S and D1BS, and supplied to the sense amplifier S1 as schematically shown in FIG. 2C.

After the data input to the sense amplifier S1 is detected and amplified by the sense amplifier S1, the data is input to the buffer circuit B1.
Is written to. At this time, the control signal BC1 causes the data to be transferred to the data line O1, and eventually to the output processing circuit
The buffer circuit B1 is controlled so that the signal does not propagate to the buffer circuit B1. The above is the second stage.

Finally, in the third stage, the stored data is read from the buffer circuit B1 by the control signal BC1 and supplied to the output processing circuit S via the data line O1, where predetermined processing is performed. Thereafter, as schematically shown in FIG. 2D, the data is output as final output data S0. The above is the third stage.

On the other hand, in another column block BL2, in parallel with the operation of the second stage in the column block BL1, for example, as shown in FIG.
To Mn ', the data stored in the memory cell M1' is selected, and the transfer gates T1A ', T1
Propagated through digit lines D2 and D2B via B 'and further input to the latch circuit MF2 via transfer gates TF' and TFB ', and the data is transferred to the memory cell M1 as schematically shown in FIG. The first-stage processing of rewriting the same data as' is performed.

In parallel with the operation of the third stage in the column block BL1, the column block BL2 is
Perform the stage operation, and as schematically shown in FIG.
After the data from the latch circuit MF2 is input to the sense amplifier S2 and amplified, the data is written to the buffer circuit B2. Finally, after completion of the third-stage operation in the column block BL1, the column block BL2 performs the third-stage operation, and the data in the memory cell M1 'is finally stored as schematically shown in FIG. It is output as output data S0.

The above is the description of the two column blocks BL1 and B
This is a description of L2. As can be seen from this description, by controlling the three column blocks so that the above three steps are performed separately and simultaneously in a cyclic manner, the read mechanism is reduced to three. Can be divided into two. In this case, it is most efficient to fix the row address and change only the column specification to change the next and subsequent addresses, and then move the row address after the final specification of the column is completed Let it.

As described above, in the present embodiment, the rate is determined by the processing time in the conventional sense amplifier without increasing the area occupied by the memory cells, as compared with the conventional device in which the reading process is performed in only one stage. Read time can be reduced to half or less.

The present invention is not limited to the above embodiment. For example, the latch circuits MF1 and MF2 are provided in the path from the output side of the sense amplifiers S1 and S2 to the input side of the output processing circuit S. You may do so.

[0032]

As described above, according to the present invention,
After outputting data from the memory cell specified by the current read address, the data of the memory cell at the next read address that is pre-read and held by the holding means can be immediately read from the holding means. The read time can be shortened without increasing the area of the block, and after the data of the block specified by the current read address is output, the block of the next read address that is read ahead and held by the holding unit is read out. Can be immediately read out from the holding means, so that the reading time, which was limited by the processing time in the conventional sense amplifier, can be reduced to half or less.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

FIG. 3 is a configuration diagram of a main part of a conventional example.

[Explanation of symbols]

M1 to Mn, M1 'to Mn' Memory cells T1A to TnA, T1B to TnB, T1A 'to Tn
A ', T1B' to TnB ', TF, TFB, TF', T
FB 'transfer gate TCA, TCB, TCA', TCB 'column address transfer gate S1, S2 sense amplifier B1, B2 buffer circuit S output processing circuit BL1, BL2 block R1-Rn, R1'-Rn' row address signal F1, F2 Latch circuit transfer control signal C1, C2 Column address signal S0 Final output data O1, O2 Output data line BC1, BC2 Control signal

Claims (4)

[Claims] 1. A semiconductor memory device according to claim 1, wherein data from one memory cell designated by a read address among a plurality of memory cells is output to a data line through a switching element and a sense amplifier. Based on the read address after the current read address, the data previously read from one memory cell specified by the read address of the plurality of memories is input to the input side and the output side of the sense amplifier. On the other hand, a semiconductor memory device having a holding means for holding, and reading and outputting data from the holding means. 2. A read address, comprising as many columns as blocks having a configuration for outputting data from one memory cell specified by a read address to a data line through a switching element and a sense amplifier among a plurality of memory cells. In the semiconductor memory device in which the order is predetermined, each of the blocks is read first from one memory cell designated by a read address among the plurality of memories based on a read address after a current read address. Holding means for holding the output data on one of the input side and the output side of the sense amplifier, and output means for reading and outputting data from the holding means;
A semiconductor memory device, wherein each of the plurality of blocks alternately performs a holding operation by the holding unit and an output operation by an output unit, and continuously outputs data from the output unit in units of the block. 3. A read address of a read address provided with blocks corresponding to the number of columns, the blocks being configured to output data from one memory cell designated by a read address among a plurality of memory cells to a data line through a switching element and a sense amplifier. In the semiconductor memory device in which the order is predetermined, each of the blocks is read first from one memory cell designated by a read address among the plurality of memories based on a read address after a current read address. A latch circuit for holding the output data on the input side of the sense amplifier, and a buffer circuit for outputting the output data of the sense amplifier to which the data from the latch circuit is input to the data line at the same timing. And wherein the plurality of blocks are read from the one memory cell. A first step of holding the latched data by the latch circuit, a second step of reading the data held in the latch circuit and writing the data to the buffer circuit through the sense amplifier, and And a third step of reading out to the data line based on the address of the plurality of blocks is sequentially and cyclically performed, and each of three blocks among the plurality of blocks simultaneously performs the first step, the second step, and the third step. A semiconductor memory device which performs the operations separately and in parallel and continuously outputs data to the data lines. 4. A row address signal designating one of the plurality of memory cells in each block is fixed,
5. The semiconductor memory device according to claim 4, wherein a column address signal for selecting the plurality of blocks is sequentially changed, and after the end of the last column address, the row address is moved and updated repeatedly.