JP2003123477A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the access delay of an address in which word line transition is caused can be prevented apparently. SOLUTION: In a semiconductor memory comprising a bit line group 2 connected to a column decoder 1, a word line group 4 connected to a row decoder 3, and a plurality of memory cells arranged at addresses at which each bit line and each word line intersect, the device is provided with a mirror bit line (MBL) 6 at which a memory cell group 7 in which the same data as data in a memory cell corresponding to an address 0 (BL[0]) of the bit line is written is arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more specifically, to an LSI memory product (eg, DRA).
M, SRAM, a flash memory as a non-volatile semiconductor memory device, a mask ROM, etc.) for enabling high-speed reading of data.

[0002]

2. Description of the Related Art A conventional semiconductor memory device will be described below with reference to the drawings.

As shown in FIG. 3, a bit line BL group 52 connected to a column decoder 51 and a row decoder 53.
A memory cell array 55 is composed of a word line WL group 54 connected to each other and a plurality of memory cells arranged at addresses where each bit line BL and word line WL intersect.

That is, as shown in FIG. 3, for example, the word line WL [0] and each bit line BL group (BL [0],
BL [1], BL [2], BL [3], BL [4], B
L [5], BL [6], BL [7] ... BL [f
b], BL [fc], BL [fd], BL [fe], B
A memory cell (not shown) corresponding to each position (called an address or an address) intersecting with L [ff]) is
"000", "001", "002", "00"
3 ”,“ 004 ”,“ 005 ”,“ 006 ”,“ 00 ”
7 "..." 0FB "," 0FC "," 0FD "," 0 "
Each data of "FE" and "0FF" is written.

External addresses "100", "101",
"102", "103", "104", "105",
"106", "107" ... "1FB", "1F"
The data corresponding to “C”, “1FD”, “1FE”, and “1FF” is the word line WL [1] and each bit line B.
L group (BL [0], BL [1], BL [2], BL
[3], BL [4], BL [5], BL [6], BL
[7] ... BL [fb], BL [fc], BL [f
d], BL [fe], BL [ff]) is written in each memory cell. The same applies hereinafter.

Then, desired data is output through the sense amplifier 56 connected to the column decoder 51.

[0007]

In recent years, with the increase in the speed of the CPU, the access from the CPU to the memory has become the bottleneck of the entire system.

In order to solve this, a memory product (for example, a DR product) that automatically outputs regular address data from the address once the address is input.
AM, SRAM, flash memories as non-volatile semiconductor memory devices, mask ROMs, etc.) have appeared.

In an LSI memory product, an external address is internally divided into a row address (word line selection) and a column (bit line selection) to efficiently access a memory cell.

Generally, lower addresses are assigned to columns and higher addresses are assigned to rows. For this reason, relatively high-speed reading is possible for continuous access within the column, but when accessing to another row address (different word line), the reading time is increased for access. Was there.

Therefore, there are restrictions such as "high-speed reading only in column address" and "waiting time occurs when row address is different" in a memory product capable of regular continuous reading.

That is, as shown in FIG. 3, for example, the address “000” → “001” → “002” → “003” →
.. “0FC” → “0FD” → “0FE” → “0FF”
The continuous reading in the same word line WL [0] could be speeded up.

However, for example, the address "0FF" → "1"
Different word lines (WL [0] → WL [1] and WL [1] → WL] such as “00” or “1FF” → “200”
Continuous reading over [2]) requires time for word line transition, making it difficult to read data at high speed.

[0014]

In view of the above problems, a semiconductor memory device according to the present invention has a bit line group connected to a column decoder, a word line group connected to a row decoder, and each bit line and word. A mirror bit line comprising a plurality of memory cells arranged at addresses intersecting with lines, in which memory cells to which the same data as the data in the memory cells corresponding to the predetermined addresses of the bit lines are written are arranged. Is provided.

Further, the same data as the data in the memory cell corresponding to the predetermined address of the bit line is on a different word line obtained by incrementing the row address by one,
Writing is performed in a memory cell arranged at an address intersecting with the mirror bit line.

Further, it is characterized by further comprising a first sense amplifier for the bit line group, a second sense amplifier for the mirror bit line, and a selection circuit for selecting a desired sense amplifier. Is.

Further, the selection circuit comprises a pass gate circuit for selecting a desired sense amplifier based on a start signal which is start information for continuous reading.

Further, the second sense amplifier is characterized in that it is connected to the selection circuit via a latch circuit.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a semiconductor memory device of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a group of bit lines BL connected to a column decoder 1, a group of word lines WL connected to a row decoder 3, and an address where each bit line BL and a word line WL intersect. A memory cell array 5 is composed of a plurality of memory cells arranged in.

That is, as shown in FIG. 1, for example, external addresses "000", "001", "002", "00" are used.
3 ”,“ 004 ”,“ 005 ”,“ 006 ”,“ 00 ”
7 "..." 0FB "," 0FC "," 0FD "," 0 "
The data corresponding to FE ”and“ 0FF ”includes word line WL [0] and each bit line BL group (BL [0], BL
[1], BL [2], BL [3], BL [4], BL
[5], BL [6], BL [7] ... BL [fb],
BL [fc], BL [fd], BL [fe], BL [f
f]) is written in each memory cell that intersects.

External addresses "100", "10"
1 ”,“ 102 ”,“ 103 ”,“ 104 ”,“ 10 ”
5 "," 106 "," 107 "..." 1FB "," 1 "
The data corresponding to “FC”, “1FD”, “1FE”, and “1FF” includes word line WL [1] and each bit line BL group (BL [0], BL [1], BL [2], BL.
[3], BL [4], BL [5], BL [6], BL
[7] ... BL [fb], BL [fc], BL [f
d], BL [fe], BL [ff]) is written in each memory cell. The same applies hereinafter.

Further, the column decoder 1 is (first)
It is connected to the sense amplifier 8.

The configuration up to this point is similar to the conventional circuit configuration.

The feature of the present invention is to provide a mirror bit line (Mirror BL, MBL hereinafter) 6 corresponding to the bit line BL [0] (address of column 0) as shown in FIG. Bit line MBL
[0] and each word line WL [0], WL [1], WL
"100", "2" at the position (address) where [2] intersects
That is, the memory cell group 7 into which each data of “00” and “300” is written is arranged.

Each memory cell corresponding to the mirror bit line MBL [0] has a memory cell on a different word line WL whose row address is incremented by one.
The same data as the data of the bit line BL [0] is written. Therefore, in the present embodiment shown in FIG.
The data corresponding to the addresses “100”, “200”, and “300” have different word lines WL but different bit lines BL [0] and mirror bit lines MBL [0].
There are two above.

That is, the data corresponding to the address of "100" is stored on the memory cell where the bit line BL [0] and the word line WL [1] which should be present intersect, and the mirror bit line MBL [0]. And word line WL
Data is written in the memory cell where [0] intersects.

The data corresponding to the address "200" is stored on the memory cell where the bit line BL [0] and the word line WL [2] which should be present intersect, and the mirror bit line MBL [0]. And word line WL
Data is written in the memory cell where [1] intersects.

Further, the data corresponding to the address of "300" is provided on the memory cell where the bit line BL [0] and the word line WL [3] (not shown) which should be present intersect, and the mirror bit line. The data is written in the memory cell where MBL [0] and word line WL [2] intersect. The same applies hereinafter.

Here, when performing continuous access within the word line WL [0], for example, “0FD” → “0F”
After reading "E" → "0FF", word line WL
By reading out the “100” cell on [0], “0F
The reading delay from "F" to "100" does not occur.

Reference numeral 9 is the mirror bit line MBL.
In the (0) (second) sense amplifier, the sense amplifier 8 is directly connected to a selection circuit 12 described later, but the sense amplifier 9 is connected via a latch circuit 10 to the selection circuit 1
Connected to 2.

Here, the selection circuit 12 is the selection control circuit 1
Based on the selection signal from 1, the sense amplifiers 8 and 9
Any of the above is selected, and arbitrary data is output from the sense amplifier side selected by the selection circuit 12.

In this embodiment, as the selection circuit 12, a pass gate circuit configuration is adopted as shown in FIG. 2, and the selection signal (start position information for starting continuous reading) is transferred to desired transfer gates 13 and 14. Input, and either transfer gate turns on,
The desired sense amplifier output is selected. Reference numeral 15 is an inverter.

That is, the selection signal (start signal) is "00".
During continuous reading starting from "0"("100","200", etc.), the original sense amplifier 8 side is selected, and the word line transition does not occur by using the normal bit line BL [0]. Further, the sense amplifier 9 side connected to the mirror bit line MBL [0] 6 is selected when the select signal (start signal) is continuously read across the word line WL.

Then, in advance, the mirror bit line M
By storing the data of the “100” address in the latch circuit 10 before the sense amplifier 9 for BL [0] needs to read the “100” address,
The transition of the word line WL is generated at the stage requiring the actual "100" read (word line WL
[0] → WL [1]), during which the data of the latch circuit 10 is treated as output data, and then bit line B
The reading of L [0] is skipped and the bit line BL [1] is skipped.
By performing the internal processing so that the continuous reading is performed again, the waiting time does not occur even in the continuous reading across the word lines WL.

According to the present invention, a bit line group connected to a column decoder, a word line group connected to a row decoder, and a plurality of memory cells are arranged at positions where both lines intersect. The present invention is applicable to LSI memory products (for example, DRAM, SRAM, flash memory, mask ROM, etc.) and enables high-speed reading of data.

[0037]

According to the present invention, the mirror bit line is arranged corresponding to the predetermined address of the bit line, and is arranged at the address where the different word line incremented by one row address and the concerned mirror bit line intersect. By writing the same data as the data in the predetermined address in a plurality of memory cells, latching the data in the memory cells corresponding to the mirror bit lines in advance, and outputting the data from there, the word line The access delay of the address where the transition occurs can be apparently eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a selection circuit applied to the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

1 column decoder 2 bit line group 3 Row decoder 4 word line group 5 memory cell array 6 Mirror bit line 7 memory cells 8 sense amplifier 9 sense amplifier 10 Latch circuit 11 Selection control circuit 12 Selection circuit

Claims (5)

[Claims] 1. A group of bit lines connected to a column decoder, a group of word lines connected to a row decoder,
In a semiconductor memory device comprising a plurality of memory cells arranged at an address where each bit line and a word line intersect, a memory cell in which the same data as the data in the memory cell corresponding to the predetermined address of the bit line is written A semiconductor memory device having a mirror bit line formed by arranging the following. 2. The same data as the data in the memory cell corresponding to the predetermined address of the bit line is arranged at an address intersecting with the mirror bit line on a different word line obtained by incrementing the row address by one. The semiconductor memory device according to claim 1, wherein data is written in the memory cell. 3. A first sense amplifier for the bit line group, a second sense amplifier for the mirror bit line, and a selection circuit for selecting a desired sense amplifier. Item 2. The semiconductor memory device according to item 1. 4. The semiconductor memory device according to claim 3, wherein the selection circuit includes a pass gate circuit that selects a desired sense amplifier based on a start signal that is start information for continuous reading. 5. The semiconductor memory device according to claim 3, wherein the second sense amplifier is connected to the selection circuit via a latch circuit.