JPH10276076A - Semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a circuit that switches a voltage over a breakdown voltage of a single field effect transistor(FET). SOLUTION: With an input voltage Vi set to 0 V, FETs 13-1, 13-2 are conductive, and since the resistance of voltage uniformizing resistors 14-1, 14-2 is sufficiently higher than the resistance of a load resistor 15, an output voltage Vo is pulled up to a power supply voltage Vdd. In this case, nearly a uniform voltage is applied to the FETs 13-1, 13-2 by the voltage uniformizing resistors 14-1, 14-2. When the input voltage Vi is gradually increased and exceeds 0.1 V, the FET 13-1 is conductive, and a source level of the FET 13-2 is increased by a source-drain voltage of the FET 13-1, but a threshold voltage is set lower, then the FET 13-2 is made conductive nearly similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaAs MES as a field effect transistor (hereinafter referred to as "FET").
The present invention relates to a semiconductor circuit using FETs, MOSFETs, and the like, and more particularly to a semiconductor circuit that switches a voltage higher than the withstand voltage of a single FET.

[0002]

2. Description of the Related Art Conventionally, as a technique relating to a semiconductor circuit (for example, an inverting amplifier) using an FET, there is a technique described in the following literature. Reference: McGraw-Hill, Inc, 1983, DAHodges et al. "ANA
LYSIS AND DESIGN OFDIGITAL INTEGRATED CIRCUITS ", P.
FIG. 2 is a circuit diagram of a conventional inverting amplifier described in the above-mentioned document. The inverting amplifier has an input terminal 1 for inputting an input voltage and an output terminal 2 for outputting an output voltage. The input terminal 1 is connected to the gate electrode of an n-channel FET 3. The source electrode of FET3 is ground (GN
D), and this drain electrode is connected to the output terminal 2. Between the output terminal 2 and the power supply voltage Vdd,
The load resistance 4 is connected. In such an inverting amplifier, when the input voltage input to the input terminal 1 is equal to or lower than the threshold voltage of the FET 3, the FET 3 is turned off, and the output terminal 2 is pulled up to the power supply voltage Vdd by the load resistor 4, and Power supply voltage Vdd is output from output terminal 2. When the input voltage is increased from this state, FE
T3 is turned on, the on-resistance of the FET 3 gradually decreases, and the output terminal 2 is pulled down to the GND potential, so that the output voltage decreases. As described above, as the input voltage is increased, the output voltage is decreased, and an inverting amplification operation is performed.

[0003]

However, in a conventional semiconductor circuit such as an inverting amplifier, when the FET 3 is off, the entire power supply voltage Vdd is applied between the drain electrode and the source electrode of the FET 3. , The FE
Power supply voltage Vdd exceeding withstand voltage between drain and source of T3
There was a problem that it could not be used for the circuit. The present invention solves the above-mentioned problems of the prior art and provides a single FE
It is an object of the present invention to provide a semiconductor circuit for switching a voltage higher than a withstand voltage of T.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor circuit such as an inverting amplifier, comprising a voltage switch means and a voltage equalizing means. . The voltage switch means includes k (where k is a positive integer of 2 or more) n-channel FETs, and the source electrode of the first FET is connected to the low-voltage node and the k-th F-channel FET is connected to the low-voltage node.
A drain electrode of the ET is connected to the high voltage node, and a drain electrode of the i-th (where 1 ≦ i ≦ k−1) FET is connected to a source electrode of the i + 1-th FET;
The gate electrodes of all the first to k-th FETs are connected to the input terminal, and the threshold voltage of the (i + 1) th FET is set lower than the threshold voltage of the i-th FET. The equalizing means is connected between the high voltage node and the low voltage node, and when all the first to k-th FETs are off by gate control of an input voltage input from the input terminal. A uniform source-drain voltage is applied to each of these FETs. The current flowing from the drain electrode of the k-th FET to the source electrode of the first FET is controlled by the voltage between the input terminal and the source electrode of the first FET.

According to a second aspect of the present invention, the n-channel FET of the first aspect is replaced with a p-channel FET.
The relationship between the threshold voltages of the k FETs is reversed. That is,
According to a second aspect of the present invention, there is provided a semiconductor circuit including a voltage switch and a voltage equalizing unit similar to the first aspect. The voltage switch means has k (where k is a positive integer of 2 or more) p-channel FETs, and the source electrode of the first FET is connected to the high voltage node, and the drain electrode of the k-th FET is connected to the high voltage node. Are connected to the low voltage nodes, respectively, and the ith (where 1 ≦ i ≦ k
-1) the drain electrode of the FET is connected to the source electrode of the (i + 1) th FET, the gate electrodes of all the first to k-th FETs are connected to the input terminal, and
The threshold voltage of the +1 FET is set higher than the threshold voltage of the i-th FET. The current flowing from the source electrode of the first FET to the drain electrode of the k-th FET is controlled by the voltage between the input terminal and the source electrode of the first FET.

According to the first aspect of the present invention, since the semiconductor circuit is configured as described above, for example, when the same input voltage as the low voltage node is input to the input terminal, k FETs are turned off. At this time, a voltage lower than the voltage of the high voltage node is evenly applied between the source electrode and the drain electrode of each FET by the equalizing means. When the input voltage of the input terminal is gradually increased and exceeds the threshold voltage of the first FET, the first
Are turned on, and the threshold voltage of the (i + 1) th FET is set lower than the threshold voltage of the ith FET, so that the second to kth FETs are also turned on in substantially the same manner. According to the second aspect of the present invention, the operation is substantially the same as that of the first aspect, except that the direction of the current flowing through the k FETs is reversed.

[0007]

FIG. 1 is a circuit diagram of an inverting amplifier showing an embodiment of a semiconductor circuit according to the present invention. This inverting amplifier has an input terminal 11 for inputting an input voltage Vi, and an output terminal 12 for outputting an output voltage Vo. Between the high voltage node Nh connected to the output terminal 12 and the low voltage node Nl connected to GND, a voltage switch means gate-controlled by the input voltage Vi is connected. The voltage switch means includes k (for example, two) first switches.
N-channel type FET 13-1 and second n-channel type F
The first FET is configured by a series circuit with the ET13-2.
13-1 compared with the threshold voltage Vt of the second FET 13-2.
Are set low. The gate electrodes of the first and second FETs 13-1 and 13-2 are connected to the input terminal 11.
The source electrode of the first FET 13-1 is connected to the low voltage node Nl, and the drain electrode of the first FET 13-1 is connected to the source electrode of the second FET 13-2. The drain electrode of the second FET 13-2 is connected to the high voltage node Nh.

Further, a high voltage node Nh and a low voltage node N
1 is connected to a pressure equalizing means. When the FETs 13-1 and 13-2 are turned off, the equalizing means supplies a uniform source voltage to each of the FETs 13-1 and 13-2.
And a drain-to-drain voltage Vsd.
It is composed of a series circuit of equalizing resistors 14-1 and 14-2, which are linear resistors. A connection point between the resistors 14-1 and 14-2 is connected to a drain electrode of the FET 13-1 and a source electrode of the FET 13-2. ing. A load resistor 15 is connected between the high voltage node Nh and the power supply voltage Vdd, and outputs an output voltage Vo obtained by inverting the input voltage Vi from the output terminal 12. Here, the first and second n-channel FETs 13-1 and 13-2 have a gate length of 0.5.
μm, G of heat-resistant W-Al gate with gate width of 30 μm
aAsMESFET is used, and the first FET13-
The threshold voltage Vt of 1 is set to 0.1V, and the threshold voltage Vt of the second FET 13-2 is set to -1.5V. The first F
The K value of ET13-1 is 10 mS / V, and the second FET 13
The K value of -2 is 10 mS / V. Equalizing resistor 14-
1, 14-2 have a resistance value of 10KΩ, the load resistance 15 has a resistance value of 1KΩ, and the power supply voltage Vdd is 3.3V.

Next, the operation of the inverting amplifier of FIG. 1 will be described. When the input voltage Vi of the input terminal 11 is set to 0 V, FE
T13-1 and 13-2 are turned off. Resistance 14-
Since the resistance values of the resistors 14 and 14-2 are 20 KΩ in total and sufficiently larger than the load resistor 15, the output voltage Vo of the output terminal 12 is almost pulled up to the power supply voltage Vdd. At this time, the resistors 13-1 and 14-2 cause the FET 13-
A substantially uniform voltage of about 1.6 V is applied to 1,13-2. When the input voltage Vi is gradually increased and exceeds 0.1 V, the FET
13-1 is turned on. The source potential of the FET 13-2 is the source-drain voltage Vsd of the FET 13-1.
Although it is higher by one minute, on the contrary, since the threshold voltage Vt of the FET 13-2 is set lower than the threshold voltage Vt of the FET 13-1, the FET 13-2 is also substantially turned on. . This is shown in FIG. FIG. 3 shows the results of a circuit simulator simulating changes in the source-drain voltages Vsd1 and Vsd2 of the FETs 13-1 and 13-2 and changes in the output voltage Vo when the input voltage Vi is changed from 0V to 1V. FIG. 2 is a diagram showing a voltage change characteristic of a main part with respect to an input voltage change in FIG. 1. As is apparent from FIG.
The voltage is applied almost uniformly to -1 and 13-2, and the maximum value does not exceed 1.6V.

As described above, this embodiment has the following effects. When the source electrode and the drain electrode of the two FETs 13-1 and 13-2 are connected in cascade, each of these F
Source-drain voltage Vs of ET13-1 and 13-2
d1 and Vsd2 are determined by a point where the drain currents flowing are balanced under the same condition. In addition, FET13-1,
The off-source-drain current characteristic of 13-2 is called a sub-threshold region. The source-drain current is the source-drain voltage Vsd1, Vsd2
Of the FETs 13-1, 13-
It is not hard to imagine that if any variation or the like of the two elements occurs, the entire voltage will be almost applied to either the source electrode or the drain electrode of the two FETs 13-1 and 13-2. Here, by providing the resistors 14-1 and 14-2 as in the present embodiment, the FET 13
When -1 and 13-2 are off, the resistors 14-1 and 14-2
, A uniform voltage is applied to the two FETs 13-1 and 13-2. As a result, in principle, the FETs 13-1, 13
-2, which is almost twice the source-drain breakdown voltage. When, for example, a linear resistor made of a semiconductor is used as the resistors 14-1 and 14-2, the fluctuation of the voltage division ratio due to the element variation is smaller than the fluctuation based on the sub-threshold characteristics of the FETs 13-1 and 13-2. Although it is extremely small, stable characteristics can be obtained.

On the other hand, as the input voltage Vi is increased, the FET
When turning on 13-1 and 13-2, for example, F
If the ET 13-1 is turned on and the FET 13-2 remains off, the power supply voltage Vdd is almost applied between the source electrode and the drain electrode of the FET 13-2, and a breakdown voltage is required. . Thus, in the present embodiment, the threshold voltage Vt of the FET 13-2 is
1 is set lower than the threshold voltage Vt of 1, the source potential of the FET 13-2 is higher than the GND potential at the time of off, but has the effect of equivalently lowering the potential.
The FETs 13-1 and 13-2 have substantially the same ON characteristics. Therefore, one FET (13-1 or 13-
Voltage is not applied extremely to the source electrode and the drain electrode in 2), and the voltage is applied almost uniformly.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e). (A) Although the equalizing means of the above embodiment is configured using the resistors 14-1 and 14-2 formed of linear resistors, any element may be used as long as the equalizing can be performed. For example, an active circuit such as a nonlinear resistor or a diode, a circuit network combining these, an operational amplifier, or the like may be used. (B) The voltage switch means of the above embodiment is composed of two n
Although it is constituted by the channel type FETs 13-1 and 13-2, three or more n-channel type FETs are used, and the threshold voltage Vt of these FETs is reduced by the FET on the low voltage node Nl side.
, And the voltage equalizing resistors 14-1 and 14-2 are provided in proportion to the number of FETs on the high voltage node Nh side. . (C) The n-channel FET 13-1 of the above embodiment,
13-2 may be replaced with a p-channel FET.
In this case, the power supply voltage Vdd is set to a negative voltage (that is, the low voltage node Nl in FIG.
Becomes a low voltage node), and the relationship of the threshold voltage Vt may be reversed (that is, the threshold voltage Vt of the FET is changed to F-side on the GND side).
Set up in order from ET). Even with such a configuration, the same effects as in the above embodiment can be obtained. Further, as in (b) above, the number of p-channel FETs constituting the voltage switch means may be three or more. (D) In the above embodiment and the modified examples (a) to (c), GaAs is used as the FET constituting the voltage switch means.
The example using the sMESFET has been described.
Even with other FETs, substantially the same operation and effect can be obtained. (E) In the above embodiment and the above (a) to (d), the inverting amplifier was described as an example of the semiconductor circuit. However, the load resistor 15 in FIG. By incorporating the means into another circuit, various semiconductor circuits can be formed.

[0013]

As described above in detail, the present invention includes the voltage switch means and the equalizing means, and the voltage between the input terminal and the source electrode of the first FET is changed by the voltage between the input terminal and the source electrode of the first FET.
From the drain electrode (or source electrode) of the first FET (or the first FET) to the first FET (or the k-th FE).
Since the configuration is such that the current flowing to the source electrode (or drain electrode) of T) is controlled, when the FETs are off, an equal voltage is applied to each of the FETs by the equalizing means. Can be higher than the conventional one. Further, since the fluctuation of the voltage dividing ratio due to the element variation of the voltage dividing means is extremely smaller than the fluctuation based on the sub-threshold characteristic of the FET, stable characteristics can be obtained. In addition, when increasing the input voltage and turning on the FETs constituting the voltage switch means, the threshold voltages of the FETs are set in a predetermined relationship, so that each FET has substantially the same ON characteristics,
No voltage is applied to the source electrode / drain electrode extremely, and a voltage is applied to each FET almost uniformly. Therefore, a semiconductor circuit that switches a voltage higher than the withstand voltage of a single FET can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an inverting amplifier showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional inverting amplifier.

3 is a voltage change characteristic diagram of a main part with respect to the input voltage change of FIG.

[Explanation of symbols]

 11 Input terminal 12 Output terminal 13-1, 13-2 FET 14-1, 14-2 Equalizing resistor 15 Load resistance Nl Low voltage node Nh High voltage node Vi Input voltage Vo Output voltage Vdd Power supply voltage

Claims (2)

[Claims] 1. A semiconductor device comprising: k (where k is a positive integer of 2 or more) n-channel field-effect transistors, wherein a source electrode of the first field-effect transistor is connected to a low-voltage node; The drain electrodes of the field effect transistors are connected to the high voltage nodes, respectively, and the i-th (where 1 ≦ i ≦ k−
1) the drain electrode of the field-effect transistor and the i +
The source electrode of the first field-effect transistor is connected, the gate electrodes of all the first to k-th field-effect transistors are connected to the input terminal, and the threshold voltage of the (i + 1) -th field-effect transistor is the i-th field-effect transistor. Voltage switch means lower than the threshold voltage of the field-effect transistor, and connected between the high-voltage node and the low-voltage node, and the first to k-th gates are controlled by gate control of an input voltage input from the input terminal. Equalizing means for applying a uniform source-drain voltage to each of the field-effect transistors when all of the field-effect transistors are off, the input terminal and the first field-effect transistor The voltage between the source electrode of the transistor and the drain electrode of the k-th field-effect transistor causes the first field-effect transistor to Semiconductor circuit is characterized in that the configuration for controlling the current flowing to the source electrode of Njisuta. 2. A semiconductor device comprising: k (where k is a positive integer of 2 or more) p-channel field-effect transistors, wherein a source electrode of the first field-effect transistor is connected to a high-voltage node and The drain electrodes of the field-effect transistors are connected to the low-voltage nodes, respectively, and the ith (where 1 ≦ i ≦ k−
1) the drain electrode of the field-effect transistor and the i +
The source electrode of the first field-effect transistor is connected, the gate electrodes of all the first to k-th field-effect transistors are connected to the input terminal, and the threshold voltage of the (i + 1) -th field-effect transistor is the i-th field-effect transistor. Voltage switch means higher than the threshold voltage of the field-effect transistor, and connected between the high-voltage node and the low-voltage node, and the first to k-th gates are controlled by gate control of an input voltage input from the input terminal. Equalizing means for applying a uniform source-drain voltage to each of the field-effect transistors when all of the field-effect transistors are off, the input terminal and the first field-effect transistor The voltage between the source electrode of the transistor and the source electrode of the first field-effect transistor causes the k-th field-effect transistor to move from the source electrode of the first field-effect transistor. Semiconductor circuit is characterized in that the arrangement for controlling a current flowing to the drain electrode of the register.