JP2806654B2 - Bias circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias circuit, and more particularly to a bias circuit for determining a cell current value of a current cell type D / A converter.

[0002]

2. Description of the Related Art In a conventional bias circuit, as shown in FIG. 2, a resistor 1, a MOS transistor 2 and a MOS transistor 3 are connected in series between a power supply 14 and a ground 15, and
In this configuration, the gate electrodes of the S transistor 2 and the MOS transistor 3 are connected to their respective drain electrodes, and these are used as output terminals.

Next, the operation of the conventional bias circuit will be described. The resistor 1 (hereinafter abbreviated as R1), the MOS transistor 2 (hereinafter abbreviated as Q2), and the MOS transistor 3 (hereinafter abbreviated as Q3) are connected in series. The voltage is divided by each impedance, and the gate potentials VG1 and VG2 of Q3 depend on the current I flowing through Q3 and Q2,

[0004]

VG1 = VT + √ (2I / β3) (() indicates the range of √; the same applies hereinafter)

[0005]

VG2 = 2VT + √ (2I / β3) + √ (2I / β2)

[0006] Here, β3 = μoεoεs / tox × W3 / L3, β2 = μ0ε0εs / tox × W2 / L2 W3; channel width of Q3, L3; channel length of Q3, W2;
Q2 channel width, L3; Q2 channel length, μo; mobility, εo: dielectric constant in vacuum, εs: relative dielectric constant of gate oxide film, tox; gate oxide film thickness These gate potentials VG1 and VG2 are conventionally The output voltage of the conventional circuit depends on the current I flowing through Q3 and Q2, as shown by equations (1) and (2).

[0007]

The problem when a conventional bias circuit is used for a bias circuit of a current cell type D / A converter will be described again with reference to FIG.

In FIG. 2, MOS transistors 4 to 12 are shown.
(Hereinafter abbreviated as Q4 to Q12) and a resistor 13 constitute a current cell 200, and Q6, Q4, Q5 and Q12, Q10, Q11 can be switched on and off by a switching signal and its inverted signal. , A period in which Q6, Q4, and Q5 are on at the same time, although they are short, occurs.
A current flows to ground via Q6, Q4, Q5.

Since this becomes the load current of Q2, the gate voltage VG2 drops temporarily, and accordingly, the gate voltage VG1 also drops temporarily. Since the gate voltage VG1 is also a bias voltage that determines the current value of the current cell 200,
The temporary decrease in the gate voltage VG1 causes a temporary decrease in the output current of the current cell 200, that is, the output of the D / A converter.

The gate voltages VG2 and VG1 return to a steady value with the passage of time.
When the current constantly flowing through Q2 and Q3 is reduced, the impedance as viewed from the gate voltage VG2 increases, and it takes a long time for the gate voltage VG1 to return to a steady value. The time required to reach the steady value also increases. In other words, there is a disadvantage that the settling time of the D / A converter is deteriorated when trying to reduce the current consumption of the bias circuit.

[0011]

The gist of the present invention is to provide an electric current
Bias is applied to the current cell of the cell-type voltage-current conversion circuit.
A first conductive type first, second, third, fourth, fifth transistor and a second conductive type sixth transistor each having a gate electrode connected to a drain electrode. The source electrode of the sixth transistor is connected to the first power source, the drain electrode of the sixth transistor is connected to the second power source via the first resistor, and the source electrode of the seventh transistor of the second conductivity type. Is connected to a first power supply, the gate electrode of the seventh transistor is connected to the gate electrode of the sixth transistor, the drain electrode of the seventh transistor is connected to the drain electrode of the first transistor, A source electrode of the first transistor is connected to a drain electrode of the second transistor, a source electrode of the second transistor is connected to a drain electrode of the third transistor, The source electrode of the transistor is connected to the second power supply, the drain electrode of the eighth transistor of the first conductivity type is connected to the first power supply, and the gate electrode of the eighth transistor is connected to the gate electrode of the first transistor. The source electrode of the eighth transistor is connected to the drain electrode of the fourth transistor, the source electrode of the fourth transistor is connected to the drain electrode of the fifth transistor, The electrode is connected to a second power supply, and the power supply of the source electrode of the eighth transistor is connected.
Voltage as a first output, and the gate of the third transistor
A voltage as a second output, wherein the first output is the current cell
Input bias, and the current output is set at the second output.
Is to provide a bias that determines the current value of the current.

[0012]

Since the eighth transistor operates as a source follower, its output impedance can be set low, and the output voltage fluctuation due to the load current can be suppressed. In addition, since the change in the source electrode potential of the eighth transistor does not change the gate potential of the second transistor, the gate potential of the third transistor, that is, the bias voltage output is stabilized.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a bias circuit according to a first embodiment of the present invention. In the following description, the MOS transistors 2 to
Abbreviated as 18. Resistor 1 and Q2-Q9 are bias circuits 10
0, and the source electrode potential VG2 of Q7 and the drain electrode potential VG1 of Q6 are output voltages of the bias circuit 100. The MOS transistors Q10 to Q18 and the resistor 19 constitute a current cell 110. Q10-Q12 and Q16-
At the timing when Q18 is turned on / off by the switching signal, during the period when it is simultaneously turned on, VG2
A current flows from the output terminal to the ground via Q10-Q12 and Q16-Q18. At this time, Q7 operates as a source follower, and its output impedance rOUT is

[0014]

Equation 3 rout = 1 / gm = 1 / √ (2Iβ)

Where I is the drain current of Q7 and β
Is the channel width of Q7 and the channel length of L; Q7 is β = μoεoεs / tox × W / L W; As shown in Equation 3, even if the drain current of Q7 is reduced, Q7
The output impedance of Q7 can be reduced by increasing the channel width of Q7, that is, by increasing β of Q7, so that when a current flows from the VG2 output terminal to ground via Q10 to Q12 and Q16 to Q18, VG2
Can be suppressed.

In the first embodiment, 20 and 21 are the first and second
And the resistor 1 functions as a first resistor. The first to eighth transistors are Q4, Q5, Q6, Q8, Q9,
It is composed of Q2, Q3 and Q7.

As a specific example, a power supply voltage of 5 V, MO
When the conductivity coefficient of the S transistor is K = 20 μA / V ² , in the conventional example shown in FIG. 2, the impedance seen from the gate electrode of the MOS transistor 2, that is, the output of the bias voltage is r1 // ｛(gm22) ⁻¹ + (Gm23) ^-1 }, where r1 is the resistance of the resistance element 1, gm22 is the conductance of the MOS transistor 2, gm23 is the conductance of the MOS transistor 3, and r1 and gm2 are such that the impedance becomes 4 KΩ.
2. When gm23 is determined, r1 = 3V / 46.875 μA = 64 KΩ gm22 = gm23 = 1 / √ (2 × 46.875 μA × 20 μA / V ² × 117.1875) = 0.00046875 The current consumption of the circuit is 46.8
75 μA.

On the other hand, in the embodiment shown in FIG. 1, the impedance as viewed from the gate electrode of the MOS transistor 8, that is, the output of the bias voltage is (gm17) ^-1 / {(gm18) ^-1 + (gm19) ^-1 }. Gm17; conductance of MOS transistor, gm1
8; conductance of MOS transistor 8, gm19;
Gm17, gm so that this impedance becomes 4 KΩ.
When gm19 is determined, gm17 = √ (2 × 10 μA × 20 μA / V ² × 100) = 0.002 gm18 = gm19 = √ (2 × 10 μA × 20 μA / V ² × 100) = 0.001 And the current consumption of the bias circuit is 25 μA.

From the above calculations, if the impedances viewed from the output of the bias voltage in the bias circuits shown in FIGS. 1 and 2 are equal, the current consumption of the first embodiment is about 53% of the current consumption of the conventional example. , The current consumption is reduced to about half. The first embodiment also reduces the power supply voltage dependency of the current consumption of the bias circuit. As a specific example, a case where the power supply voltage VDD changes from 5V to 4.5V will be described. In the conventional example, if the voltage between the gate and the source of the MOS transistor and the MOS transistor 3 is determined to be equal, the voltage is set to VGS, the resistance 1 and the current flowing through the MOS transistors 2 and 3 are set to I1, and -2VGS / R1 I1 = β23 / 2 (VGS−VT) ² R1; resistance value of resistor 1, β23;
VGS when β I0 and I1 of 3 are equal is the bias voltage, and the value of I0 = I1 at that time is the current consumption of the bias circuit. When VDD = 5V, VGS = 1V, the current consumption is 50 μA, and when VDD = 4.5V, VGS = 0.98V, the consumption current is 40.5 μA, which is about 20% change.

In the bias circuit of the first embodiment, when the power supply voltage dependence is shown for the resistor 1 and the MOS transistor 2 which determine the current of the circuit, the current flowing through the resistor 1 is represented by I
2. If the current flowing through the MOS transistor 2 is I3, it can be expressed as I2 = VDD-VGS / R2 I3 = β2 / 2 (VGS-VT) ² . R2: resistance value of resistor 1, β2: β of MOS transistor 2. From VDD = 5V and VGS = 1V, current consumption is 5μ.
A, when V DD = 4.5 V, V GS = 0.99 V, the current consumption is 4.5125 μA, and the power supply voltage dependency is reduced by about 10% as compared with the conventional example.

As described above, in this embodiment, the current consumption of the bias circuit is reduced while maintaining the operation speed of the D / A converter (while maintaining the impedance as viewed from the output stage of the bias voltage).

FIG. 3 shows a second embodiment of the present invention.
The MOS transistor in the first embodiment has the first conductivity type changed to the second conductivity type, and the second conductivity type changed to the first conductivity type. In the first embodiment, the bias voltage is determined based on the second power supply 21, but the second embodiment is characterized in that the bias voltage is determined based on the first power supply 20.

In the second embodiment, the first to eighth transistors are constituted by Q34, Q35, Q36, Q38, Q39, Q32, Q33 and Q37, respectively.

[0024]

As described above, according to the present invention, D / A
Even if the current cell of the converter is switched, the current output set voltage VG1 does not fluctuate, and even if the current consumption of the bias circuit, that is, the drain current of Q7 is reduced, the bias voltage VG2
Can be suppressed, and the settling time of the D / A converter does not deteriorate even if the current consumption of the bias circuit is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1,11,19 Resistance element 2-18,32-38 MOS transistor 20 Power supply 21 Ground 22 Switching signal 23 Switching signal inversion signal 100 Bias circuit 110 Current cell

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 1/74 G05F 3/16 H01L 43/08 H03F 3/16

Claims (1)

(57) [Claims] A current cell type voltage-current conversion circuit;
A first conductive type first, second, third, fourth, fifth transistor having a gate electrode connected to a drain electrode, and a second conductive type sixth transistor.
A source electrode of the sixth transistor is connected to a first power source, a drain electrode of the sixth transistor is connected to a second power source via a first resistor, and a second conductive The source electrode of the seventh transistor is of the first type.
A power supply, a gate electrode of the seventh transistor is connected to a gate electrode of the sixth transistor, a drain electrode of the seventh transistor is connected to a drain electrode of the first transistor, A source electrode of the transistor is connected to a drain electrode of the second transistor, a source electrode of the second transistor is connected to a drain electrode of the third transistor, and a source electrode of the third transistor is connected to a second power supply. Connecting the drain electrode of the eighth transistor of the first conductivity type to the first power supply; connecting the gate electrode of the eighth transistor to the gate electrode of the first transistor; An electrode is connected to a drain electrode of the fourth transistor, and a source electrode of the fourth transistor is connected to a drain electrode of the fifth transistor. Connected to the poles, the source electrode of the fifth transistor connected to the second power supply, the voltage of the source electrode of the transistor of the eighth and the first output, the third
The gate voltage of the second transistor as a second output,
Setting the input bias of the current cell with the output of
A bias for determining a current value of the current cell is provided by the second output.
Bias circuit and wherein the providing.