JPH10275891A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability on the thermal stress of a semiconductor device by preventing damages to the inner lead which arises at manufacture of an area array type of surface-mounting type semiconductor device, where a TCP tape is applied. SOLUTION: A tape substrate 2, which has wiring 3 in which the main conductive layer is made of copper or copper alloy and its surface, is plated with gold, and a semiconductor chip 1 are bonded to each other by the adhesive layer 6 consisting of the elastic body having elastic modulus of 0.1-50 MPa, and an inner lead 9 integrally formed with the wiring 3 is connected to the wiring connection 11 made on a semiconductor chip 1 by ultrasonic bonding. At this time, the horizontal distance L from the junction at the wiring connection 11 and the tape ending face 8 which is the end face of the tape substrate is made 100 μm or over and preferably 390 μm, and the vertical distance H between the semiconductor chip 1 and the wiring 1 is made 150 μm or under.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technology effective when applied to an area array type surface mount type semiconductor device to which a TCP (Tape Carrier Package) is applied.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for a miniaturized package of a semiconductor device for use in applications where the area occupied by a mounting substrate is extremely limited, such as a portable information terminal or a mobile communication device. In addition, there is a strong demand for a technology that responds to the increase in the number of pins of a highly functional semiconductor device and that simultaneously reduces the area occupied by the mounting substrate.

[0003] As one of the techniques satisfying such requirements, a CSP (Chip Size Package) technique is known. In addition, as literatures which explain the technique regarding CSP in detail, for example, there is a press journal issued by April 20, 1995, "Monthly SemiconductorWorld" May, 1995, p104-p131.

[0004] In particular, a proposal by Tessera Corporation of the United States described in the same document, p112 to p113, or published in Nikkei BP, May 1, 1994, "Nikkei Microdevice" May 1994, p98 to p102. ΜBGA technology is superior to bare chip mounting or flip chip mounting in terms of ease of standardization of connection pitch, good absorption of difference in thermal expansion coefficient, ease of test such as burn-in, etc.
It is superior to TCP in terms of ease of handling during mounting and the like, and is considered to be a technology that is generally superior to other mounting technologies.

[0005] The technology of μBGA is disclosed in Japanese Patent Laid-Open Publication No. Hei 6-50440.
Japanese Patent Publication No. 8 is described in detail, and its outline is as follows.

That is, for example, wiring and bumps as outer leads are formed on a flexible tape of polyimide or the like to form a tape substrate having substantially the same area as the semiconductor substrate, and the tape substrate is formed by an adhesive layer made of an elastic material. A gull-wing inner lead formed by adhering to the surface and extending from an end surface of the tape substrate or a through hole opened in the tape substrate is connected to the wiring pad on the main surface of the semiconductor device by heat or ultrasonic pressure bonding. is there. The inner lead is formed as a part of the wiring formed on the tape substrate.

As described above, in the μBGA technology, the outer leads are formed on the surface corresponding to the entire surface of the semiconductor substrate, so that miniaturization is easy and handling is easy as described above. In addition, since the semiconductor substrate and the tape substrate are bonded with an elastic body, relative displacement between the two substrates is possible, and thermal stress due to a difference in thermal expansion coefficient between the members is reduced. Is possible.

The gull wing shape of the inner lead effectively acts to absorb the relative displacement between the semiconductor substrate and the tape substrate, and the wiring (ie, the inner lead) is made of a flexible material. Excellent gold is selected.

[0009]

However, if gold is selected as the wiring on the tape substrate, the material cost increases,
Price competitiveness decreases. Thus, it is clear that changing the wiring material from gold to copper plated with gold can greatly contribute to cost reduction, but the present inventors have found that there is a problem that the connectivity of the inner leads is reduced.

That is, when gold-plated copper is used as the inner lead, a crack is generated in the bent portion of the inner lead when the inner lead is connected to the connection pad on the main surface of the semiconductor substrate, and the ultrasonic energy during bonding is generated. Losses occur. Due to such a loss of ultrasonic energy, sufficient ultrasonic energy is not supplied to the connection portion between the inner lead and the connection pad on the main surface of the semiconductor substrate, and the metal fusion of the connection portion occurs sufficiently, resulting in poor bonding. It has been found.

[0011] Such poor bonding of the connection portion is as follows.
Although a connection failure may occur by itself, even if it is apparently connected, the connectivity may gradually deteriorate due to the application of thermal stress after mounting, leading to a connection failure. In such a case, there is a problem that the connection reliability of the inner leads is reduced, and the reliability of the semiconductor device is reduced.

An object of the present invention is to provide a technique for preventing damage to the inner leads when connecting the inner leads of the wiring formed on the tape substrate to the connection pads on the main surface of the semiconductor substrate.

Another object of the present invention is to provide a technique for improving the connection reliability between the connection pads on the main surface of the semiconductor substrate and the inner leads.

Still another object of the present invention is to provide a semiconductor device having high reliability against thermal stress after mounting.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention comprises: a semiconductor substrate having a wiring connection portion on a main surface thereof; a tape substrate adhered to the main surface side of the semiconductor substrate by an adhesive layer; A semiconductor device including a wiring patterned on the surface, an inner lead being a part of the wiring, extending from an end of the tape substrate at a predetermined angle with respect to the surface of the tape substrate, and connected to a wiring connection portion And
The horizontal distance L from the end of the tape substrate to the wiring connection portion in a plane parallel to the surface of the tape substrate and the vertical distance H from the main surface of the semiconductor substrate to the surface of the tape substrate on which the wiring is formed are H <150 μm, L> 100 μm.

According to such a semiconductor device, the horizontal distance L and the vertical distance H are H <150 μm, L> 1.
Since the condition of 00 μm is satisfied, the bending angle of the inner lead can be reduced to some extent, and no crack is generated in the inner lead. As a result, there is no loss in the ultrasonic energy at the time of bonding, the inner lead and the wiring connection portion can be connected with sufficient reliability, and the reliability of the semiconductor device can be improved.

The horizontal distance L can be increased to infinity under the above conditions, but is substantially limited by the number and arrangement of outer leads formed on the tape substrate.
That is, the inner lead is formed in an opening portion opened in the tape substrate or in an empty space from the end surface of the tape substrate to the end surface of the semiconductor substrate, but the size of the semiconductor substrate and the position of the wiring connection portion are determined in advance by design. Therefore, how much the horizontal distance L can be determined depends on how large the opening of the tape substrate can be made or how much the end face of the tape substrate can be set inside. Therefore, the area for arranging the outer leads occupied on the tape substrate is reduced by reducing the number of the outer leads, or by arranging the outer leads in a staggered arrangement, and the space for the inner leads is reduced. Will be secured. However, in reality, about several hundred μm is considered to be the limit in consideration of other pins. On the other hand, the length of the inner lead is preferably as low as possible because it is preferable that the length of the inner lead be low in consideration of the speeding up of the semiconductor device. However, as the length becomes shorter, the bending angle of the inner lead increases, and cracks are more likely to occur. The above-mentioned condition is a limit in harmonizing this point.

The vertical distance H can be set to 0 under the above conditions. However, the thickness cannot be substantially reduced due to restrictions on the manufacturing process of the adhesive layer, and the adhesive layer also acts as an elastic body as described above. Is required to be thick enough to absorb the displacement caused by the difference between the two, and therefore a film thickness of about 100 μm or more is required. On the other hand, if the thickness of the adhesive layer is too large, thermal expansion of the adhesive layer becomes a problem due to thermal stress after mounting, and it is not preferable that the thickness be 150 μm or more.

The above conditions of the horizontal distance L and the vertical distance H are conditions under which the probability of occurrence of cracks in the inner leads becomes remarkably empirical. By appropriately selecting the horizontal distance L and the vertical distance H, conditions for further reducing the bending angle can be exemplified.

For example, the horizontal distance L and the vertical distance H are
Conditions that satisfy H <150 μm and L> 280 μm can be exemplified. In such a case, the length of the horizontal distance L increases, and the probability of cracks occurring in the inner leads can be reduced.

Further, the horizontal distance L and the vertical distance H are H
<150 μm, L> 390 μm, for example. In such a case, the probability of occurrence of cracks can be reduced to a level where the occurrence of cracks does not matter. Note that the horizontal distance L and the vertical distance H in this case are substantially lower and upper limits.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor device according to the above (1), wherein the wiring is a conductor whose main conductive layer is copper and whose surface is plated with gold. .

According to such a semiconductor device, since gold-plated copper is used as the wiring under the conditions shown in (1), no crack is generated in the inner lead, that is, the reliability of the semiconductor device is improved. It is possible to reduce the cost of the semiconductor device while maintaining the same.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor device according to the above (1) or (2), wherein the adhesive layer is made of an elastic material having an elastic modulus of 0.1 MPa to 50 MPa. is there.

According to such a semiconductor device, since the adhesive layer is made of an elastic material having an elastic modulus of 0.1 MPa to 50 MPa, each member of the semiconductor device, particularly the difference in the coefficient of thermal expansion between the semiconductor substrate and the tape substrate. Owing to the displacement of the circuit board, the occurrence of thermal stress in the outer lead portion, which is the connection portion with the circuit board, can be suppressed. As a result, the reliability of the semiconductor device against thermal stress can be improved. Further, it is considered that by using such an adhesive layer having a relatively low elastic modulus, a relatively large stress is applied to a connection portion between the wiring connection portion of the semiconductor substrate and the inner lead of the wiring on the tape substrate. Since the connection is performed under the condition (1), the connection reliability of the inner lead is high, and the connection reliability of the inner lead against thermal stress does not decrease.

As such an elastic body, silicone or a rubber material based on silicone can be exemplified.

(4) A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate having a wiring connection portion on a main surface thereof, a tape substrate adhered to the main surface side of the semiconductor substrate by an adhesive layer, A semiconductor device including a wiring patterned on the surface, an inner lead being a part of the wiring, extending from an end of the tape substrate at a predetermined angle with respect to the surface of the tape substrate, and connected to a wiring connection portion. Then, a part of the wiring at the end of the tape substrate is peeled off from the tape substrate to be a part of the inner lead, thereby relaxing the angle.

According to such a semiconductor device, a part of the wiring at the end of the tape substrate is separated from the tape substrate to be a part of the inner lead, so that the wiring formed on the tape substrate and the inner lead are partly separated. The angle made is reduced and can be reduced. That is, it is possible to reduce the bending angle of the inner lead and suppress the occurrence of cracks in the inner lead. As a result, the reliability of connection of the inner leads to the wiring connection portion on the main surface of the semiconductor substrate can be improved, and the reliability of the semiconductor device against thermal stress can be improved.

[0031]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

FIG. 1 is a perspective view showing an example of an appearance of a main part of a semiconductor device according to an embodiment of the present invention. FIG.
In order to make the drawings easier to see in FIG. FIG. 2 is a sectional view taken along the line II-
FIG. 3 is a sectional view taken along line II, and FIG. 3 is an enlarged view of a part III in FIG.

The semiconductor device according to the present embodiment has a semiconductor chip 1 having a semiconductor circuit element formed on a main surface of a semiconductor substrate.
And a tape substrate 2 made of an organic material.

As a material of the tape substrate 2, for example, polyimide (Upilex) can be used, and its thickness can be set to 50 μm. In this regard, normal TC
P differs from using a tape having a thickness of 75 μm or 125 μm.

On one surface of the tape substrate 2, a patterned wiring 3 is provided, and on the other surface, bumps 4 functioning as outer leads are formed.

The wiring 3 can be made of a metal whose main conductive layer is copper or a copper alloy, for example, and its surface can be plated with gold. By using copper or a copper alloy as the main conductive layer in this manner, sufficient conductivity and current capacity can be ensured, and costs can be reduced as compared with the case where gold is used as the main conductive layer. The thickness and width of the wiring 3 can be set to, for example, 18 μm and 50 μm, respectively, and the interval between the wirings 3 can be set to, for example, 50 μm. However, both the width and the interval of the wiring 3 can be reduced to 25 μm.

The bump 4 can be, for example, a solder bump, and the diameter and height of the ball are, for example, 6
It can be 00 μm and 500 μm. However, the diameter and height are 300 μm and 200 μm, respectively.
It is possible to reduce to μm.

The wiring 3 and the bump 4 are connected via a connection hole 5 opened in the tape substrate 2. The opening diameter of the connection hole 5 can be, for example, 450 μm.
μm.

The semiconductor chip 1 and the tape substrate 2 are adhered by an adhesive layer 6. As a material of the adhesive layer 6, silicone rubber can be exemplified. The adhesive layer 6 functions as an adhesive between the semiconductor chip 1 and the tape substrate 2 and also functions as an elastic body, and its elastic modulus can be set to 0.1 to 50 MPa. As described above, since the semiconductor chip 1 and the tape substrate 2 are bonded by the adhesive layer 6 which is an elastic body, the thermal expansion between the circuit board and the semiconductor chip 1 after the semiconductor device is mounted, or the semiconductor chip 1 The thermal stress caused by the difference in the coefficient of thermal expansion from the tape substrate 2 is absorbed, and the stress acting between the bump 4 serving as the outer lead and the circuit board is reduced, so that the reliability of mounting can be improved.

In this embodiment, a tape opening 7 is formed in the center area of the tape substrate 2. Tape opening 7
In the tape end face 8 of the tape substrate 2 in FIG. That is, the material of the inner leads 9 is a material having copper or a copper alloy as a main conductive layer, similarly to the wiring 3, and the surface thereof may be gold-plated. The shape of the inner lead 9 is substantially the same as the shape of the wiring 3, and the width thereof can be, for example, 50 μm.

The lead end 10 of the inner lead 9 is connected to a wiring connecting portion 11 formed on the main surface of the semiconductor substrate of the semiconductor chip 1. That is, the inner lead 9
Is bent at the bent portion 12 on the tape end face 8,
The wire 3 is directed toward the wire connecting portion 11 at an angle with respect to the wire 3 and is connected at the wire connecting portion 11. Although FIGS. 1 to 3 show that it is bent only at the bent portion 12, it goes without saying that it is actually bent smoothly with an appropriate curvature. If the curvature of the inner lead 9 in the bent portion 12 and the wiring connection portion 11 is large, cracks occur in the inner lead 9 and loss of ultrasonic energy occurs when the inner lead 9 is connected. What is not performed well is as described above.

However, in this embodiment, the horizontal distance L between the lead end 10 and the tape end face 8 is 390
μm, and the vertical distance H between the position of the wiring 3 (the bent portion 12) on the tape end surface and the lead end 10 can be set to 150 μm. When the inner lead 9 is formed at such a horizontal distance L and a vertical distance H, cracks do not occur in the bent portion 12 of the inner lead 9, and no ultrasonic energy loss occurs when the inner lead 9 is connected. , Reliable bonding is performed. As a result, the connection reliability of the inner leads 9 is improved, and the reliability of the semiconductor device against thermal stress can be improved. Further, since sufficient connection reliability can be obtained, the adhesive layer 6
Even if an elastic body having a relatively low elastic modulus of 0.1 to 50 MPa is used, it sufficiently absorbs the relative displacement between the semiconductor chip 1 and the tape substrate 2 and is strong against thermal stress.
In addition, a highly reliable semiconductor device can be obtained.

It should be noted that reducing the horizontal distance L is effective for reducing the size of the semiconductor device and reducing the wiring resistance and wiring inductance. Therefore, the horizontal distance L can be further reduced, for example, to 280 μm. Furthermore, the horizontal distance L can be shortened, but cannot be less than 100 μm. That is,
If the horizontal distance L is 100 μm or less, the probability of occurrence of cracks in the inner leads 9 is empirically increased, and the possibility of bonding that lacks connection reliability increases.

The vertical distance H is 1 in this embodiment.
Although it is set to 50 μm, it can be further reduced. However, if the distance is further reduced, the relative displacement between the semiconductor chip 1 and the tape substrate 2 cannot be sufficiently absorbed, so that the value of the present embodiment is appropriate.

The wiring connection portion 11 is a power supply terminal or a signal input / output terminal of the semiconductor circuit element formed on the semiconductor substrate, and is generally a wiring pad of the semiconductor circuit element wiring formed on the main surface of the semiconductor substrate. Part. Gold plating or gold bumps may be formed on the wiring connection portion 11 to facilitate connection.

The tape opening 7 is embedded with a resin 13. By embedding the resin 13 in the tape opening 7, the inner lead 9 can be protected.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 4 to 6 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to the present embodiment in the order of steps.

First, a thin film 15 of copper or a copper alloy having a thickness of about 18 μm is formed on one surface of a polyimide tape 14 having a thickness of 50 μm (FIG. 4A).

Next, a resist 16 is formed on both surfaces of the copper or copper alloy thin film 15 (FIG. 4B). The resist 16 is patterned into a pattern corresponding to the wiring 3 to be formed later, and the patterning can be performed by a known screen printing method or a photolithography technique.

Next, the wiring 3 is formed by etching the copper or copper alloy thin film 15 using the resist 16 as a mask. Further, the resist 16 is removed (FIG. 4C).
The thin film 15 can be etched by a known wet etching method or dry etching method.

Next, the connection hole 5 and the tape opening 7 are formed in the polyimide tape 14 (FIG. 4D). At this time, the inner leads 9 are formed. For removing the polyimide tape 14, for example, an ablation method using a laser can be used. Immediately after this step, wiring 3
May be subjected to electrolytic plating to form gold plating. Since the width of the tape opening 7 is a dimension that determines the horizontal distance L determined in advance by design, it is necessary to open the tape so as to conform to the dimension and to ensure accuracy.

Next, bumps 4 made of solder are formed at the connection holes 5 (FIG. 4E). The bump 4 can be formed by, for example, electrolytic plating. The tape substrate 2 can be formed as described above.

Next, the tape substrate 2 is bonded to the semiconductor chip 1 via the bonding layer 6 (FIG. 5). As described above, a silicone resin is suitable for the adhesive layer 6, and has an effect of improving the connection reliability of the outer leads. Note that the thickness of the adhesive layer 6 needs to be such that the thickness after bonding is 150 μm, and the thickness before bonding needs to be optimized according to process conditions and the like.

Next, the lead end 10 of the inner lead 9
The tool 17 is pressed to the wiring connection portion 11 while bending the inner lead 9. In addition, tool 1
Ultrasonic energy is applied to 7 to connect the inner lead 9 to the wiring connection portion 11 (FIG. 6). As a connection method,
As a TCP bonding method, known gang bonding (batch method), single point bonding, or the like can be used. At the time of bonding in this step, since the above-mentioned conditions of the horizontal distance L and the vertical distance H are satisfied, no crack occurs in the inner lead 9, and poor bonding due to loss of ultrasonic energy does not occur. Note that bonding by heating may be used in addition to the ultrasonic energy.

Finally, the resin 13 is filled in the tape opening 7 to complete the semiconductor device shown in FIGS.

According to the semiconductor device of this embodiment, since the horizontal distance L is 390 μm and the vertical distance H is 150 μm, when the inner lead 9 is connected to the wiring connection portion 11, cracks or the like Therefore, the connection between the inner lead 9 and the wiring connection portion 11 can be performed with sufficiently high reliability without causing a defect that causes a loss in the ultrasonic energy. As a result, the connection reliability in the wiring connection portion 11 is improved, and even if the relative position change occurs between the semiconductor chip 1 and the tape substrate 2 due to the elastic deformation of the adhesive layer, that is, the inner leads in the wiring connection portion 11 Even if stress occurs at the connection point of No. 9, the connection is not easily broken. As a result, a semiconductor device with high reliability against thermal stress often generated after mounting the semiconductor device can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, as shown in FIG. 7, a part of the wiring 3 in the vicinity of the tape end face 8 may be peeled off to reduce the curvature of the bent portion of the inner lead 9.
In such a case, the probability of occurrence of cracks in the bent portion can be reduced, the connection reliability of the inner leads 9 can be improved, and the reliability of the semiconductor device can be improved.

In the present embodiment, the tape opening 7
Is provided at the center portion of the semiconductor chip 1, but may be provided at both ends or the peripheral portion of the semiconductor chip 1.

Further, in this embodiment, the case where the tape substrate 2 is made of polyimide is exemplified. However, other organic materials may be used, and the material of the bumps 4 is solder. Needless to say, it is good.

[0061]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Damage to the inner leads when connecting the inner leads of the wiring formed on the tape substrate to the connection pads on the main surface of the semiconductor substrate can be prevented.

(2) The connection reliability between the connection pads on the main surface of the semiconductor substrate and the inner leads can be improved.

(3) A semiconductor device with high reliability against thermal stress after mounting can be provided.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an example of an appearance of a main part of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line II-II in FIG.

FIG. 3 is an enlarged sectional view of a part III in FIG. 2;

FIG. 4 is a cross-sectional view illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 5 is a sectional view showing an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;

FIG. 7 is a fragmentary cross-sectional view showing another example of the semiconductor device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 tape substrate 3 wiring 4 bump 5 connection hole 6 adhesive layer 7 tape opening 8 tape end surface 9 inner lead 10 lead end 11 wiring connection portion 12 bent portion 13 resin 14 polyimide tape 15 thin film 16 resist 17 tool H vertical Distance L Horizontal distance

Claims (6)

[Claims] 1. A semiconductor substrate having a wiring connection portion on a main surface thereof, a tape substrate adhered to the main surface side of the semiconductor substrate by an adhesive layer, and a wiring mainly patterned on a surface of the tape substrate. A semiconductor device comprising: an inner lead that is a part of the wiring, extends from an end of the tape substrate at a predetermined angle with respect to a surface of the tape substrate, and is connected to the wiring connection unit. A horizontal distance L from the end of the tape substrate to the wiring connection portion in a plane parallel to the surface of the tape substrate, and a vertical distance from the main surface of the semiconductor substrate to the surface of the tape substrate on which the wiring is formed A semiconductor device, wherein H satisfies the following condition: H <150 μm, L> 100 μm. 2. The semiconductor device according to claim 1, wherein the horizontal distance L and the vertical distance H satisfy the following condition: H <150 μm, L> 280 μm. 3. The semiconductor device according to claim 1, wherein the horizontal distance L and the vertical distance H satisfy the following condition: H <150 μm, L> 390 μm. apparatus. 4. The semiconductor device according to claim 1, wherein the wiring is a conductor whose main conductive layer is copper and whose surface is plated with gold. 5. The semiconductor device according to claim 1, wherein the adhesive layer is an elastic body having an elastic modulus of 0.1 MPa to 50 MPa. 6. A semiconductor substrate having a wiring connection portion on a main surface thereof, a tape substrate adhered to the main surface side of the semiconductor substrate by an adhesive layer, and a wiring mainly patterned on a surface of the tape substrate. A semiconductor device comprising: an inner lead that is a part of the wiring, extends from an end of the tape substrate at a predetermined angle with respect to a surface of the tape substrate, and is connected to the wiring connection unit. A part of the wiring at an end of the tape substrate is peeled from the tape substrate to be a part of the inner lead,
A semiconductor device, wherein the angle is reduced.