JPH1026961A - Image display device driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make possible a display with large display capacity and a large area by changing a voltage applied to a liquid crystal at every pixel, gradation displaying and inputting the data to a pixel electrode of a liquid crystal display body with line sequential operation. SOLUTION: An image display device is constituted of a shift register 1, a latch 2, a digital/analog converter 3 and the liquid crystal display body 4. At this time, a digital input to the digital/analog converter 3 outputted in parallel written in the latch 2 by a write enable signal W becomes a value complementarily inverted to a just before frame value, and since the output of the digital/analog converter 3 is constituted so as to become the value inverted to common electrode potential Vc by such a input conversion, a voltage D(J)-Vc(J=1-N) applied to the pixel is inverted with the just before frame in its code at every even frame, and the liquid crystal is AC driven. Although the display of eight gradation is shown in figure, generally, the display of 2<n> gradation is obtained by a data input of n bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal image sandwiched between a substrate on which a column electrode is formed and a counter substrate on which a plurality of pixel electrodes selected by a common electrode or a row electrode orthogonal to the column electrode are formed. It relates to a display device.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional image display device has a substrate on which a plurality of column electrodes indicating connection terminals and potentials are formed by D (1) to D (N), and electrode terminals by V _C. It is composed of a liquid crystal display (6) sandwiched between opposing substrates on which a common electrode indicating a potential is formed. Data to a column electrode is transferred in series by a shift register (5) with data D by a clock CL. After a group of data transfer corresponding to (1) to D (N) is completed, the shift register is kept stationary for a certain period of time, and the parallel output of each bit is applied to D (1) to D (N).

V _DD and V _SS (V _DD > V _SS ) are the power supply terminal and potential of (5). After data D is transferred at V _C = V _SS ,
D (J) -V _C voltage (J = 1) applied to the pixel of (6)
To N) are sign-inverted by transferring data inverted from the previous frame in the next frame of V _C = V _DD ,
The liquid crystal was driven by AC.

[0004]

Therefore, the voltage applied to the pixel can be displayed (lit) or erased (non-lit).
There is a structural problem in realizing a display with gradations of light and shade by changing the voltage only by changing the voltage.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is an image display apparatus provided with an active element and a display using a liquid crystal. An electrode group is arranged in a matrix so as to be orthogonal to each other, active elements are provided corresponding to a matrix of row electrodes and column electrodes, a pixel electrode and a common electrode facing the pixel electrode are provided, and between the opposing substrates. There is provided a row-side shift register for holding a liquid crystal, turning on a pixel connected to the same row electrode and transmitting a signal for selecting a pixel, a digital / analog converter connected to the column electrode is a decoder,
A voltage divider circuit and a switch are provided.The voltage divider circuit is provided with a plurality of output potentials that are divided by a reference voltage with a resistor to match the optical characteristics of the liquid crystal, and sequentially selects each row from a row-side shift register. The output potential is supplied to the column electrode through a switch, and the digital image data composed of n bits per column is transferred through the shift register on the column side. Digital image data is supplied to the digital / analog converter almost simultaneously through a latch, and is converted into a selected output for each column by a decoder, and a switch is controlled by the selected output so that one of the output potentials is converted as analog image data. The signal is selected and sent to each column electrode, is stored in the pixel electrodes of all columns in a certain row, and further has the potential of the common electrode and the analog voltage. Polarity of the voltage between the image data is inverted at a predetermined period AC driving of the liquid crystal is performed to provide an image display apparatus characterized by display of 2 ⁿ gradations can be performed.

FIG. 1 is a diagram showing the configuration of an image display device according to the present invention, wherein (1) is a shift register, (2) is a latch,
(3) shows a digital / analog converter, and (4) shows a liquid crystal display.

[0007] (4) formed a common electrode of a substrate and electrode terminals and potential in V _C having a plurality of column electrodes indicating the connection terminals of the (3) in D (1) to D (N) Data D (J) consisting of liquid crystal sandwiched between opposing substrates and applied to column electrodes
(J = 1 to N), the data D ₀ , D ₁ , and D ₂ are serially transferred by the clock CL according to (1), and D ₀ ^S (1), D
₁ ^S (1), D ₂ ^S (1) to D ₀ ^S (N), D ₁ ^S (N), D ₂ ^S
After completing a group of data transfer corresponding to (N), the output of each bit of (1) is written in parallel to (2) by the write enable signal W, and the outputs D ₀ (J), D ₁ (J),
D ₂ (J) (J = 1 to N) is obtained by digital / analog conversion for each column.

V _DD , V _SS (V _DD > V _SS ) are given by (1),
A power supply terminal, the potential of the (2), V _CC is taken V _CC ≦ V _SS, become power supply terminal and potential along with V _DD (3), V
_R is a reference voltage input of (3) that determines an analog output for the common electrode potential V _C of (4).

[0009]

The operation is shown in the timing chart of FIG.
(1) is composed of three sets of shift registers for transferring D ₀ , D ₁ , and D ₂ , wherein CL is V _SS and D ₀ , D ₁ , D ₂
D ₁ and D ₂ are read, and data is transferred to the next stage at V _DD . D (J) is at the potential of V _CC ~V _R, taken V _CC V _C is for each frame, the potential of V _R alternately, D _0, D _1,
D ₂ is in the inverted data and the immediately preceding frame for each even frame.

From this, the digital input D ₀ to (3), which is written in (2) by W and is output in parallel, by W
(J), D ₁ (J), D ₂ (J) (J = 1 to N) are values that are complementarily inverted with respect to the value of the immediately preceding frame, and the output of the digital / analog converter is as described above. Do the input conversion because it is configured such that the inverted value of relative V _C, the voltage D (J) -V _C according to the pixels, the frame and the sign is inverted immediately before every even-numbered frame, the liquid crystal AC drive is performed.

FIG. 1 shows a digital / digital conversion of 3-bit data.
Since the analog conversion is performed, the image display device has eight gradations.
An image display device with ⁿ gradations is obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Such an image display device of the present invention is applied to an image display device in which liquid crystal is driven using a plurality of active elements such as transistors or diodes formed on the same substrate as switches.

FIG. 4 shows a configuration of a pixel of an image display device driven by a transistor formed for each pixel, and shows four pixels (I, J) to (I + 1, J + 1). (7) is a transistor, (8) is a storage capacitance of a display voltage, (9) is a pixel electrode, (10) is a common electrode on the substrate facing (9), (11) is a liquid crystal, and (12) is a gate. Row electrodes for transmitting signals, and (13) are column electrodes for transmitting source signals.

The transistor turned on by the gate signal G (I) transmits the source signals D (J) and D (J + 1) to each pixel electrode, and changes the voltage between (10) and (8) and (11). The voltage is stored in the parallel capacitor as a display voltage, and an image is displayed with the stored voltage when the capacitor is turned off.

The one-sided electrode (8) and (10) are connected in common and have a potential of V _C , and the parallel capacitance of (8) and (11) is equal to the gate-drain capacitance of (7). keeping since sufficiently large, the constant little dependence between, on the potential change of V _C displaying voltage off transistor is disposed between (9) and (10) with respect to.

FIG. 5 is a block diagram of an image display device having the pixels shown in FIG. 4, and is a first embodiment of the present invention. According to FIG. 1, (14) is a shift register, (15) is a latch, (16), (17) and (18) are digital /
An analog converter is constructed, and (20) sets (7), (8), (9), (12), and (13) of the pixel shown in FIG. 4 so that the row electrode group and the column electrode group are orthogonal to each other. A display comprising a liquid crystal (11) sandwiched between a plurality of substrates arranged in a matrix and a counter substrate on which a common electrode (10) is formed;
(19) is a shift register for transmitting a gate signal for sequentially turning on a transistor group connected to the same row electrode for each row.

G (1) to G (M) denote connection terminals and potentials with the row electrode groups of the plurality of rows in (20), and V _G , V _EE (V _G
> V _SS ≧ V _EE) is a power supply terminal, the potential of the (19), shifts the data D _G clock CL _G, G (1) ~G
The gate signal of (M) is created. Latch output D ₀
(J), D ₁ (J), D ₂ (J) (J = 1 to N) are converted to d ₁ (J), d ₂ (J), d ₃ by the decoder (16).
(J), d ₄ (J), d ₅ (J), d ₆ (J), d ₇
(J), 8 outputs of d ₈ (J), and the voltage dividing circuit (17)
V _1, V _2, V ₃ outputted _{from, V 4, V 5, V} 6,
Controls the switch (18) connected to the potential of V _7, V _8, are making analog image data D (J) to be sent to the source electrode of the select potential (20).

The power supply of the digital / analog converter consisting of (16), (17) and (18) is V _CC = ( _C ) in FIG.
Taken at V _SS, (17) is divided by combined resistance to the liquid crystal of the optical properties of the voltage between the terminals of the V _R -V _C (20). As shown in the timing chart of FIG.
, The data D ₀ , D ₁ , and D ₂ are serially transferred by the clock CL, and D ₀ ^S (1), D ₁ ^S (1), D ₂ ^S (1) to D _{2
^{0 S (N), D 1}} S (N), after the end of the group of data transfer corresponding to D ₂ ^S (N), a gate signal line is V _G becomes the same row of the pixel group (20) (19) The transistor is turned on, and the output of each bit of (14) is written in parallel to (15) by the write enable signal W, and its output D ₀
Data D (J) obtained by digital / analog conversion for each column of (J), D ₁ (J), D ₂ (J) (J = 1 to N) is stored in the pixel electrode through the column electrode.

The data of the next line while the gate signal of this line is in the V _G is transferred (14), a gate signal V
Becomes _EE and transistors of the pixel group is off the line, write the gate signal of the next line is V _G from V _EE out next write enable signal output (14) to (15), (16), The data converted by (17) and (18) is transmitted to the pixel. Such a sequence is G
The display voltages of all the pixels of (20) are determined in one frame repeated M times by the gates of (1) to G (M).

The data cycle to the pixels in this embodiment is symmetrically inverted with respect to one frame for storing various display data in all pixels and one frame for storing uniform erase data in all pixels and the common electrode potential. This cycle is composed of a total of four frames, one frame in which display data to be written is stored in all pixels and one frame in which erase data is stored in all pixels. The above is the driving.

The common electrode potential V _C becomes two frames V _SS before and two frames V _RO after this in accordance with this cycle.
Determining the analog output for V _C (16), (1
7) and (18), the value of the reference potential V _R of the digital / analog converter is set to two frames V _RO before and two frames V V after
_SS, and the value of the reference voltage between V _{R and} V _{C is} V
_The liquid crystal is AC-driven by inverting at a predetermined cycle every two frames as _RO− V _SS and the latter two frames V _SS −V _RO .

The effective voltage applied to the liquid crystal in the pixel is a voltage between the display data V _C and V _X , and a voltage between the erase data V _C and V ₀ (V ₀ = V ₁ -V _C ). Then (V _X ² +
Since V ₀ ² ) ^0.5 / 2 ^0.5 , (17) determines the resistance ratio so that gradation display is performed with an effective value, and V _{1 to} V ₈
Of potential. Therefore, the potential of one row J column of the pixel electrodes D (1 J) is inverted D (1J) -V _C every 2 frames with V _C has a 50% duty AC waveform.

FIG. 7 shows a pixel configuration of an image display device of a driving system different from that of FIG. 4, and (I, J) to (I + 1, J +
1 shows four pixels. (21) is a transistor, (22) is a storage capacitance of a display voltage, (23) is a pixel electrode, (24) is a column electrode on a substrate facing (23),
(25) is a liquid crystal, (26) is a row electrode for transmitting a gate signal, (27) is one side electrode of (22) commonly connected in a column on a substrate on which transistors opposed to (24) are integrated. a source signal V _a for transmitting the column electrodes (28) is a source signal to be connected to (24). Transistors turned on by the gate signal, the parallel capacitance of convey the potential of the source signal V _a to the pixel electrodes, the column electrodes D (J), D a difference voltage between the signals from the (J + 1) (22) and (25) The display voltage is stored as a display voltage, and an image is displayed at the stored voltage when the display is off.

As described with reference to FIG. 4, since the parallel capacitance of (22) and (25) is sufficiently larger than the gate-drain capacitance of (21), data is stored between (23) and (24). While the transistor is off, the displayed display voltage is kept almost independent of the potential changes in (24) and (27).

FIG. 8 is a block diagram of an image display device having the pixels shown in FIG. 7, showing a second embodiment of the present invention, and FIG. 9 is a timing chart showing the operation thereof.

(29) to (35) correspond to (1) in FIG.
4) to (20), which are different from the first embodiment in that (35) is a substrate on which a plurality of column electrodes (24) of the pixel shown in FIG. 7 are formed, and (21) , (22),
(23), (26), (27), and (28) are arranged in a matrix so that the row electrode group and the column electrode group are orthogonal to each other, and a plurality of rows selected by the row electrode orthogonal to the column electrode (24). (35) that constitutes a digital / analog converter formed for each column electrode (31), (32). ), (33 of) is that it is fixed reference voltage V _R -V _SS (32).

[0027] placed in the pixel electrode common source signal V _a to the plurality of column electrodes when a gate signal is a pixel group of transistors (35) of V _G becomes the same row are turned on one row (34) Therefore, this line Data is added through column electrodes D (J) (J = 1 to N) so that an analog voltage applied to the liquid crystal is determined with respect to the potential of the pixel electrode selected by the electrode.

The data of the next line while the gate signal of this line is in the V _G is transferred (29), a gate signal V
_EE (≦ 2V _SS −V _RO ), the transistor of the pixel group in that row is turned off, and when the gate signal in the next row changes from V _EE to V _G , a write enable signal W is output and the parallelization of each bit of (29) is performed. The output is written to (30), and data obtained by converting the output of (30) by the digital / analog converters of (31), (32), and (33) is transmitted to the pixel.

The data cycle to the pixel in this embodiment is:
From a total of two frames, one frame in which various display data is stored in all pixels, and one frame in which display data inverting symmetrically to the data of the previous one frame with respect to the potential of the pixel electrode selected by the row electrode are stored in all pixels. It is configured.

The potential of the pixel electrodes selected by the row electrodes according to the source signal V _a has become before one frame V _SS, after one frame V _RO, input D ₀ to the shift register,
Since D ₁ and D ₂ are data inverted from the preceding one frame in the succeeding frame, the digital inputs D ₀ (J), which are written in the latch by W and output in parallel, are output to the digital / analog converter. D ₁ (J) and D ₂ (J) are values complementary to the value of the preceding one frame in the subsequent one frame, and the decoder responds to this complementary input with d _k (J) → The selection of the switch is changed so that d _9−k (J) (k = 1 to 8), and the voltage dividing circuit performs V _k −V _SS = V
Since that defines the potential of V ₁ ~V ₈ to _R -V _9-k,
The output voltage of the digital / analog converter is inverted at a predetermined cycle for each frame with respect to the potential of the pixel electrode selected by the row electrode, thereby performing AC driving of the liquid crystal.

[0031] When the voltage of the previous frame according to the liquid crystal and V _X, after one frame -V _X, and the (32) as described above the voltage specified lighting of the liquid crystal, the non-lighting between V _R -V _SS In accordance with the characteristics, the voltage is divided by a resistor so that gradation display is performed, and the voltage D (J) -D applied to the liquid crystal of the pixels in one row and J columns is applied.
Driving is performed at a duty of 100% as shown in (1J).

FIG. 10 is a timing chart according to a second embodiment of the present invention, which is a modification of the timing chart shown in FIG. Potential of the pixel electrodes selected by the row electrodes according to the source signal V _a is V _SS or V _RO, the column electrode signal D
Since (J) is between V _{SS and} V _RO , during one frame from the time when the potential of the pixel electrode selected by the row electrode is V _SS , the potential D (IJ) of the pixel electrode throughout the non-selection period
(I = 1 to M, J = 1 to N) are in 2 V _SS -V _{RO to} V _RO , and D (IJ) for one frame from V _RO is V _SS to V _SS .
In the 2V _RO -V _SS.

In FIG. 9, a gate signal for controlling a transistor for each pixel is represented by V _G (> V _RO ) for selecting a pixel and turning on the transistor, and V _EE (≦ ≤ for deselecting the pixel and turning off the transistor. 2V _SS −V _RO ), but in FIG. 10, the potential of D (IJ) is noted,
One frame from the time when the potential of the pixel electrode selected by the row electrode is V _SS is V _G for turning on the transistor.
+ V _SS -V _RO (> V _SS ), V _EE (≦ 2V _SS -V _RO ) to turn off the transistor, and one frame from V _RO , V _G (> V S) to turn on the transistor.
_RO ), V _EE + V _RO -V to turn off the transistor
_SS (≦ V _SS) and to, shortening the pulse height of the gate signal for each frame to _{V G + V SS -V RO -V} EE (<V G -V EE), G (1) ~G of (M) Each gate signal is output.

In FIG. 5 and FIG. 8, the digital / analog converter has one voltage dividing circuit, and the decoder and the switch are formed for each column electrode of the display. A digital circuit may be provided to perform digital / analog conversion.

Also, what is called the common electrode / potential in the configurations of FIGS. 1 and 5 is the pixel electrode / potential selected by the row electrode orthogonal to the column electrode of the configuration shown in FIG. Can be achieved in a similar manner. The same applies to the case where the pixel electrodes and the potentials selected by the row electrodes orthogonal to the column electrodes in the configuration in FIG. 8 are the common electrodes and the potentials in the configurations shown in FIGS.

Therefore, it is assumed that this point is taken into consideration in the following examples, and a liquid crystal display body sandwiched between a substrate on which a plurality of column electrodes are formed and a counter substrate on which a common electrode is formed is used. Describes an image display device, an image using a liquid crystal display body sandwiched between a substrate on which a plurality of column electrodes are formed and a counter substrate on which a plurality of pixel electrodes selected by row electrodes orthogonal to the column electrodes are formed It also includes a display device.

Next, a description will be given with reference to FIGS.
Note that common circuit elements and driving methods used in each example can be applied in combination in other examples. First, FIG. 11 shows (16), (17), (1) in FIG.
8), (31), (32), and (33) of FIG. 8 show alternative digital / analog converters, and FIG.
2 shows an operational amplifier used in the circuit shown in FIG. While the digital / analog converters of FIGS. 5 and 8 are of the voltage selection type, FIG. 11 is of the current selection type.

Each of them is constituted by an integrated circuit of a complementary connection insulated gate type field effect transistor. An operational amplifier (36) inverts the reference voltage V _R -V _CC and outputs current source transistors (38), (41) and (4).
3), (45) and (47) are controlled, and the resistance of r (39)
Is a non-inverting input.

(37), (40), (42), (4)
4) and (46) are (38), (41), (43) and (4)
5) and (47) are switch transistors for turning on / off the current paths, and have sufficiently lower on-resistance than the current source transistors, and (38) / (41 + 2L) (L = 0 to 0).
3) Channel width / channel length ratio and (37) / (4)
0 + 2L).

(37) where the gate voltage is V _SS is always on, and the current flowing through (39) by (38) is such that the voltage between the electrodes of the resistor becomes V _R -V _CC (36).
Is determined by

The current source transistors in an integrated circuit is disposed close normalized channel width / channel length performance is equivalent, from the fact that the gate input of the operational amplifier output V ₀ in common, the current source transistor Channel length / channel length of (38) β, (41) β
_p , (43) β ₀ , (45) β ₁ , (47) β ₂ ,
If the resistance of (48) is R, the output is D (J) = (V _R −
V _CC ) R (Pβ _p + D ₀ (J) β ₀ + D ₁ (J) β ₁ +
D ₂ (J) β ₂ ) / rβ + V _CC , (P, D ₀ (J), D
₁ (J) and D ₂ (J) become 0 at V _DD and 1) at V _SS , and by setting r, R, β _p , β ₀ , β ₁ , and β ₂ to appropriate values, P , D ₀ (J), D ₁ (J) and D ₂ (J) are obtained by digital / analog conversion of digital inputs.

For example, r = R, β ₂ = 2β ₁ = 4β ₀ , β
= V _CC ~ digital input of β ₀ + β ₁ + β ₂ with them if V _SS ~V _DD analog voltage _{(V R -V CC) (1} + β p / β) + V CC is, (V _R -V _CC) / 7 is output with a 3-bit weight of the unit voltage.

In (36), simply, an operational amplifier having a bias stage and a differential amplifier stage can be used.
The circuit illustrated in FIG. 1 uses P-channel transistors (54) and (55) which are close and identical in shape as an active load, and are connected to the gates of N-channel transistors (52) and (53) which are close and identical in shape. differential input V _+, V _-
And connect the source to an N-channel transistor (5
1) a differential amplifier stage connected to a constant current source; and a bias stage in which a P-channel transistor (49) serving as a load resistor is connected to an N-channel transistor (50) connected to a gate / drain and the gate of (51). An operational amplifier consisting of

Although the digital / analog converter is formed for each column electrode of the liquid crystal display, (36) can be shared by a plurality of columns of digital / analog converters as in the voltage dividing circuit described above. The resistors (48) for determining (J) are arranged on the integrated circuit in a plurality of columns so as to be close to (39).

(V _R -V _CC ) β _p / β is the value of V in FIGS.
₁ using -V _C, V ₁ -V _SS, to set a predetermined voltage corresponding to V _R -V _8, and the switch (40) in P, it is achieved by controlling the (41) .

FIG. 13 is a block diagram of an image display device having the digital / analog converter shown in FIG. 11 for each column of the liquid crystal display composed of the pixels shown in FIG. FIG. 14 is a timing chart thereof. (56), (57), (59), and (60) correspond to (14), (15), (19), and (20) in FIG. 5, respectively.

In step (56), the data D ₀ , D ₁ , and D ₂ are serially transferred by the clock CL, and D ₀ ^S (1), D
₁ ^S (1), D ₂ ^S (1) to D ₀ ^S (N), D ₁ ^S (N), D ₂ ^S
After completion of a group of data transfer corresponding to (N), to turn on the transistor gate signal line is a pixel group (60) of V _G next same line (59).

The output of each bit of (56) is written to (57) by the write enable signal W, and its output D ₀
(J), D ₁ (J), D ₂ (J) (J = 1 to N)
In step 8), the data D (J) obtained by digital / analog conversion for each column as shown in FIG. 11 is stored in the pixel electrode through the column electrode.

The data of the next line while the gate signal of this line is in the V _G is transferred to (56), a gate signal V
And pixel groups of transistors are off the line becomes _EE, converting the gate signal of the next line is V _G from V _EE out next write enable signal output (56) to (57) by writing (58) The transmitted data is transmitted to the pixel.

The data cycle to the pixel in this embodiment is
It is composed of a total of two frames, one frame for storing various display data in all pixels and one frame for storing display data, which is inverted symmetrically to the data with reference to the common electrode potential V _C , in all pixels. Being driven.

The common electrode potential V _C becomes one frame V _CC before and one frame V _RO after this in accordance with this cycle.
Since the inputs D ₀ , D ₁ , and D ₂ to the shift register are data inverted from the previous one frame in the subsequent one frame, the data is written to the latch by W and output to the digital / analog converter in parallel. Digital input D ₀
(J), D ₁ (J), D ₂ (J) are one frame after and one frame before
It is a value that is complementarily inverted to the value of the frame, and the switch input P for setting a predetermined voltage is also set to the voltage in the previous one frame V _SS , and not to be set in the subsequent one frame V _DD Therefore, the output of the digital / analog converter in which the reference voltage input is constant at V _RO -V _CC is inverted at a predetermined period for each frame with respect to the potential of the common electrode, and the liquid crystal is AC-driven.

The channel width / channel length of the current source transistor of the digital / analog converter shown in FIG. 11 is determined to an appropriate value (in FIG. 14, β = β _p + β ₀ + β
₁ + β ₂ , β _p , β ₀ <β ₁ <β ₂ ), and an analog output corresponding to a digital input is output in accordance with the optical characteristics of the liquid crystal for gradation display. Therefore, D (1J) of the pixel electrode in one row and J column is inverted every frame together with V _C , and D (1J) −V _C has an AC waveform with a duty of 100%.

FIG. 15 is a timing chart of a third embodiment of the present invention, which is a modification of the timing chart shown in FIG. When the common electrode potential V _C is V _CC , the potential of the pixel electrode is between 2 V _CC -V _{RO and} V _RO , and when V _C is V _RO , it is between V _{CC and} 2V _RO -V _CC .

In FIG. 14, a gate signal for controlling a transistor for each pixel is represented by V _G (> V _RO ) for selecting a pixel and turning on the transistor, and V _EE (≦ ≤ for deselecting the pixel and turning off the transistor. 2 V _CC -V _RO ), but in FIG. 15, when the common electrode potential V _C is V _CC , V _G + V _CC -V is used to turn on the transistor.
_RO (> V _RO ), V to turn off the transistor
_EE (≦ 2V _CC −V _RO ), when V _C is V _RO , V _G to turn on the transistor, V _EE + V _RO −V _CC (≦ V _CC ) to turn off the transistor, and the gate signal the height of the pulse _{V G + V CC -V RO -V} EE (<V G -
V _EE ), and gate signals G (1) to G (M) are output.

FIG. 16 is a timing chart showing the operation of the image display apparatus of the fourth embodiment having the same configuration as the image display apparatus shown in FIG. FIG. 16 is different from FIG. 14 in that the clock CL and the data D input to the shift register
₀ , D ₁ , D ₂ , a signal W for enabling data writing to the latch, and a switch input P for setting a predetermined output voltage to the digital / analog converter are similar signals. The power supply V _CC and the reference voltage input V _{R of the} analog converter change every frame,
The common electrode potential V _C is constant.

[0056] The digital / analog converter shown in FIG. 11, the reference voltage input V _R, the output D (J) both the power supply potential V
_{It is} determined for _CC , and D (J) -V _CC is determined to be constant when V _R -V _CC is kept constant.

In FIG. 16, before P becomes V _SS , 1
In the frame, V _R is V _RO , V _CC is (V _RO + V _CO ) / 2
In the subsequent one frame, the inputs D ₀ , D ₁ , and D ₂ to the shift register are the data inverted from the previous data, so that the digital / analog data written to the latch by W and output in parallel is output. The digital inputs D ₀ (J), D ₁ (J), and D ₂ (J) to the converter have values that are complementarily inverted in the subsequent one frame with the values in the preceding one frame, and P is V _DD , V _R There _{(V RO + V CO) /} 2, and it V _CC is V _CO, regardless of the common electrode potential V _C frame (V _RO + V
_CO ) / 2, and the channel width / channel length of the digital / analog converter is β = β _p + β ₀ + β
_Since it is selected to be ₁ + β ₂ , the potential entering the pixel is (V _RO + V _CO ) / 2 to V _{RO in} the first frame, and is inverted symmetrically with respect to V _C in the last frame with reference to V _C. (V
_RO + V _CO) / _{2~V CO,} and the liquid crystal AC driving which inverts at a predetermined period for each frame have been made.

Therefore, the potential D of the pixel electrode in the first row and the J column is
(1 J) is inverted every frame to V _C, D (1
J) -V _C shows a 100% duty of the AC waveform.

In order to perform a color display with the image display device having the digital / analog converter according to the first to fourth embodiments described above, a transparent common electrode or a column electrode is formed on a substrate which is close to the electrode. R (red), G (green), B
The three primary color filters (blue) are arranged corresponding to the pixel electrodes on the opposite substrate, and the color data D ₀ , D ₃ , D 4 _,. This is achieved by transferring D ₁ and D ₂ to a shift register and putting the digital / analog converted output after latching into the pixel electrodes of the selected row.

That is, a light source is arranged behind a color filter of a liquid crystal display, a liquid crystal array is controlled for each pixel by a voltage applied to the liquid crystal, and a color image is displayed by changing the amount of light transmitted through the color filter and the liquid crystal. .

[0061]

As described above, the image display apparatus of the present invention has a configuration in which a digital / analog converter provided with a voltage dividing circuit, a decoder, and a switch common to each column electrode of a liquid crystal display is arranged. By doing so, it is possible to perform gradation display by changing the voltage applied to the liquid crystal for each pixel, and to input the data into the pixel electrodes of the liquid crystal display in a line-sequential operation. The period of analog conversion into the pixel electrode is the frame period / the number of rows of pixels, and since there is a margin in the data setting time, the number of rows and columns of pixels is increased to display a large display capacity and a large area. It has excellent characteristics that can realize the following.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an image display device of the present invention.

FIG. 2 is a configuration diagram of a conventional image display device.

FIG. 3 is a timing chart showing the operation of the image display device of FIG. 1;

FIG. 4 is a configuration diagram of a pixel of an image display device driven by a transistor formed for each pixel.

FIG. 5 is a configuration diagram of a first embodiment of the present invention having the pixel of FIG. 4;

FIG. 6 is a timing chart showing the operation of the first embodiment of FIG.

FIG. 7 is a configuration diagram of a pixel of an image display device driven by a transistor formed for each pixel.

FIG. 8 is a configuration diagram of a second embodiment of the present invention having the pixels of FIG. 7;

FIG. 9 is a timing chart showing the operation of the image display device of FIG. 8;

FIG. 10 is a timing chart showing the operation of the image display device of FIG. 8 as in FIG. 9;

FIG. 11 is a circuit diagram of a digital / analog converter used in the image display device of the present invention.

FIG. 12 is an operational amplifier used in the digital / analog converter of FIG. 11;

FIG. 13 is a configuration diagram of an image display device according to a third embodiment of the present invention having the pixels of FIG. 4 and the digital / analog converter of FIG. 11;

14 is a timing chart showing the operation of the image display device of FIG.

FIG. 15 is a timing chart showing the operation of the image display device of FIG. 13 as in FIG. 14;

FIG. 16 is a timing chart showing an operation of the image display device according to the fourth embodiment of the present invention having the same configuration as the image display device of FIG.

[Explanation of symbols]

1: shift register 2: latch 3: digital / analog converter 4: liquid crystal display D (1) to D (N): column electrode indicating a connection terminal between (3) and (4) W: of (2) Write enable signal V _R : (3) reference voltage input V _C : (4) common electrode terminal / potential V _DD , V _SS : (1) and (2) power supply terminal / potential V _DD , V _CC : ( 3) Power supply terminal and potential

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[Procedure amendment]

[Submission date] April 7, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: Method for driving an image display device

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction contents]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal image sandwiched between a substrate on which a column electrode is formed and a counter substrate on which a plurality of pixel electrodes selected by a common electrode or a row electrode orthogonal to the column electrode are formed. The present invention relates to a method for driving a display device.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is directed to a method of driving an image display device having a display using an active element and a liquid crystal. The group and the column electrode group are arranged in a matrix so as to be orthogonal to each other, the active elements are provided corresponding to the matrix of the row electrode and the column electrode, and the pixel electrode and the common electrode facing the pixel electrode are provided. Liquid crystal is sandwiched between the substrates,
A row-side shift register that sends a signal for selecting a pixel by turning on a pixel connected to the same row electrode is provided,
The digital / analog converter connected to the column electrode is provided with a decoder, a voltage dividing circuit, and a switch. The voltage dividing circuit divides a reference voltage by a resistor to generate a plurality of outputs matched to the optical characteristics of the liquid crystal. A potential is provided, and a gate signal for sequentially selecting each row is output from the row-side shift register,
The output potential is supplied to a column electrode through a switch, and digital image data composed of n bits per column is transferred in a column-side shift register. For a certain row, digital image data of all columns is passed through a latch. Almost simultaneously, it is supplied to a digital / analog converter, and is converted into a selection output for each column by a decoder. A switch is controlled by the selection output, and one of the output potentials is selected as analog image data and is applied to each column electrode. And stored in the pixel electrodes of all the columns in a certain row.
And the potential of the common electrode, the polarity of the voltage between the analog image data is performed is inverted AC driving of the liquid crystal at a predetermined period, the driving of the image display apparatus, wherein a display of 2 ⁿ gradations can be performed Provide a way .

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

FIG. 1 is a block diagram of an image display device used in the present invention. (1) is a shift register, (2) is a latch, (3) is a digital / analog converter, and (4) is a liquid crystal display. Is shown.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

FIG. 1 shows a digital / digital conversion of 3-bit data.
Since the analog conversion is performed, the image display device has eight gradations.
^A method for driving an image display device with ⁿ gradations is obtained.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The driving method of an image display device according to the present invention as described above is applied to an image display device in which liquid crystal is driven by using a plurality of transistors or active elements such as diodes formed on the same substrate as switches. Is done.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0046

[Correction method] Change

[Correction contents]

[0046] Figure 13 is a block diagram of an image display device having a digital / analog converter shown in FIG. 11 for each column of the liquid crystal display element comprising a pixel shown in FIG. 4, first the present invention
FIG. 14 is a timing chart of the third embodiment . (56), (57), (59), and (60) correspond to (14), (15), (19), and (20) in FIG. 5, respectively.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction contents]

In order to perform color display by the method of driving the image display device having the digital / analog converter according to the first to fourth embodiments described above, a transparent common electrode or a column electrode is formed. R (red), G
The three primary color filters (green) and B (blue) are arranged corresponding to the pixel electrodes on the counter substrate, and are sequentially synchronized with the clock CL according to the arrangement of the color filters corresponding to the pixel electrodes selected by the row electrodes. The color data D ₀ , D ₁ ,
Transfer the D ₂ to the shift register is achieved by placing the pixel electrode of the selected row output latched after digital / analog conversion.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0061

[Correction method] Change

[Correction contents]

[0061]

As described above, the driving of the image display device of the present invention is described.
The method employs a configuration in which a digital / analog converter provided with a voltage dividing circuit, a decoder, and a switch common to each column electrode of the liquid crystal display, thereby changing the voltage applied to the liquid crystal for each pixel. By displaying data in a pixel electrode of a liquid crystal display in a line-sequential operation, image data can be latched and converted to digital / analog and input to the pixel electrode in a frame cycle / Since this is the number of rows of pixels and the data setting time has a margin, the number of rows and columns of pixels can be increased to realize a large display capacity and a large area display.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG. 1 is a configuration diagram of an image display device used in the present invention.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/66 102 H04N 5/66 102B

Claims (4)

[Claims] 1. An image display device comprising an active element and a display using liquid crystal, wherein a row electrode group and a column electrode group are arranged in a matrix so as to be orthogonal to each other, and the active element is arranged in a row electrode and a column. A pixel electrode and a common electrode facing the pixel electrode are provided corresponding to the electrode matrix, a liquid crystal is sandwiched between the opposed substrates, and a pixel connected to the same row electrode is turned on to select a pixel. A row-side shift register for transmitting a signal is provided, a digital / analog converter connected to a column electrode is provided with a decoder, a voltage dividing circuit, and a switch, and the voltage dividing circuit divides a reference voltage by a resistor. A plurality of output potentials corresponding to the optical characteristics of the liquid crystal are provided, a gate signal for sequentially selecting each row is output from a row-side shift register, and the output potential is supplied to a column electrode through a switch, Digital image data composed of n bits per column is transferred through a shift register on the column side, and for a certain row, digital image data of all columns is supplied to a digital / analog converter almost simultaneously through a latch. The output is converted into a selection output for each column by a decoder, a switch is controlled by the selection output, and one of the output potentials is selected as analog image data and sent to each column electrode. In addition, the potential of the common electrode and the polarity of the voltage between the analog image data are inverted at a predetermined cycle, and the AC driving of the liquid crystal is performed, and 2 ⁿ gray scale display is performed. Image display device. 2. The image display device according to claim 1, wherein the predetermined period is one frame or two frames. 3. The image display device according to claim 1, wherein a color filter is further provided corresponding to each pixel electrode to perform color display. 4. A digital color filter in which three primary color filters of R (red), G (green), and B (blue) are arranged, and color data corresponding to the arrangement of the color filters corresponding to the pixel electrodes selected by the row electrodes. 4. The image display device according to claim 1, wherein the image data is transferred to a shift register.