JPH10269271A - Logical synthesis automatic converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time for designing by correcting a circuit with the change of the description of HDL(hardware describing language) without performing logical synthesis again. SOLUTION: When a user selects the retaining of a changed description file, the original file of a storage device 2 is overwritten to the original file of a storage device 1 and the changed file is overwritten to the original file of the storage device. A changed part extracting device 7 compares a file before changing and the changed file with each other to extract a changed part. An automatic changing part 8 selects an element pertinent to the changed part by referring to the changed part extracted by the device 7 and converts only the pertinent part of data stored in a storage device 3 to the selected element to output. An error detector 9 judges whether data converted by the converter 8 is proper based on whether it is pertinent to each check item and when it is pertinent to one of the check items, outputs an error signal and a message.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis automatic conversion for automatically converting a previous logic synthesis result when a file described in HDL is changed in a top-down design using a hardware description language (HDL). Related to the device.

[0002]

2. Description of the Related Art In recent years, HDL top-down design has become widespread, and various logic synthesis tools have been proposed. As a result, various types of gate circuits, from small to large, can be easily generated without manual intervention. In addition, when a designer gives restrictions such as area and speed, it is possible to regenerate a circuit that matches the specifications of the developed product. For example, Japanese Patent Laying-Open No. 6-96157 discloses a configuration in which the efficiency of logic synthesis is improved by decomposing each circuit block so that optimum synthesis can be performed in a short time. Also, Japanese Patent Application Laid-Open No. Hei 8-30650 discloses a method of generating a low power consumption circuit by logic synthesis, and Japanese Patent Application Laid-Open No. Hei 6-314314 discloses that an intended circuit can be easily designed even for inexperienced persons. A possible HDL description device is disclosed.

[0003]

However, in the conventional HDL description device, although there are effective means for logic synthesis, the H-description is performed at the time of circuit change or at the time of circuit change.
There was no method to consider when changing the description of the DL. In the conventional HDL description device,
When the description of the HDL is changed, in the process of s12 in the process shown in FIG. 9, it takes time and effort to re-synthesize the changed portion based on the functional diagram showing the circuit block before the logic synthesis. In addition, the design time becomes longer depending on the circuit scale. Further, even when the changed portion is small, the logic synthesis of the entire circuit must be executed again.

[0004] It is an object of the present invention to provide a logic synthesis automatic conversion device that can perform circuit correction accompanying a change in the description of HDL without re-synthesizing the logic again and can reduce the design time.

[0005]

According to a first aspect of the present invention, there is provided a modified part extracting means for comparing a HDL description file before a change with an HDL description file after a change to extract a changed part; Automatically replaces the changed element extracted by the partial extraction means with a selected element from a plurality of pre-registered element groups and replaces the changed element in the logic synthesis result based on the description file before the change. And conversion means.

According to the first aspect of the present invention, a changed element extracted from a comparison between a description file before a change and a description file after a change is selected, and is selected based on the description file before the change. By replacing the element before the change in the logic synthesis result with the selected element, the result of the logic synthesis based on the description file after the change can be obtained easily and in a short time.

According to a second aspect of the present invention, a first storage means for storing a description file of a hardware description language before a change, and a second storage means for storing a description file of a hardware description language after a change. And a third storage unit for storing a result of logic synthesis based on the description file before the change.

[0008] In the second aspect of the present invention, the first
The changed part is easily extracted by comparing the storage content of the storage means with the storage content of the second storage means, and the changed element of the changed part is stored in the storage content of the third storage means. By replacing with the element, the changed logic synthesis result can be easily obtained.

According to a third aspect of the present invention, when the description file in the hardware description language is changed, description saving selection means for receiving selection input as to whether or not to save the changed description file is included. Features.

According to the third aspect of the invention, the user can select whether or not the result of the logic synthesis based on the changed description file is necessary.

[0011] According to a fourth aspect of the present invention, a logical validity is determined based on a check item set in advance with respect to a result of logic synthesis after replacing elements by the automatic reply means. Is output.

According to the fourth aspect of the present invention, the logical validity of the logic synthesis result based on the changed description file can be easily determined based on the presence or absence of the error signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing a configuration of a logic synthesis automatic conversion apparatus according to an embodiment of the present invention. The automatic logic synthesis conversion device 10 includes a storage device 1 for storing a description file before change, a storage device 2 for storing a description file after change, a storage device 3 for storing a result of logic synthesis based on the description file before change, and In addition to a storage device 4 in which data automatically converted by a changed portion extracted from the storage device 3 is stored, a description storage / selection device 6, a changed portion extraction device 7, an automatic conversion device 8, and an error detection device 9 are provided. ing.

The description storage / selection device 6 receives a user's selection input as to whether or not to store the changed description file. The changed part extracting device 7 compares a description file stored in the storage device 1 with a description file stored in the storage device 2 to extract a changed part. In the automatic conversion device 8, an element group including a plurality of elements such as a combinational circuit such as an AND gate and an OR gate and a cell of a sequential circuit such as a flip-flop and a latch is registered in advance.
The error detection device 9 detects the presence or absence of an error in the changed data according to the check items.

FIG. 2 is a flowchart showing a processing procedure in the above-described automatic logic synthesis conversion apparatus. When the HDL description of the storage device 2 is changed, the logic synthesis automatic conversion device 10 determines whether or not to save the changed description file as a description file for obtaining an intended circuit via the description storage selection device 6. (S1, s2). If the user selects to save the modified description file, the original file in the storage device 2 is overwritten on the original file in the storage device 1, and the newly changed file is overwritten on the original file in the storage device 2. . Then, the changed part extraction device 7 compares the file before the change and the file after the change to extract the changed part (s3).

Next, conversion processing is performed by the automatic conversion device 8 (s4). That is, as shown in FIG. 3, the automatic conversion device 8 refers to the changed portion extracted by the changed portion extracting device 7 and selects an element corresponding to the changed portion among the registered cells, signals, and terminal names. . Then, only the relevant part of the data stored in the storage device 3 is converted into the selected element and output to the error detection device 9.

Thereafter, the validity of the converted circuit data is determined by the error detection device 9 (s5). That is, FIG.
As shown in (1), the error detection device 9 does not generate a hazard generated in the selector or the like, does not exceed the clock frequency of the delay time from the input terminal to the output terminal, or has an unconnected pin. Check items for determining the logical validity of the data such as are set in advance. The error detection device 9 determines whether or not the data converted by the automatic conversion device 8 is appropriate based on whether or not the data corresponds to each check item.

The error detection device 9 outputs an error signal and a message when the data converted by the automatic conversion device 8 corresponds to any of the check items. If the data converted by the automatic conversion device 8 does not correspond to all of the check items, the error detection device 9 stores the data in the storage device 4 as a result of logic synthesis of the changed description file. If the data converted by the automatic conversion device 8 corresponds to any of the check items, the description is changed again based on the error content. less than,
The actual conversion process of the HDL description file by the logic synthesis automatic conversion device 10 will be described using Verilog-HDL as an example. Assuming that the Verilog-HDL description shown in FIG. 5 is changed to the Verilog-HDL description shown in FIG. 6, the description file in FIG.
Then, the description file of FIG. Before the description is changed, the description file shown in FIG. 5 is subjected to logic synthesis in advance, and the result of the logic synthesis (see FIG. 7) for the description file in FIG. 5 is stored in the storage device 3.

Comparing the description of FIG. 5 with the description of FIG. 6, the logical product && of the formula of y is changed to II. Therefore, the changed part extraction device 7 extracts this part as a changed part of the description. Then, the automatic conversion device 8 selects a cell corresponding to the logical sum II, which is a changed portion, from the cells registered in advance, in this case, an OR gate. Further, the automatic conversion device 8 replaces the selected OR gate with an AND gate of a changed portion in the data stored in the storage device 3, and generates converted data shown in FIG. The converted data is input to the error detection device 9, and the presence or absence of an error is checked according to the check items. In this case, since there is no error, the data shown in FIG. 8 is stored in the storage device 4 and a series of processing is completed.

With the above processing, according to the automatic logic synthesis conversion apparatus 10, when a part of cells are changed in the description file, the automatic conversion apparatus 8 changes the corresponding portion of the logic synthesis result before the change. The conversion can be performed quickly without referring to the other parts. Even when the signal name is changed, the conversion can be performed quickly only by replacing the signals at the corresponding location, and the circuit intended by the designer can be obtained in a short time without logically synthesizing the whole again.

[0021]

According to the first aspect of the present invention, the changed element extracted from the comparison between the description file before the change and the description file after the change is selected, and the description before the change is selected. By replacing the element before the change in the logic synthesis result based on the file with the selected element, the logic synthesis result based on the changed description file can be obtained easily and in a short time, and the circuit design time intended by the user can be obtained. Can be shortened.

According to the second aspect of the present invention, a changed portion can be easily extracted by comparing the storage contents of the first storage device and the storage contents of the second storage device, and the change of the changed portion can be easily performed. By replacing the latter element with the element of the changed part in the storage content of the third storage means, the changed logic synthesis result can be easily obtained.

According to the third aspect of the present invention, the user can select whether or not a logic synthesis result is necessary based on the changed description file, and can easily design a circuit intended by the user. it can.

According to the fourth aspect of the present invention, the logical validity of the logic synthesis result based on the changed description file can be easily determined based on the presence or absence of the error signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logic synthesis automatic conversion device as an example of an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing procedure of the automatic logic synthesis conversion device.

FIG. 3 is a diagram showing functions of an automatic conversion device constituting the automatic logic synthesis conversion device.

FIG. 4 is a diagram showing functions of an error detection device constituting the logic synthesis automatic conversion device.

FIG. 5 is a diagram showing a description file before change in an example of conversion processing of the automatic logic synthesis conversion apparatus.

FIG. 6 is a diagram showing a modified description file in an example of the conversion process.

FIG. 7 is a diagram showing a result of logic synthesis of the description file before the change.

FIG. 8 is a diagram showing a logical-picture composition result of the description file after the change.

FIG. 9 is a flowchart showing a processing procedure in a conventional automatic conversion process.

[Explanation of symbols]

 1-4 storage device 6-description change selection device 7-change part extraction device 8-automatic conversion device 9-error detection device 10-logic synthesis automatic conversion device

Claims (4)

[Claims] A modified part extracting means for comparing a description file of a hardware description language before a change with a description file of a hardware description language after a change to extract a changed part; Automatic conversion means for selecting an element after change for the changed part from a plurality of pre-registered element groups and replacing the element before change for the changed part in the result of logic synthesis based on the description file before change with the selected element; , A logic synthesis automatic conversion device. 2. A first storage means for storing a description file of a hardware description language before change, a second storage means for storing a description file of a hardware description language after change, and a description file before change. 3. The automatic logic synthesis conversion device according to claim 1, further comprising: a third storage unit that stores a result of logic synthesis based on the logic. 3. The logic according to claim 1 or 2, further comprising a description storage selecting means for receiving a selection input as to whether to save the changed description file when the description file in the hardware description language is changed. Synthetic automatic conversion device. 4. An error detecting means for judging logical validity based on a preset check item for a result of logic synthesis after replacing elements by said automatic reply means, and outputting an error signal when invalid. The automatic logic synthesis conversion device according to claim 1, further comprising: