JPH06195414A - Logical design supporting system - Google Patents

Abstract

PURPOSE:To execute more optimized replacement by considering replacement with a basic element provided with the antiphase input/output terminal in the case of improving a delay time by the replacement of the basic element. CONSTITUTION:Concerning the basic element of target technology inputted from a library input part 2, a library classifying part 3 prepares the group of the basic elements of the same input number, the same logic and different power and by setting the group of basic elements to be an object, the set of the basic elements of the same input number and antiphase logics is previously stored in a temporary storage part 5. At the time of improving the delay time after various processings to a design object circuit description by a processing part 4, this system executes local optimization by the replacement of the basic element through the use of information of the group of basic elements and the set stored in the temporary storage part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic design support system.

[0002]

2. Description of the Related Art Generally, when designing an electronic computer or a large-scale integrated circuit, a library for managing information such as functions and physical characteristics of basic elements such as AND elements, inverter elements and flip-flop elements is prepared in advance. Aside
Logic design is performed by connecting these basic elements to each other.

A logic synthesizer is one of typical logic design support systems. This is because the hardware description of the design target, which is described by the designer using a function or behavioral description independent of the target technology, is input, and optimization or technology that does not depend on the technology is specified under certain constraints. After performing technology mapping including dependent optimization, a logic description or a circuit diagram is generated.

Further, in the circuit diagram input device which is one of the logic design support systems, the shapes of the basic elements of the library on the circuit diagram are prepared in advance, and the designer stores the basic elements in the main storage unit of the electronic computer. Place it on the schematic that is expanded above,
The logic is designed by wiring the terminals of the device.

Conventionally, in this type of logic design support system, in order to improve the delay time of a circuit once designed,
There has been a method of replacing a basic element in a circuit with a basic element having the same number of inputs and the same logic but different capacitance, resistance and internal delay time.

For example, in a logic synthesizer, after technology mapping is performed, as a method of optimizing the delay time, when a plurality of basic elements having the same number of inputs and the same logic existing in the library are replaced. Local delay was calculated by calculating the delay time and selecting the optimum basic element.

In the circuit diagram input device, timing analysis is performed on the circuit diagram for which input has been completed with a desired external terminal delay constraint to check whether there is a constraint violation. Some of the basic elements on the path that violate the constraint have a local optimization function as in the logic synthesizer.

[0008]

In order to improve the delay time, the logic design support system according to the above prior art selects the optimum one from the basic elements having the same number of inputs and the same logic as the basic elements in the circuit. Since only replacement is considered, there is no choice but to select the number of basic elements of the same kind.

For example, as shown in FIG. 3, AND circuits having different powers are provided in a certain library with reference numerals 311 and 31.
Two kinds of NAND elements denoted by reference numerals 321 and 3
It is assumed that there are three types indicated by 22 and 323. In this case,
If an AND element in a target circuit for performing a certain delay improvement is replaced, conventionally, reference numerals 411, 412, 413 are used in FIG.
There is a problem in that only the three types of replacement possibilities shown in (3) can be considered.

Therefore, according to the present invention, when the delay time is improved by the replacement of the basic element, the replacement with the basic element having the input / output terminals of the opposite phase is taken into consideration, and the more optimal replacement can be performed. To provide a system.

[0011]

In order to achieve the above object, the present invention has any one of the following configurations. (1). An input unit for inputting a logic design target circuit, a library unit for inputting library information such as basic elements of the target technology, a library classification unit for classifying the input library for each logic of the same and opposite phase, and a process for performing logic design A temporary storage unit for holding a final result and library information in the middle of design, an output unit for outputting the circuit of the design result and the classified library information (claim 1). (2). Input section to input the logic design target circuit, library input section to input the library information such as basic elements of the target technology, library classification section to classify the basic elements from the input library, and delay calculation of the input logic circuit , A processing unit that replaces basic elements, a temporary storage unit that holds the final result during the design and the final result, an output unit that outputs a circuit description of the design result, a circuit diagram of the intermediate result of the design, a critical path, etc. It is decided to have a display section for displaying (Claim 2).

[0012]

When the basic elements in the circuit are replaced with basic elements having the same logic but different powers to improve the delay time, the basic elements in the circuit should be replaced not only with the same logical elements but with completely opposite logical elements. Consider.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION In contrast to the above-mentioned conventional logic design support system, in the present invention, when a basic element having the same number of inputs and the same logic is replaced in order to improve the delay time, a basic element having an input and an output terminal of the opposite phase is replaced. Considering the possibility of replacement with, the inverter etc. connected to the basic element is deleted and inserted in order to match the logic before and after. 1. First Embodiment The present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram showing a logic synthesis device which is an embodiment of a logical design support system according to the present invention.

In FIG. 1, the logic synthesizing apparatus has an input section 1 for inputting a circuit to be logically designed, a library input section for inputting library information such as a basic element of a target technology, and input library basic elements of the same and opposite phases. A library classifying unit 3 for classifying by logic, a processing unit 4 for performing logic design, a temporary storage unit 5 for holding a final result and a library in the middle of design, a circuit of design results, and an output unit 6 for outputting a classified library. To be done.

Next, the operation of the logic synthesizer will be described with reference to FIGS. A library in which information such as functions of basic elements of a target technology such as CMOS used for logic synthesis, input / output terminal capacitance, resistance, internal delay time, etc. is input from the library input unit 2 and stored in the temporary storage unit 5. .

In the library classifying section 3, the basic elements of the library stored in the temporary storage section 5 are classified by the logic classifying means 21 into basic element groups having the same number of inputs and different logic but different powers.

The results of this classification are as illustrated in FIG. 3, and the 2-input AND element group 31 has a small power 31.
There are three types: 1, medium power 312, and large power 313.
Further, the 2-input NAND element group 32 has three types of small power 321, medium power 322, and large power 323.

Next, the reverse phase classification means 22 in FIG. 2 inputs all the basic element groups in the library,
The output terminals with opposite phases and the same number of inputs and the same logic are collected as a set.

In the example of FIG. 3, the 2-input AND element group 31 and the 2-input NAND element group 32 can be put together as one set. Fig. 2 shows the logical element group thus assembled into a set.
It is registered in the temporary storage unit 5 (see FIG. 1) by the reverse phase registration means 23 in.

In FIG. 2, when the end judging means 24 judges that there is a basic element group which is not yet registered in the set in the library, it returns to the anti-phase classification means 22 and the judgment is completed for all the basic element groups. This completes the library classification process.

Next, the specification description of the logic synthesis target circuit is input from the input unit 1, converted into an internal data structure, and stored in the temporary storage unit 5.

The processing unit 4 in FIG. 1 performs the technology independent optimization means 51 in FIG. 5 to optimize the logic synthesis target circuit description stored in the temporary storage unit 5 independently of the target technology.

The technology mapping unit 52 refers to the basic elements of the library stored in the temporary storage unit 5 for the circuit which has been optimized independently of the technology, and satisfies the constraint conditions such as the area delay time. , Map the basic elements.

The local optimizing means 53 replaces the basic element group stored in the temporary storage unit 5 and the optimum basic element when the basic element in the circuit for delay improvement is replaced with reference to the set. To do.

At this time, when a basic element having an input terminal and an output terminal of opposite phase is selected, a process of inserting or deleting an inverter before or after the basic element is performed. For example, the circuit 41 shown in FIG.
In the case of the configuration of 2, the circuits 411 and 413 are the same in the AND element, and the circuits 421, 422, and 423 are 5 in the opposite phase.
There is a possibility of street replacement.

If the circuit 423 is found to be optimal by performing the delay calculation, the AND element 312 and the NAND element 323 are replaced, the previous inverter that is fan-out on the left side is deleted, and the fan-out on the right side is performed. Insert the inverter at the end.

When all logic synthesis processing is completed for the circuit to be synthesized, the circuit description stored in the temporary storage unit 5 is output from the output unit 6.

The library including the basic element group and the set information is output from the output unit 6 to a file or the like, and when the same technology library is used in the next logic synthesis,
If the library having already added the basic element group and the set information is input from the library input section 2, the library classification processing in the library classification section 3 becomes unnecessary.

Further, for example, when optimizing the circuit 411 of FIG. 4, a total of six types are considered in consideration of the possibility of replacement using the NAND elements 321, 322, 323 like the circuits 421, 422, 423. The most suitable candidate can be selected from among these.

In this case, since one inverter is removed for the path fanned out to the left of the AND element, the delay improvement of this path has an advantage over simple replacement of the basic element. 2. Second Embodiment FIG. 6 shows the overall configuration of a circuit diagram input device according to a second embodiment of the present invention. In FIG. 6, the circuit diagram input device includes an input unit 61 for inputting a logic design target circuit via an input device such as a keyboard and a mouse, a library input unit 62 for inputting library information such as a basic element of a target technology, and an input unit. A library classification unit 63 that classifies basic elements from a library, a processing unit 64 that performs delay calculation of input logic circuits, replacement of basic elements, etc.
It comprises a temporary storage unit 65 for holding the final result, an output unit 66 for outputting the circuit description of the design result, and a display unit 67 for displaying the circuit diagram of the intermediate result of the design, the critical path and the like.

Next, the operation of the circuit diagram input device will be described with reference to the drawings. The library input section 6 stores a library in which information such as functions of the basic elements of the target technology used for logic design, inputs, and output terminals is described.
It is input from 2, and stored in the temporary storage unit 65.

In the library classification unit 63, the temporary storage unit 6
For the library stored in 5, the basic elements in the library are classified by the same method as described in the first embodiment.

Next, in the input unit 61, a basic element is selected and arranged in the logic design target circuit by using an input device such as a keyboard and a mouse, the elements are wired, the internal data structure is converted, and the temporary storage unit is provided. Store in 65. This is performed while displaying the intermediate result of the input on the display unit 67.

When the logic circuit is completed, the delay time is calculated by the processing unit 64. If the desired constraint condition is not satisfied, the same basic procedure as the local optimizing means 53 of the first embodiment is used. The element is replaced to improve the delay time. When the satisfactory circuit is completed, the output unit 66
Output a circuit drawing. 3. As described above, in each embodiment, not only the replacement of the basic element having the same number of inputs and the same logic for improving the delay time but also the possibility of the replacement with the basic element having the input / output terminal of the opposite phase is considered. Therefore, the basic element to be replaced can be selected from a larger number of candidates, and the possibility of further optimization is increased.

Further, when the replacement is performed with the basic element of the opposite phase, the inverters before and after the replacement can be deleted. Therefore, in addition to the improvement of the delay time by the replacement, there is an advantage that the delay time can be improved by deleting the inverter. .

Here, the basic elements once classified are held together with the library, and from the next time, if the library of “classified” is used, the library classification process can be performed once for each technology live and library.

[0037]

According to the present invention, when the delay time is improved by replacing the basic element, the replacement with the basic element having the input / output terminals of the opposite phase is taken into consideration. Therefore, more optimal replacement can be performed. You can

[Brief description of drawings]

FIG. 1 is a diagram illustrating an overall configuration of a logic design support system according to a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart illustrating details of a library classification unit according to the first embodiment.

FIG. 3 is a diagram illustrating an example of basic elements classified by the same number of inputs and the same logic.

FIG. 4 is a diagram illustrating and exemplifying a candidate for replacement with a basic element having an antiphase input and an output terminal.

FIG. 5 is a flowchart illustrating the operation of logic synthesis in the processing unit according to the first embodiment.

FIG. 6 is a diagram illustrating an overall configuration of a logic design support system according to a second exemplary embodiment of the present invention.

[Explanation of symbols]

 1 Input Section 2 Library Input Section 3 Library Classification Section 4 Processing Section 5 Temporary Storage Section 6 Output Section 61 Input Section 62 Library Input Section 63 Library Classification Section 64 Processing Section 65 Temporary Storage Section 66 Output Section 67 Display Section

Claims (2)

[Claims] 1. An input unit for inputting a logic design target circuit,
A library section for inputting library information such as basic elements of the target technology, a library classifying section for classifying the input library for each of the same and opposite phase logics, a processing section for performing logic design, a design process, a final result and A logical design support system comprising: a temporary storage section for holding library information; and an output section for outputting a circuit as a design result and classified library information. 2. An input section for inputting a logic design target circuit,
A library input section that inputs library information such as basic elements of the target technology, a library classification section that classifies basic elements from the input library, and a processing section that performs delay calculation of input logic circuits, replacement of basic elements, etc. , A temporary storage unit for holding the final result during the design and an output unit for outputting a circuit description of the design result, and a display unit for displaying a circuit diagram of the result of the design, a critical path, etc. A logical design support system.