JPH08184647A - Design of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To prepare a test pattern for achieving a target failure detection rate in a short time automatically by substituting an FF circuit with scanning function for an FF circuit present in a feedback loop. CONSTITUTION: The output section 23 of an FF circuit 21 searches a route of a signal line 27-the input section of a logic circuit 24-an output section 26-a signal line 28-the input section 22 of the circuit 21 and makes a decision that the circuit 21 is present in the feedback loop. FF circuits 29, 30 function similarly. FF circuits 36, 37 with scanning function are substituted for the circuits 21, 30. An external input section 44 is then connected with an input section 40 for scanning the circuit 36 and the output section of the circuit 36 is connected with the input section 39 of the circuit 37 through a scan chain 41. Furthermore, input sections 42, 43 for switching are connected with an external output section 45. Since a test pattern applied to the input section 44 can be scanned directly in the circuits 36, 37, a signal being fed back through a feedback loop can be determined easily and a test can be carried out easily with high failure detection rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit designing method employing a partial scan designing method, which is one of the methods for automatically creating a test pattern for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, a scan design method has been attracting attention as a method for automatically creating a test pattern in accordance with the increase in the scale and synchronous circuit of a semiconductor integrated circuit. The scan design method is to replace the first flip-flop circuit, which becomes a bottleneck when the test pattern is automatically created, with the second flip-flop circuit in the connection information,
This is a method that facilitates test pattern creation. Specifically, in the connection information, the second flip-flop circuit is regarded as a continuous shift register group under a certain condition to facilitate test pattern creation. here,
The second flip-flop circuit is a flip-flop circuit having a data input unit (hereinafter referred to as a scan input unit) and a switching input unit capable of switching a data input unit to be used (hereinafter, a flip-flop with a scan function). Circuit)). Scan design methods are roughly classified into a full scan design method and a partial scan design method.
The full scan design method is to replace all flip-flop circuits with flip-flop circuits with a scan function when executing an automatic test pattern generation tool (hereinafter referred to as ATPG) used to automatically create a test pattern. Although it is a method of automatically creating a test pattern with a high fault detection rate, it has a drawback that the circuit scale is considerably increased because all flip-flop circuits are replaced with flip-flop circuits with a scan function. On the other hand, the partial scan design method is "IEEE D
esign Test Comput., vol.5, pp.8-15, Apr. 1988, "De
signingcircuits with partial scan ", VDAgrawal,
As shown in “KTCheng, DDJohnson, and T.Lin”, a method of replacing only an arbitrary flip-flop circuit with a flip-flop circuit with a scan function when executing ATPG can suppress the increase in the circuit scale to a minimum. It is something to try. Hereinafter, a method for designing a semiconductor integrated circuit adopting the conventional partial scan design method will be described. FIG. 4 is a basic flow chart of a semiconductor integrated circuit designing method adopting a conventional partial scan designing method. Step 41 is a step of executing ATPG for connection information of the semiconductor integrated circuit, and step 42 is a step 41.
A step of selecting a flip-flop circuit to be replaced with the flip-flop circuit with the scan function based on the execution result of the step, step 43 is a step of replacing the flip-flop circuit selected in step 42 in the connection information with the flip-flop circuit with the scan function, Reference numeral 44 connects the output section of one flip-flop circuit replaced in step 43 to the data input section of another replaced flip-flop circuit, and is successively connected from the external input section to the external output section. A step of forming a set of flip-flop circuits with a scan function, step 45 is a step of connecting the switching input section of the flip-flop circuits with a scan function connected in step 44 to an external input section, and step 46 is a switching input in step 45. Scat with connecting parts Is again performing a ATPG the semiconductor integrated circuit having a built-in function flip-flop circuit.

The operation of a semiconductor integrated circuit designing method adopting the partial scan designing method configured as described above will be described below. First, in step 41, A
When the TPG is executed, an attempt is made to create a test pattern capable of detecting a failure in all signal lines inside and outside the connection information. That is, assuming that there is a failure in the circuit to which the output section is connected to the signal line, all the circuits connected to the external input section or the external output section centered on the circuit are sequentially described above. An attempt is made to create a test pattern in which a failure state can be found (hereinafter referred to as controllability) and the state can be observed from an external output unit (hereinafter referred to as observability). At this time, if a test pattern having controllability and observability for a certain signal line cannot be created or if it is difficult to create a test pattern, regarding the signal line name and the signal line, The signal line name that becomes the bottleneck in the test pattern creation with controllability and observability of is output. Next, in step 42, an arbitrary flip-flop circuit is selected based on the signal line name output by the execution of ATPG in step 41. At this time, if all the flip-flop circuits are selected, the circuit scale increases, so it is necessary to select the minimum necessary one. Next, in step 43, the flip-flop circuit selected in the determination step of step 42 is replaced with a flip-flop circuit with a scan function. Next, in step 44, for the flip-flop circuit with the scan function replaced in step 43, one output section and another one data input section are sequentially and continuously connected from at least one set of external input section to external output section. The wiring is connected by a wiring (hereinafter referred to as a scan chain) so as to form a set of the flip-flop circuits with the scan function. Next, at step 45, the switching input section of the flip-flop circuit with scan function connected by the scan chain at step 44 is connected to the external input section. Finally, in step 45, the ATP is again applied to the semiconductor integrated circuit including the flip-flop circuit with the scan function, to which the switching input section is connected.
G is executed to determine whether or not the automatically created test pattern has achieved the target fault coverage. At this time, when the target fault coverage is not achieved, the steps 42 to 46 are repeated based on the result of ATPG until the target fault coverage is achieved.

[0004]

However, in the above-described conventional method, it is necessary to determine which flip-flop circuit should be replaced with the scan-function flip-flop circuit from the signal line name output as a result of ATPG execution. , The criteria were not clear. Therefore, in this determination, if the importance is placed on the reduction of the circuit scale at the time of production, the number of flip-flop circuits to be replaced tends to be reduced, and it is an object unless ATPG execution and this determination are repeated a plurality of times. There is a problem in that the failure detection rate cannot be achieved and a huge amount of time is spent in creating a test pattern. On the other hand, in this determination, if importance is attached to shortening the processing time, it is determined that the unnecessary flip-flop circuit should be replaced with the flip-flop circuit with the scan function, resulting in an unnecessary increase in circuit scale. was there. That is, in the conventional method, it is difficult to automatically create a test pattern while balancing the problems of the circuit scale and the processing time. The present invention solves the above-mentioned conventional problems, and a semiconductor integrated circuit designing method adopting a partial scan designing method in which a flip-flop circuit to be replaced with a minimum necessary flip-flop circuit with a scan function can be easily selected. The purpose is to provide.

[0005]

In order to achieve this object, a semiconductor integrated circuit designing method according to the present invention described in claim 1 uses a first flip-flop circuit existing in a feedback loop as a data The second flip-flop circuit is formed by replacing the data input unit and the data input unit to be used with a flip-flop circuit having a switchable input unit.

According to a second aspect of the present invention, there is provided a method of designing a semiconductor integrated circuit, comprising the steps of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit, and the first flip-flop circuit performing feedback / feedback. It is possible to switch between the data input section and the data input section for the step of judging whether it exists in the loop and the first flip-flop circuit judged to exist in the feedback loop in the step of judging The second flip-flop circuit is formed by replacing the flip-flop circuit with a switching input section.

According to a third aspect of the present invention, there is provided a method of designing a semiconductor integrated circuit, comprising the steps of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit, and the first flip-flop circuit performing feedback / feedback. The data input section and the data input section to be used can be switched to the step of judging whether or not it exists in the loop, and the first flip-flop circuit judged to exist in the feedback loop in the judging step. A second flip-flop circuit is formed by adding a switching input section.

According to a fourth aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit, comprising the steps of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit, and the first flip-flop circuit performing the feedback. Switching between the data input section and the data input section for the step of determining whether or not it exists in the loop, and the first flip-flop circuit determined to exist in the feedback loop in the step of determining A step of forming a second flip-flop circuit by replacing the flip-flop circuit with a possible switching input section, and when there are a plurality of second flip-flop circuits, at least one set of external input section and first external input section The step of connecting the data input sections of the two flip-flop circuits, and the output section of one second flip-flop circuit and the other A step of forming a set of second flip-flop circuits successively connected to the external input section by connecting the data input sections of the two second flip-flop circuits; Connecting the output part of the second flip-flop circuit at the final stage and the external output part in the set of flip-flop circuits of the above, and connecting the switching input parts of all the second flip-flop circuits to the external input part. The process consists of

According to a fifth aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit, comprising the steps of detecting all the first flip-flop circuits incorporated in the semiconductor integrated circuit, and the first flip-flop circuit performing the feedback. Switching between the data input section and the data input section for the step of determining whether or not it exists in the loop, and the first flip-flop circuit determined to exist in the feedback loop in the step of determining A step of forming a second flip-flop circuit by adding a possible switching input section; and, when there are a plurality of second flip-flop circuits, at least one set of external input section and the second flip-flop. Connecting the data input of the circuit, the output of one of the second flip-flop circuits and the other one of the second flip-flops. A step of forming a set of second flip-flop circuits sequentially and continuously connected to the external input section by connecting the data input section of the flop circuit; It comprises a step of connecting the output section of the second flip-flop circuit at the final stage and the external output section in the set, and a step of connecting the switching input sections of all the second flip-flop circuits to the external input section. .

[0010]

With this configuration, in the semiconductor integrated circuit designing method of the present invention as defined in claim 1, only the flip-flop circuit existing in the feedback loop can be replaced with the flip-flop circuit with the scan function. As a result, it is possible to minimize the increase in circuit scale and processing time for automatically performing test pattern creation.

The semiconductor integrated circuit designing method according to the second and third aspects of the present invention has, in addition to the function of the first aspect, whether or not the flip-flop circuit is present in the feedback loop with reference to the flip-flop circuit. Therefore, it is possible to select the flip-flop circuit to be replaced with the flip-flop circuit with the scan function in a short time.

According to the fourth aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit according to the present invention.
By forming a set of scan function-equipped flip-flop circuits that are sequentially and continuously connected by a scan chain, it is possible to suppress an increase in the number of external input units and external output units, that is, the circuit scale.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a basic flowchart of a method for designing a semiconductor integrated circuit according to an embodiment of the present invention, focusing on a feedback loop. The reason for paying attention to the feedback loop is that the operation of the circuit existing in the feedback loop depends on the signal fed back by the feedback loop, and the signal depends on the state of the output signal line of the circuit. This is because it is difficult to determine the output state due to the tour, and it is often difficult to create a test pattern that can detect a failure in the signal line.

In FIG. 1, step 11 is a step of detecting the flip-flop circuit in the connection information of the semiconductor integrated circuit incorporating the flip-flop circuit, and step 12 is that the flip-flop circuit detected in step 11 exists in the feedback loop. This is a step of determining whether or not to do it from the connection information. Whether or not a flip-flop circuit is present in the feedback loop depends on the signal flow or flip-flop, starting from the output of this flip-flop circuit until it reaches the external output or the input of the flip-flop circuit which has departed. The output section of the circuit, the signal line connected to this, and the input section of the circuit connected to this signal line are searched in this order. If the result of this search is that it has arrived at the input of the starting flip-flop circuit, it is determined that this flip-flop circuit is present in the feedback loop. On the other hand, if it is the external output unit that arrived,
This flip-flop circuit determines that it is not in the feedback loop. These steps 11 and 12 perform processing for all the flip-flop circuits, and the flip-flop circuits determined to be present in the feedback loop are the targets of the steps 13 to 17 below. Become.

Step 13 is a step of replacing the flip-flop circuit judged to exist in the feedback loop in step 12 with a flip-flop circuit having a scan function. At this time, one feedback
If there are a plurality of flip-flop circuits in the loop, only one arbitrary flip-flop circuit is replaced with the flip-flop circuit with the scan function. It should be noted that the same effect can be obtained by using a process of adding a scan input section and a switching input section to the flip-flop circuit instead of replacing the flip-flop circuit with the scan function.

Step 14 is a step of connecting at least one set of the data input section and the external input section of the flip-flop circuit with the scan function replaced in Step 13. Step 15 is a step of connecting the flip-flop circuits with the scan function with a scan chain to form a set of the flip-flop circuits with the scan function, which are successively connected from the external input section connected in step 14. Step 16 is a step of connecting the output part of the flip-flop circuit with the scan function at the final stage in the set of flip-flop circuits with the scan function formed in step 15 to the external output part.

The controllability and observability are excellent by forming several sets of flip-flop circuits with a scan function, which are sequentially and continuously connected from the external input section to the external output section by the connection in steps 14 to 16. It can be a semiconductor integrated circuit. That is, the output state of the flip-flop circuit with the scan function in the same set can be determined by the input state of the external input unit connected in step 14 by switching the switching input unit and performing the shift operation. (Hereinafter, referred to as scan-in) and can be observed by the external output unit.

The connections in steps 14 to 16 are roughly classified into a method of connecting all flip-flop circuits with a scan function in a scan chain and a method of not connecting any of them. The method of connecting all the scan function flip-flop circuits by the scan chain requires a large number of shift operations for setting the output state of the scan function flip-flop circuits, but the test pattern tends to be large. Since the number of external input units can be reduced, there is an advantage that an increase in circuit scale can be suppressed. On the other hand, in the method that does not connect all flip-flop circuits with a scan function in the scan chain, it is necessary to provide many external input units and external output units, which tends to increase the circuit scale.
Since the number of shift operations for setting the output state of the flip-flop circuit with the scan function is small, there is an advantage that the test pattern can be made small. If all scan function flip-flop circuits are connected by a scan chain, the position of the scan function flip-flop circuits in the manufactured semiconductor integrated circuit is likely to be different, and the scan-in timing is shifted. Causes a clock skew, and an erroneous signal is easily scanned in. In other words, considering two flip-flop circuits with a scan function connected by a scan chain, if the scan-in timing of the flip-flop circuit with a scan function in the first stage is much faster than that in the second stage,
The second-stage flip-flop circuit with a scan function is not an input signal to be originally scanned in, but the input signal scanned in by the first-stage flip-flop circuit with a scan function, that is, the second-stage flip-flop circuit with a scan function is Then, the input signal to be scanned in is scanned in. Therefore, in order to solve the above-mentioned problems, it is necessary to form as many sets of flip-flop circuits with a scan function connected by a scan chain as possible as long as the circuit scale is allowed to increase.

The order of steps 14 to 16 is not such that the same effect cannot be obtained unless the steps are followed.
The same effect can be obtained by either order.

Step 17 is a step of connecting the switching input sections of all the flip-flop circuits with the scan function to the external input sections. As a result, all flip-flop circuits with a scan function can be brought into a scan-in enabled state at the same time. Step 18 is Step 11
This is a step of executing the ATPG with respect to the connection information of the semiconductor integrated circuit designed by -17 to automatically create a test pattern.

FIG. 2 is a circuit diagram in which a flip-flop circuit is built in the feedback loop. Reference numeral 21 is a flip-flop circuit, 22 is an input portion of the flip-flop circuit 21, 23 is an output portion of the flip-flop circuit 21, and 24.
Is a logic circuit, 25 is an input part of the logic circuit 24, 26 is an output part of the logic circuit 24, 27 is a signal which connects the output part 23 of the flip-flop circuit 21 and the input part 25 of the logic circuit 24 to form a feedback loop. Line 28 is the logic circuit 2
4 and the input section 2 of the flip-flop circuit 21.
2 is a signal line for connecting the two. Further, 29 and 30 are flip-flop circuits existing in the feedback loop. Further, 31 is a flip-flop circuit, 32 is an output section of the flip-flop circuit 31, 33 is an external output section,
Reference numeral 34 is a signal line connecting the output section 32 of the flip-flop circuit 31 and the external output section 33, and 35 is a part of the semiconductor integrated circuit.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit using the method for designing a semiconductor integrated circuit according to this embodiment.
Is a flip-flop circuit with a scan function, 38 is an output part of the flip-flop circuit with a scan function 36, 3
Reference numerals 9 and 40 are scan input sections, 41 is a scan chain, 42 and 43 are switching input sections, 44 and 45 are external input sections, and 46 is an external output section.

When the method of designing a semiconductor integrated circuit of the present embodiment configured as shown in FIG. 1 is applied to the circuit of FIG. 2, the operation will be described below. The semiconductor integrated circuit of the present embodiment of FIG. An example of a semiconductor integrated circuit using the design method will be described.

First, in FIG. 2, the flip-flop circuit 21 is detected, and the signal line 27 connected to the output portion 23 of the flip-flop circuit 21 is searched for along the flow of signals.
When it reaches the input section 25, the signal line 28 connected to the output section 26 of the logic circuit 24 is searched for along the signal flow. At this time, the search is terminated because the input section 22 of the flip-flop circuit 21 that started the search is reached. In this case, the flip-flop circuit 21 determines that it exists in the feedback loop. Flip-flop circuit 29 and flip-flop circuit 3
Similarly for 0, it is determined that it exists in the feedback loop.

Next, the flip-flop circuit 31 is detected, and the signal line 34 connected to the output section 32 is searched for along the signal flow, but the search is terminated because the external output section 33 is reached. In this case, the external output unit 33
Since it has reached, it is determined that this flip-flop circuit is not in the feedback loop.

Next, the flip-flop circuit 21 which is determined to be present in the feedback loop.
Is replaced with a flip-flop circuit 36 with a scan function (FIG. 3). However, the flip-flop circuits 29, 3
Since 0 exists in one feedback loop, only the flip-flop circuit 30 is replaced by the flip-flop circuit 37 with a scan function. In addition,
Only the flip-flop circuit 29 may be replaced.

Next, the external input section 44 and the scan input section 40 of the flip-flop circuit 36 with a scan function are connected.

Further, the output part 38 of the flip-flop circuit 36 with the scan function and the scan input part 39 of the flip-flop circuit 37 with the scan function which are replaced are connected by a scan chain 41. If the compression of the test pattern is emphasized, the output unit 38 and the scan input unit 39 may not be connected by the scan chain.

The scan function flip-flop circuit 3 which is the final stage of the set of scan function flip-flop circuits formed by the scan chain 41.
Since the output unit 7 is originally connected to the external output unit 46, no processing is performed.

Finally, the switching input sections 42 and 43 and the external input section 45 are connected. Thereby, the external input unit 45
The flip-flop circuits 36 and 37 with a scan function can be regarded as a series of flip-flop circuit groups by switching the switch, and the input signal applied to the external input section 44 can be easily flip-flop circuits 36 and 3 with a scan function.
7 output states. If the scan chains are not connected by placing importance on the compression of the test pattern, it is not necessary to scan in at the same time, and it is not always necessary to connect the switching input units 42 and 43 and the external input unit 45.

The test in the semiconductor integrated circuit manufactured based on the design of one embodiment of the present invention as described above is performed by the flip-flop with a scan function in which the test pattern given to the external input section 44 is directly present in the feedback loop. Since it is possible to scan into the circuits 36 and 37, the signal to be fed back can be easily determined by the feedback loop. Further, according to this configuration, the output state of the circuit existing in the feedback loop can be forcibly set at the time of the test and can be observed, so that the test with a high failure detection rate can be easily performed. It becomes possible.

As described above, according to the present embodiment, by replacing only the flip-flop circuit existing in the feedback loop with the flip-flop circuit having the scan function, the test for achieving the target fault coverage in a short time. It is possible to automatically create a pattern and to limit the increase in circuit scale for that purpose to the minimum necessary. In particular, since the flip-flop circuit is used as a reference to judge whether or not it exists in the feedback loop, the flip-flop circuit to be replaced with the flip-flop circuit with the scan function can be selected in a shorter time. Also,
The number of external input units and external output units can be further reduced by sequentially connecting flip-flop circuits with a scan function by a scan chain to form a set. Furthermore, when there are multiple flip-flop circuits in one feedback loop, only one of them is replaced by the flip-flop circuit with scan function, so the circuit scale is larger than the method of replacing all of them. Can be suppressed.

[0033]

According to the present invention, by replacing only the flip-flop circuit existing in the feedback loop with the flip-flop circuit having the scan function, a test pattern for achieving a target fault coverage in a short time is automatically created. In addition, the present invention realizes an excellent method for designing a semiconductor integrated circuit that can minimize the increase in circuit scale for that purpose.

[Brief description of drawings]

FIG. 1 is a basic flow chart of a method for designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram in which a flip-flop circuit is incorporated in a feedback loop.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit using a method for designing a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 4 is a basic flow chart of a conventional method of designing a semiconductor integrated circuit by a partial scan design method.

[Explanation of symbols]

 21 flip-flop circuit 22 input section 23 output section 24 logic circuit 25 input section 26 output section 27, 28 signal line 29 to 31 flip-flop circuit 32 output section 33 external output section 34 signal line 35 part of semiconductor integrated circuit 36, 37 Flip flip circuit with scan function 38 Output unit 39, 40 Scan input unit 41 Scan chain 42, 43 Switching input unit 44, 45 External input unit 46 External output unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location D

Claims (5)

[Claims] 1. In connection information of a semiconductor integrated circuit having a feedback loop in the circuit, if the first flip-flop circuit exists in the feedback loop, the first flip-flop circuit is used for data. A method for designing a semiconductor integrated circuit, comprising the step of forming a second flip-flop circuit by replacing the input section and the data input section to be used with a flip-flop circuit having a switchable input section. . 2. A step of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit in the connection information of the semiconductor integrated circuit having a feedback loop in the circuit, and the first flip-flop circuit comprising: A data input using a step of determining whether or not it is present in the feedback loop, and a first flip-flop circuit determined to be present in the feedback loop in the determining step as a data input section. A second flip-flop circuit by replacing the unit with a flip-flop circuit having a switchable input unit. 3. A step of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit in the connection information of the semiconductor integrated circuit having a feedback loop in the circuit, and the first flip-flop circuit comprising: A step of determining whether or not it is present in the feedback loop, and a first flip-flop circuit determined to be present in the feedback loop in the step of determining are input to data and an input for data to be used. By adding a switching input section capable of switching the second section,
And a step of forming the flip-flop circuit. 4. A step of detecting all the first flip-flop circuits included in the semiconductor integrated circuit in the connection information of the semiconductor integrated circuit having a feedback loop in the circuit, and the first flip-flop circuit comprising: A data input using a step of determining whether or not it is present in the feedback loop, and a first flip-flop circuit determined to be present in the feedback loop in the determining step as a data input section. A second flip-flop circuit by replacing the part with a flip-flop circuit having a switchable input part, and at least one external set when there are a plurality of the second flip-flop circuits. A step of connecting an input part and a data input part of the second flip-flop circuit; The second flip-flop circuit sequentially and continuously connected to the external input unit by connecting the output unit of the second flip-flop circuit to the data input unit of the other one of the second flip-flop circuits. And a step of connecting an output part of the second flip-flop circuit at the final stage to an external output part in the set of the second flip-flop circuits connected in series successively. And a step of connecting the switching input unit of the second flip-flop circuit to an external input unit. 5. A step of detecting all the first flip-flop circuits contained in the semiconductor integrated circuit in the connection information of the semiconductor integrated circuit having a feedback loop in the circuit, and the first flip-flop circuit comprising: A data input using a step of determining whether or not it is present in the feedback loop, and a first flip-flop circuit determined to be present in the feedback loop in the determining step as a data input section. By adding a switching input section capable of switching the second section,
Of the second flip-flop circuit, and at least one of the second flip-flop circuits is provided.
Connecting a pair of external input units and a data input unit of the second flip-flop circuit, and an output unit of one of the second flip-flop circuits and data of another one of the second flip-flop circuits. By connecting the input section for
Forming a set of the second flip-flop circuits sequentially connected to the external input section, and the second stage at the final stage in the set of second flip-flop circuits connected in the continuous sequence. A semiconductor integrated circuit comprising: a step of connecting an output section of the flip-flop circuit and an external output section; and a step of connecting all the switching input sections of the second flip-flop circuits to the external input section. Design method.