JP2017106826A - Scan test circuit generation device and scan test circuit generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan test circuit generation device and a scan test circuit generation method with which it is possible to suppress an increase in circuit scale when generating a scan test circuit in which FFs of shift structure having a branch in the middle are scanned.SOLUTION: A scan test circuit generation device is constituted so as to include: circuit analysis means for analyzing a circuit constituted by a plurality of flip-flops; non-scanized object determination means for determining at least some of the flip-flops as being excluded from alteration to scan flip-flops having a scannable structure; and scanization means for altering the flip-flops, out of the plurality of flip-flops, which were not determined as being excluded from scanization, to scan flip-flops, and generating a scan chain in which the scan flip-flops are cascaded.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a scan test circuit generation device and a scan test circuit generation method.

  As a design technique (DFT: Design For Testability) that facilitates testing of a semiconductor integrated circuit, a circuit that allows setting and reading of a value to a flip-flop (hereinafter also referred to as “FF”) is added. There is a scanning method. As one of the scanning methods, a FF that is a target for setting and reading a value is corrected to a scannable structure (hereinafter also referred to as “scanning”), and the scanned FF (scan flip-flop, hereinafter referred to as “SFF”) is scanned. There is also a shift scan method in which a scan chain is connected in a chain shape. FIG. 4B shows an example of configuring a scan test circuit in which a shift-structured FF is scanned, details of which will be described later.

  When scanning a circuit with a shift configuration in which FFs are connected in series, only the first and last FFs are scanned and the FFs are not scanned between them, thereby suppressing the increase in test circuits. It is known to be possible. FIG. 5 shows an example of configuring a scan test circuit in which only the first and last FFs are scanned, details of which will be described later.

  Patent Document 1 describes a scan test circuit that includes a scan flip-flop and a flip-flop, and includes a selector that switches data input to the flip-flop between a capture operation, a shift operation, and a normal operation.

  The configuration of the FF is not limited to a complete shift configuration connected in series. For example, there may be a branched configuration in which the output of another logic circuit is input in addition to the output of the previous stage. When scanning such a configuration, since it is not a complete shift configuration, all the included FFs are scanned, resulting in a problem that the circuit scale increases.

  The present invention has been made to solve the above-described problems, and can suppress an increase in circuit scale when generating a scan test circuit in which a FF having a shift structure having a branch in the middle is scanned. An object of the present invention is to provide a scan test circuit generation device and a scan test circuit generation method.

In order to solve the above-described problem, a scan test circuit generation device according to the present invention includes:
Circuit analysis means for analyzing a circuit composed of a plurality of flip-flops;
Non-scanning target judging means for judging that the flip-flop has a structure capable of scanning at least a part of the flip-flop, and that is not subject to change.
Of the plurality of flip-flops, the flip-flops that are not determined to be excluded from the scan target are changed to the scan flip-flops, and a scan unit that generates a scan chain in which the scan flip-flops are cascade-connected,
It is characterized by having.

  The scan test circuit generation device and the scan test circuit generation method according to the present invention can suppress an increase in circuit scale when generating a scan test circuit obtained by scanning a FF having a shift structure having a branch in the middle.

1 is a hardware configuration diagram of a scan test circuit generation device 1 according to an embodiment of the present invention. 1 is a functional block diagram of a scan test circuit generation device 1 according to an embodiment of the present invention. It is a schematic block diagram of a flip-flop and a scan flip-flop. It is an example of the circuit of the shift structure, and the circuit which made it scan by the prior art. This is an example in which only the first and last flip-flops of the shift configuration are scanned by the prior art. This is a circuit configuration in which a circuit having a branch between flip-flops and connected to a logic circuit is scanned by a conventional technique. 1 is a first example of a circuit configuration in which a circuit having a branch between flip-flops and connected to a logic circuit is scanned according to the present invention. It is the 2nd example of the circuit structure which made the scan according to this invention which has the branch between flip-flops, and the circuit to which the logic circuit was connected. This is an example of a circuit configuration in which a circuit having a branch between flip-flops and connected to another shift configuration is scanned according to the present invention. It is an example of the circuit structure which scanned the circuit containing the path | route which has an asynchronous relationship by the prior art. It is an example of the circuit configuration which scanned the circuit containing the path | route which has an asynchronous relationship by this invention. It is a flowchart of a scan test circuit generation process in the scan test circuit generation device 1 of the present embodiment.

  First, the hardware configuration of the scan test circuit generation device 1 according to the embodiment of the present invention will be described. FIG. 1 is a hardware configuration diagram of a scan test circuit generation device 1 according to an embodiment of the present invention. As shown in FIG. 1, the scan test circuit generation device 1 according to the embodiment of the present invention includes an information processing unit 10, a storage unit 20, an input unit 30, and an output unit 40.

  The information processing unit 10 performs an operation on a code included in the program, and executes various processes described later by the operation. The information processing unit 10 can be configured by a processor such as a CPU that executes a program read into a memory.

  The storage unit 20 stores predetermined information in a nonvolatile manner and reads it as necessary. The storage unit 20 can store, for example, data before scan test circuit generation, data after generation, a scan test circuit generation program, and the like. The storage unit 20 can be configured by an HDD (Hard Disk Drive), an SSD (Solid State Drive), or the like.

  The input unit 30 inputs data to be processed by the information processing unit 10 and an instruction to execute the information processing. The input unit 30 can be configured by a data interface such as a connector and a driver conforming to an existing connection standard such as USB (registered trademark) or SD memory card (registered trademark), or a user interface such as a keyboard or a pointing device. is there.

  The output unit 40 outputs the processing result of the information processing unit 10. The processing result is, for example, a generated scan test circuit, and is output as a data file. The output unit 40 can be configured by a data interface such as a connector and a driver conforming to an existing connection standard such as USB (registered trademark) or SD memory card (registered trademark), or a device such as a display or a printer.

  Subsequently, functional blocks of the scan test circuit generation device 1 according to the embodiment of the present invention will be described. FIG. 2 is a functional block diagram of the scan test circuit generation device 1 according to the embodiment of the present invention. As shown in FIG. 2, the scan test circuit generation device 1 includes a circuit analysis unit 100, a non-scan target determination unit 110, and a scan unit 120.

  The circuit analysis unit 100 analyzes a circuit composed of a plurality of flip-flops. As circuit analysis, the circuit analysis means 100 can specify a shift configuration in which a plurality of flip-flops are cascade-connected. The circuit analysis unit 100 can be implemented by executing a predetermined program in the information processing unit 10.

  The non-scanning target determination unit 110 determines that at least a part of the flip-flops analyzed by the circuit analysis unit 100 is out of the change to the scan flip-flops. The scan flip-flop is a circuit in which a scanable structure is added to the flip-flop, and details will be described later. The non-scan target determination unit 110 can be implemented by executing a predetermined program in the information processing unit 10.

  The configuration of the flip-flop and the scan flip-flop will be described with reference to FIG. FIG. 3 is a schematic configuration diagram of a flip-flop and a scan flip-flop. FIG. 3A shows a flip-flop, where D is a data input, CK is a clock, and Q is a data output. FIG. 3B shows a scan flip-flop scanned by a multiplexer method, and is configured by adding a MUX (multiplexer) to the flip-flop. The configuration of the scan flip-flop is not limited to the multiplexer method, and can be configured by an LSSD (Level Sensitive Scan Design) method. Here, SIN indicates a scan input, and SE indicates a scan enable. FIG. 3C is a simplified representation of the scan flip-flop circuit.

  Scanning means 120 changes a flip-flop that has not been determined to be a scan target to a scan flip-flop, and cascades the scan flip-flops to generate a scan chain. The scanning unit 120 can be implemented by executing a predetermined program in the information processing unit 10.

  Here, generation of a scan test circuit based on a specific circuit will be described. FIG. 4 is an example of a circuit having a shift configuration and a circuit obtained by scanning the circuit with a conventional technique. FIG. 4A shows a shift configuration in which seven flip-flops are connected in cascade. FIG. 4B shows a configuration in which all flip-flops in this configuration are scanned by the prior art and changed to scan flip-flops. In FIG. 4B, the bold line that continues from the left SIN to the right end indicates the scan chain.

  FIG. 5 shows an example in which only the first and last flip-flops of the shift configuration of FIG. The first flip-flop and the last flip-flop are connected by a thick line to form a scan chain.

  In the configuration of FIG. 5, a value cannot be directly set to a flip-flop that has not been scanned. However, when a value is set in the first scan flip-flop and a CLK cycle for a predetermined number of stages elapses, the value is propagated to a desired flip-flop, so that a scan test is possible.

  FIG. 6 shows a circuit configuration in which a circuit having a branch between flip-flops and connected to a logic circuit is scanned by a conventional technique. In the circuit before being scanned as shown in FIG. 6, the data output of one flip-flop is connected to the data input of the next flip-flop, and the circuit is branched between them, followed by another logic. The circuit is connected. In FIG. 6, all flip-flops having a continuous shift structure starting from the leftmost SIN are scanned. This is because the circuit is not recognized as a shift configuration due to a branch in the circuit. In FIG. 6, the description of the scan chain at the branch destination is omitted, and the same applies to the following.

  FIG. 7 is a first example of a circuit configuration in which a circuit having a branch between flip-flops and connected to a logic circuit is scanned according to the present invention. In FIG. 7, only the first and last flip-flops of the shift configuration are scanned, although the logic circuit is branched and connected. Since the shift configuration is specified by back-tracing the flip-flops in which other flip-flops are cascade-connected in order from the flip-flops in which the flip-flops are not cascade-connected, such scanning can be performed.

  In the configuration of FIG. 7, the data output of the first scan flip-flop and the scan data input of the last scan flip-flop are connected to form a scan chain. The configuration of FIG. 5 is that a scan test of a desired flip-flop that has not been scanned can be performed by setting a value in the first scan flip-flop and elapse of a predetermined number of CLK cycles. It is the same.

  FIG. 8 shows a second example of a circuit configuration in which a circuit having a branch between flip-flops and connected to a logic circuit is scanned according to the present invention. In FIG. 8, flip-flops other than one flip-flop between the beginning and the end of the shift configuration are not targeted for scanning. That is, one flip-flop between the head and the tail of the shift configuration is scanned.

  In the configuration of FIG. 8, the scan data input of the first scan flip-flop between the data output of the first scan flip-flop is connected. Also, the data output of the last one of the scan flip-flops in between is connected to the scan data input of the last scan flip-flop. In the configuration of FIG. 8, since there is one scan flip-flop between the first scan flip-flop and the last scan flip-flop, the first and last scan flip-flops are the same. When there are two or more scan flip-flops between them, a scan chain is formed in the same manner in a cascade connection. Since the scan chain formed in this way shortens the CLK cycle in which the value propagates to the flip-flop near the tail end, the test time can be shortened.

  The non-scan target determination unit 110 may not exclude the scan from the first flip-flop every predetermined number, or may not exclude the flip-flop at a predetermined position, such as between the top and the end, from the scan target. By doing so, such a configuration becomes possible. In the example of FIG. 8, one flip-flop other than the head and tail is scanned, but the number of flip-flops scanned other than the head and tail is not limited to this.

  FIG. 9 shows an example of a circuit configuration in which a circuit having a branch between flip-flops and connected to another shift configuration is scanned according to the present invention. Unlike the circuit assumed in the description of FIGS. 6 to 8, in the example of FIG. 9, another shift configuration is connected at the end of the branch between the flip-flops. Even in such a configuration, it is possible to appropriately grasp that the shift configurations are merged by back-tracing those that are cascade-connected in order from the last flip-flop of the shift configuration.

  FIG. 10 is an example of a circuit configuration obtained by scanning a circuit including paths in an asynchronous relationship with the conventional technique. A part surrounded by a broken line is provided with a plurality of stages of flip-flops so that an output of a combinational circuit operating asynchronously with this part can be received at an appropriate timing. A plurality of flip-flops have a shift configuration, but in the prior art, all flip-flops are scanned, and a lock-up cell is inserted to secure a hold time and adjust timing.

  FIG. 11 shows an example of a circuit configuration obtained by scanning a circuit including paths in an asynchronous relationship according to the present invention. The flip-flop in the part surrounded by the broken line is shifted only at the beginning and the end of the shift structure. The circuit analysis unit 100 detects a circuit configuration that operates asynchronously with the shift configuration. As a result, the scanning unit 120 inserts the lock-up cell into the scan chain connecting the data output of the first scan flip-flop and the scan data input of the last scan flip-flop.

  Next, the operation of the scan test circuit generation device 1 of this embodiment will be described. FIG. 12 is a flowchart of scan test circuit generation processing in the scan test circuit generation device 1 of the present embodiment. Referring to FIG. 12, the scan test circuit generation device 1 of the present embodiment first analyzes a circuit (step S1). Circuit analysis is performed by the circuit analysis unit 100, and the circuit to be analyzed is input from the input unit 30. Analysis of the circuit identifies the shift configuration.

  Subsequently, the scan test circuit generation device 1 determines that at least a part of the flip-flops included in the circuit analyzed in step S1 is not subject to change to the scan flip-flop (step S2). The non-scan target is determined by the non-scan target determining unit 110. The non-scanning target judging means 110 can judge that flip-flops other than the head and tail in the shift configuration in which a plurality of flip-flops are connected in cascade are not subject to scanning.

  Next, the scan test circuit generation device 1 scans the flip-flops that are not determined to be excluded from scanning in step S2 and changes them to scan flip-flops, and cascades the changed scan flip-flops to form a scan chain. (Step S3). The scanning unit 120 executes scanning and forming a scan chain.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications, within the scope of the gist of the present invention described in the claims, It can be changed.

DESCRIPTION OF SYMBOLS 1 Scan test circuit production | generation apparatus 10 Information processing part 20 Memory | storage part 30 Input part 40 Output part 100 Circuit analysis means 110 Non-scanning object judgment means 120 Scanning means

JP 2010-223672-A

Claims (10)

Circuit analysis means for analyzing a circuit composed of a plurality of flip-flops;
Non-scanning target judging means for judging that the flip-flop has a structure capable of scanning at least a part of the flip-flop, and that is not subject to change.
Of the plurality of flip-flops, the flip-flops that are not determined to be excluded from the scan target are changed to the scan flip-flops, and a scan unit that generates a scan chain in which the scan flip-flops are cascade-connected,
A scan test circuit generation device comprising:   The circuit analysis means specifies a shift configuration in which a data output of one flip-flop is cascade-connected to a data input of another flip-flop and is configured by a plurality of the flip-flops. The scan test circuit generation device according to 1.   The circuit analysis means specifies the shift configuration by back-tracing the data outputs that are cascaded in order from the flip-flops that are not connected to the data inputs of the other flip-flops. The scan test circuit generation device according to claim 2.   In the circuit analysis means, when the connection between the data output of the one flip-flop and the data input of the other flip-flop is branched, the one flip-flop and the other flip-flop are cascaded. The scan test circuit generation device according to claim 2, wherein the scan test circuit generation device is handled as at least a part of the shift configuration.   5. The non-scanning object determination unit determines that the flip-flops other than the first and last ones out of the flip-flops included in the shift configuration are excluded from the object. 2. A scan test circuit generation device according to item 1.   The non-scanning target judging means judges that the flip-flops excluding at least one of the flip-flops between the head and the tail of the flip-flops included in the shift configuration are out of scope. The scan test circuit generation device according to claim 5, wherein   7. The scanning means connects the changed data output of the first scan flip-flop and the changed scan data input of the last scan flip-flop. A scan test circuit generation device according to claim 1.   The scanning unit connects the changed data output of the first scan flip-flop to the scan data input of the first of the changed at least one scan flip-flop, and changes at least one changed 7. The scan test circuit generation device according to claim 6, wherein the data output of the last one of the scan flip-flops is connected to the scan data input of the last scan flip-flop that has been changed. When the circuit analysis means detects a circuit configuration that operates asynchronously with the shift configuration,
The scan means includes inserting a lock-up cell into a scan chain connecting a data output of the first scan flip-flop and a scan data input of the last scan flip-flop. The scan test circuit generation device according to 5. A circuit analysis process for analyzing a circuit composed of a plurality of flip-flops;
A non-scanning target determining step for determining that the flip-flop is not subject to change to a scan flip-flop having a structure capable of scanning at least a part of the flip-flop;
Of the plurality of flip-flops, changing the flip-flops that are not determined to be scanned into the scan flip-flops to generate a scan chain; and
A scan test circuit generation method comprising:

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